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fix some ia64 vector failures
- From: Richard Henderson <rth at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Tue, 28 Jun 2005 00:47:22 -0700
- Subject: fix some ia64 vector failures
Exposed by new reduction tests.
r~
* config/ia64/ia64.c (ia64_expand_vcondu_v2si): Generate proper
comparison operations.
(ia64_expand_vecint_minmax): Fix size of xops.
* config/ia64/vect.md (umax<VECINT>3): Fix fallback pattern typo.
(vec_shl_<VECINT>, vec_shr_<VECINT>): New.
Index: config/ia64/ia64.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/ia64/ia64.c,v
retrieving revision 1.381
diff -u -p -d -r1.381 ia64.c
--- config/ia64/ia64.c 25 Jun 2005 01:21:26 -0000 1.381
+++ config/ia64/ia64.c 28 Jun 2005 07:43:08 -0000
@@ -1533,11 +1533,13 @@ ia64_expand_vcondu_v2si (enum rtx_code c
/* With the results of the comparisons, emit conditional moves. */
dl = gen_reg_rtx (SImode);
- x = gen_rtx_IF_THEN_ELSE (SImode, bl, op1l, op2l);
+ x = gen_rtx_NE (VOIDmode, bl, const0_rtx);
+ x = gen_rtx_IF_THEN_ELSE (SImode, x, op1l, op2l);
emit_insn (gen_rtx_SET (VOIDmode, dl, x));
dh = gen_reg_rtx (SImode);
- x = gen_rtx_IF_THEN_ELSE (SImode, bh, op1h, op2h);
+ x = gen_rtx_NE (VOIDmode, bh, const0_rtx);
+ x = gen_rtx_IF_THEN_ELSE (SImode, x, op1h, op2h);
emit_insn (gen_rtx_SET (VOIDmode, dh, x));
/* Merge the two partial results back into a vector. */
@@ -1613,7 +1615,7 @@ bool
ia64_expand_vecint_minmax (enum rtx_code code, enum machine_mode mode,
rtx operands[])
{
- rtx xops[5];
+ rtx xops[6];
/* These four combinations are supported directly. */
if (mode == V8QImode && (code == UMIN || code == UMAX))
Index: config/ia64/vect.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/ia64/vect.md,v
retrieving revision 1.7
diff -u -p -d -r1.7 vect.md
--- config/ia64/vect.md 25 Jun 2005 01:21:29 -0000 1.7
+++ config/ia64/vect.md 28 Jun 2005 07:43:08 -0000
@@ -214,7 +214,7 @@
(define_expand "umax<mode>3"
[(set (match_operand:VECINT 0 "gr_register_operand" "")
- (smax:VECINT (match_operand:VECINT 1 "gr_register_operand" "")
+ (umax:VECINT (match_operand:VECINT 1 "gr_register_operand" "")
(match_operand:VECINT 2 "gr_register_operand" "")))]
""
{
@@ -311,6 +311,26 @@
"pshr<vecsize>.u %0 = %1, %2"
[(set_attr "itanium_class" "mmshf")])
+(define_expand "vec_shl_<mode>"
+ [(set (match_operand:VECINT 0 "gr_register_operand" "")
+ (ashift:DI (match_operand:VECINT 1 "gr_register_operand" "")
+ (match_operand:DI 2 "gr_reg_or_6bit_operand" "")))]
+ ""
+{
+ operands[0] = gen_lowpart (DImode, operands[0]);
+ operands[1] = gen_lowpart (DImode, operands[1]);
+})
+
+(define_expand "vec_shr_<mode>"
+ [(set (match_operand:VECINT 0 "gr_register_operand" "")
+ (lshiftrt:DI (match_operand:VECINT 1 "gr_register_operand" "")
+ (match_operand:DI 2 "gr_reg_or_6bit_operand" "")))]
+ ""
+{
+ operands[0] = gen_lowpart (DImode, operands[0]);
+ operands[1] = gen_lowpart (DImode, operands[1]);
+})
+
(define_expand "vcond<mode>"
[(set (match_operand:VECINT 0 "gr_register_operand" "")
(if_then_else:VECINT