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Re: [PATCH] RS6000 : Tidy up vector splat instructions
- From: Aldy Hernandez <aldyh at redhat dot com>
- To: Devang Patel <dpatel at apple dot com>
- Cc: gcc-patches <gcc-patches at gcc dot gnu dot org>
- Date: 17 Jun 2005 12:39:33 -0400
- Subject: Re: [PATCH] RS6000 : Tidy up vector splat instructions
- References: <D940FE6B-9630-4997-B345-E54F172CE481@apple.com>
>>>>> "Devang" == Devang Patel <firstname.lastname@example.org> writes:
> This patch adds two new predicates to check 5 bit signed and
> unsigned integers. altivec.md is updated to use them
> appropriately. I ran into this while moving large altivec
> code to gcc-4.0. Sometimes optimizer generates
> vspltisb v18,-128
> at high optimization level. The test case I used to fix GCC-4.0
> does not compile using mainline sources because of regressions
> (? need to verify).
> 2005-06-14 Devang Patel <email@example.com>
> * config/rs6000/predicates.md (s5bit_cint_operand,
> New predicates.
> * config/rs6000/altivec.md (altivec_vspltb, altivec_vsplth,
> altivec_vspltw, altivec_vspltis<VI_char>,
> altivec_vspltisw_v4sf): Use new
> 5bit constant operand predicates.
> * config/rs6000/rs6000.c (rs6000_expand_unop_builtin): Fix
> signed 5bit
> constant check.
This look good, but I'd really like a testcase. Can you distill
something from your big source base?