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RFA: Fix MN10300 support for bit operations on address registers


Hi Jeff, Hi Alex,

  I worked out what was wrong with my attempts to synthesise a bit
  operation on an address register for the MN10300, so I now have a
  patch that works for both the AM33 and MN10300 (attached).

  I checked for regressions by building an mn10300-elf and running
  the gcc testsuite - no changes.  I also built an am33_2-linux-gnu
  toolchain and ran the gcc testsuite - again there were no
  regressions.

  Please may I apply this patch ?

  I am also attaching a second patch which adds a testcase to the gcc
  testsuite for the code that triggered this bug.  I have extended the
  test to include the AND and XOR bit-operators.  This patch is
  independent of the first patch although ideally they should be
  committed together.

  Please may I apply this second patch ?
  
Cheers
  Nick

gcc/ChangeLog
2005-06-14  Nick Clifton  <nickc@redhat.com>

	* config/mn10300/mn10300.md (am33 andsi3 insn): Allow an integer
	value in the third alternative.
	(am33 iorsi3 insn): Allow an integer value in the second
	alternative. 
	(am33 xorsi3 insn): Likewise.
	(mn10300 andsi3 insn): Add a new alternative to handle address
	registers and an integer value.
	(mn10300 iorsi3 insn): Likewise.
	(mn10300 xorsi3 insn): Likewise.

gcc/testsuite/ChangeLog
2005-06-14  Nick Clifton  <nickc@redhat.com>

	* gcc.c-torture/compile/20050614-1.c: New.

Index: gcc/config/mn10300/mn10300.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mn10300/mn10300.md,v
retrieving revision 1.60
diff -c -3 -p -r1.60 mn10300.md
*** gcc/config/mn10300/mn10300.md	8 May 2005 09:37:17 -0000	1.60
--- gcc/config/mn10300/mn10300.md	14 Jun 2005 11:37:47 -0000
***************
*** 1183,1189 ****
  (define_insn ""
    [(set (match_operand:SI 0 "register_operand" "=dx,dx,!dax")
  	(and:SI (match_operand:SI 1 "register_operand" "%0,0,dax")
! 		(match_operand:SI 2 "nonmemory_operand" "N,dxi,dax")))]
    "TARGET_AM33"
    "*
  {
--- 1183,1189 ----
  (define_insn ""
    [(set (match_operand:SI 0 "register_operand" "=dx,dx,!dax")
  	(and:SI (match_operand:SI 1 "register_operand" "%0,0,dax")
! 		(match_operand:SI 2 "nonmemory_operand" "N,dxi,daxi")))]
    "TARGET_AM33"
    "*
  {
***************
*** 1241,1252 ****
  	  ] (const_string "set_znv")))])
  
  (define_insn ""
!   [(set (match_operand:SI 0 "register_operand" "=dx,dx")
! 	(and:SI (match_operand:SI 1 "register_operand" "%0,0")
! 		(match_operand:SI 2 "nonmemory_operand" "N,dxi")))]
    ""
    "*
  {
    if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xff)
      return \"extbu %0\";
    if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xffff)
--- 1241,1254 ----
  	  ] (const_string "set_znv")))])
  
  (define_insn ""
!   [(set (match_operand:SI 0 "register_operand" "=dx,dx,!a")
! 	(and:SI (match_operand:SI 1 "register_operand" "%0,0,0")
! 		(match_operand:SI 2 "nonmemory_operand" "N,dxi,i")))]
    ""
    "*
  {
+    if (which_alternative == 2)
+     return \"add -4, sp; mov d0, (sp); mov %1, d0; and %2, d0; mov d0, %0; mov (sp), d0; add 4, sp\";
    if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xff)
      return \"extbu %0\";
    if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 0xffff)
***************
*** 1305,1311 ****
  (define_insn ""
    [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
  	(ior:SI (match_operand:SI 1 "register_operand" "%0,dax")
! 		(match_operand:SI 2 "nonmemory_operand" "dxi,dax")))]
    "TARGET_AM33"
    "*
  {
--- 1307,1313 ----
  (define_insn ""
    [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
  	(ior:SI (match_operand:SI 1 "register_operand" "%0,dax")
! 		(match_operand:SI 2 "nonmemory_operand" "dxi,daxi")))]
    "TARGET_AM33"
    "*
  {
***************
*** 1328,1338 ****
    [(set_attr "cc" "set_znv")])
  
  (define_insn ""
!   [(set (match_operand:SI 0 "register_operand" "=dx")
! 	(ior:SI (match_operand:SI 1 "register_operand" "%0")
! 		(match_operand:SI 2 "nonmemory_operand" "dxi")))]
    ""
!   "or %2,%0"
    [(set_attr "cc" "set_znv")])
  
  ;; ----------------------------------------------------------------------
--- 1330,1342 ----
    [(set_attr "cc" "set_znv")])
  
  (define_insn ""
!   [(set (match_operand:SI 0 "register_operand" "=dx,!a")
! 	(ior:SI (match_operand:SI 1 "register_operand" "%0,0")
! 		(match_operand:SI 2 "nonmemory_operand" "dxi,i")))]
    ""
!   "@
!   or %2,%0
!   add -4, sp; mov d0, (sp); mov %1, d0; or %2, d0; mov d0, %0; mov (sp), d0; add 4, sp"
    [(set_attr "cc" "set_znv")])
  
  ;; ----------------------------------------------------------------------
***************
*** 1349,1355 ****
  (define_insn ""
    [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
  	(xor:SI (match_operand:SI 1 "register_operand" "%0,dax")
! 		(match_operand:SI 2 "nonmemory_operand" "dxi,dax")))]
    "TARGET_AM33"
    "*
  {
--- 1353,1359 ----
  (define_insn ""
    [(set (match_operand:SI 0 "register_operand" "=dx,!dax")
  	(xor:SI (match_operand:SI 1 "register_operand" "%0,dax")
! 		(match_operand:SI 2 "nonmemory_operand" "dxi,daxi")))]
    "TARGET_AM33"
    "*
  {
***************
*** 1372,1382 ****
    [(set_attr "cc" "set_znv")])
  
  (define_insn ""
!   [(set (match_operand:SI 0 "register_operand" "=dx")
! 	(xor:SI (match_operand:SI 1 "register_operand" "%0")
! 		(match_operand:SI 2 "nonmemory_operand" "dxi")))]
    ""
!   "xor %2,%0"
    [(set_attr "cc" "set_znv")])
  
  ;; ----------------------------------------------------------------------
--- 1376,1388 ----
    [(set_attr "cc" "set_znv")])
  
  (define_insn ""
!   [(set (match_operand:SI 0 "register_operand" "=dx,!a")
! 	(xor:SI (match_operand:SI 1 "register_operand" "%0,0")
! 		(match_operand:SI 2 "nonmemory_operand" "dxi,i")))]
    ""
!   "@
!   xor %2,%0
!   add -4, sp; mov d0, (sp); mov %1, d0; xor %2, d0; mov d0, %0; mov (sp), d0; add 4, sp"
    [(set_attr "cc" "set_znv")])
  
  ;; ----------------------------------------------------------------------
--- /dev/null	2004-06-24 19:04:38.000000000 +0100
+++ gcc/testsuite/gcc.c-torture/compile/20050614-1.c	2005-06-14 12:45:28.000000000 +0100
@@ -0,0 +1,29 @@
+/* These functions triggered an "insn does not match its constraints"
+   ICE for the MN10300 port, because __builtin_frame_address() returns
+   its value in an address register and bit manipulation operations
+   were only supported on data registers.  */
+
+unsigned long
+f_or (void)
+{
+  char * sp = __builtin_frame_address (0);
+
+  return * (unsigned long *) ((unsigned long) sp | 2);
+}
+
+unsigned long
+f_xor (void)
+{
+  char * sp = __builtin_frame_address (0);
+
+  return * (unsigned long *) ((unsigned long) sp ^ 2);
+}
+
+unsigned long
+f_and (void)
+{
+  char * sp = __builtin_frame_address (0);
+ 
+  return * (unsigned long *) ((unsigned long) sp & 0xffff00);
+}
+

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