This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

Re: PATCH - Fix an ICE compiling for ppc64


	The patch no longer was correct after other recent changes and
should not have been applied.  Committing parts of the patch did not
demonstrate good judgment.

	I have reverted the patch and replaced it to utilize the new
scc_eq_operand predicate.


David

	Revert scc_operand patch.
	* config/rs6000/predicates.md (scc_operand): Delete.
	* config/rs6000/rs6000.md (scc_operand): Change to scc_eq_operand.

Index: predicates.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/predicates.md,v
retrieving revision 1.18
diff -c -p -r1.18 predicates.md
*** predicates.md	12 Jun 2005 03:43:09 -0000	1.18
--- predicates.md	13 Jun 2005 15:47:44 -0000
***************
*** 132,148 ****
    (ior (match_code "const_int")
         (match_operand 0 "gpc_reg_operand")))
  
- ;; Return 1 if op is an integer meeting one of 'I','J','O','L'(TARGET_32BIT)
- ;; or 'J'(TARGET_64BIT) constraints or if it is a non-special register.
- (define_predicate "scc_operand"
-   (if_then_else (match_code "const_int")
-     (match_test "CONST_OK_FOR_LETTER_P (INTVAL (op), 'I')
- 		 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'K')
- 		 || CONST_OK_FOR_LETTER_P (INTVAL (op), 'O')
- 		 || CONST_OK_FOR_LETTER_P (INTVAL (op), 
- 					   (TARGET_32BIT ? 'L' : 'J'))")
-     (match_operand 0 "gpc_reg_operand")))
- 
  ;; Return 1 if op is a constant integer valid for addition
  ;; or non-special register.
  (define_predicate "reg_or_add_cint_operand"
--- 132,137 ----
Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.380
diff -c -p -r1.380 rs6000.md
*** rs6000.md	12 Jun 2005 03:43:12 -0000	1.380
--- rs6000.md	13 Jun 2005 15:47:44 -0000
***************
*** 11246,11252 ****
  (define_insn ""
    [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
  	(plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
! 			(match_operand:SI 2 "scc_operand" "r,O,K,L,I"))
  		 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
    "TARGET_32BIT"
    "@
--- 11246,11252 ----
  (define_insn ""
    [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r")
  	(plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
! 			(match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))
  		 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))]
    "TARGET_32BIT"
    "@
***************
*** 11263,11269 ****
  	(compare:CC
  	 (plus:SI
  	  (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
! 		 (match_operand:SI 2 "scc_operand" "r,O,K,L,I,r,O,K,L,I"))
  	  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
  	 (const_int 0)))
     (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
--- 11263,11269 ----
  	(compare:CC
  	 (plus:SI
  	  (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
! 		 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
  	  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
  	 (const_int 0)))
     (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))]
***************
*** 11287,11293 ****
  	(compare:CC
  	 (plus:SI
  	  (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
! 		 (match_operand:SI 2 "scc_operand" ""))
  	  (match_operand:SI 3 "gpc_reg_operand" ""))
  	 (const_int 0)))
     (clobber (match_scratch:SI 4 ""))]
--- 11287,11293 ----
  	(compare:CC
  	 (plus:SI
  	  (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
! 		 (match_operand:SI 2 "scc_eq_operand" ""))
  	  (match_operand:SI 3 "gpc_reg_operand" ""))
  	 (const_int 0)))
     (clobber (match_scratch:SI 4 ""))]
***************
*** 11306,11312 ****
  	(compare:CC
  	 (plus:SI
  	  (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
! 		 (match_operand:SI 2 "scc_operand" "r,O,K,L,I,r,O,K,L,I"))
  	  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
  	 (const_int 0)))
     (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
--- 11306,11312 ----
  	(compare:CC
  	 (plus:SI
  	  (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r")
! 		 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I"))
  	  (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r"))
  	 (const_int 0)))
     (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r")
***************
*** 11331,11337 ****
  	(compare:CC
  	 (plus:SI
  	  (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
! 		 (match_operand:SI 2 "scc_operand" ""))
  	  (match_operand:SI 3 "gpc_reg_operand" ""))
  	 (const_int 0)))
     (set (match_operand:SI 0 "gpc_reg_operand" "")
--- 11331,11337 ----
  	(compare:CC
  	 (plus:SI
  	  (eq:SI (match_operand:SI 1 "gpc_reg_operand" "")
! 		 (match_operand:SI 2 "scc_eq_operand" ""))
  	  (match_operand:SI 3 "gpc_reg_operand" ""))
  	 (const_int 0)))
     (set (match_operand:SI 0 "gpc_reg_operand" "")
***************
*** 11347,11353 ****
  (define_insn ""
    [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
  	(neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
! 		       (match_operand:SI 2 "scc_operand" "r,O,K,L,I"))))]
    "TARGET_32BIT"
    "@
     xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
--- 11347,11353 ----
  (define_insn ""
    [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r")
  	(neg:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r")
! 		       (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I"))))]
    "TARGET_32BIT"
    "@
     xor %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0


Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]