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fix ia64 gcc.dg/vect/vect-111.c


The vcondv2sf implementation was a stub when I first committed it, since
the support to use this pattern wasn't present in 4.0.


r~


        * config/ia64/ia64.c (update_set_flags): Just return for IF_THEN_ELSE.
        Use SCALAR_FLOAT_MODE_P.
        * config/ia64/vect.md (vcondv2sf): Remove code check on comparison.
        (fselect): Rename from fpcmp; use %F.
        (fpcmp): New.

Index: config/ia64/ia64.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/ia64/ia64.c,v
retrieving revision 1.374
diff -u -p -d -r1.374 ia64.c
--- config/ia64/ia64.c	8 Jun 2005 21:29:36 -0000	1.374
+++ config/ia64/ia64.c	9 Jun 2005 17:34:51 -0000
@@ -5168,25 +5168,19 @@ update_set_flags (rtx x, struct reg_flag
       return;
 
     case IF_THEN_ELSE:
-      if (SET_DEST (x) == pc_rtx)
-	/* X is a conditional branch.  */
-	return;
-      else
-	{
-	  /* X is a conditional move.  */
-	  rtx cond = XEXP (src, 0);
-	  cond = XEXP (cond, 0);
-
-	  /* We always split conditional moves into COND_EXEC patterns, so the
-	     only pattern that can reach here is doloop_end_internal.  We don't
-	     need to do anything special for this pattern.  */
-	  gcc_assert (GET_CODE (cond) == REG && REGNO (cond) == AR_LC_REGNUM);
-	  return;
-	}
+      /* There are three cases here:
+	 (1) The destination is (pc), in which case this is a branch,
+	 nothing here applies.
+	 (2) The destination is ar.lc, in which case this is a
+	 doloop_end_internal,
+	 (3) The destination is an fp register, in which case this is
+	 an fselect instruction.
+	 In all cases, nothing we do in this function applies.  */
+      return;
 
     default:
       if (COMPARISON_P (src)
-	  && GET_MODE_CLASS (GET_MODE (XEXP (src, 0))) == MODE_FLOAT)
+	  && SCALAR_FLOAT_MODE_P (GET_MODE (XEXP (src, 0))))
 	/* Set pflags->is_fp to 1 so that we know we're dealing
 	   with a floating point comparison when processing the
 	   destination of the SET.  */
Index: config/ia64/vect.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/ia64/vect.md,v
retrieving revision 1.3
diff -u -p -d -r1.3 vect.md
--- config/ia64/vect.md	27 Apr 2005 08:47:38 -0000	1.3
+++ config/ia64/vect.md	9 Jun 2005 17:34:51 -0000
@@ -1,5 +1,5 @@
 ;; IA-64 machine description for vector operations.
-;; Copyright (C) 2004
+;; Copyright (C) 2004, 2005
 ;;
 ;; This file is part of GCC.
 ;;
@@ -873,30 +873,8 @@
 {
   rtx x, cmp;
 
-  PUT_MODE (operands[3], V2SFmode);
-  switch (GET_CODE (operands[3]))
-    {
-    case EQ:
-    case NE:
-    case LT:
-    case LE:
-    case UNORDERED:
-    case ORDERED:
-      break;
-
-    case GT:
-    case GE:
-      x = XEXP (operands[3], 0);
-      XEXP (operands[3], 0) = XEXP (operands[3], 1);
-      XEXP (operands[3], 1) = x;
-      PUT_CODE (operands[3], swap_condition (GET_CODE (operands[3])));
-      break;
-
-    default:
-      gcc_unreachable ();
-    }
-
   cmp = gen_reg_rtx (V2SFmode);
+  PUT_MODE (operands[3], V2SFmode);
   emit_insn (gen_rtx_SET (VOIDmode, cmp, operands[3]));
 
   x = gen_rtx_IF_THEN_ELSE (V2SFmode, cmp, operands[1], operands[2]);
@@ -906,12 +884,21 @@
 
 (define_insn "*fpcmp"
   [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
+	(match_operator:V2SF 3 "comparison_operator"
+	  [(match_operand:V2SF 1 "fr_reg_or_0_operand" "fU")
+	   (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")]))]
+  ""
+  "fpcmp.%D3 %0 = %F1, %F2"
+  [(set_attr "itanium_class" "fmisc")])
+
+(define_insn "*fselect"
+  [(set (match_operand:V2SF 0 "fr_register_operand" "=f")
 	(if_then_else:V2SF
 	  (match_operand:V2SF 1 "fr_register_operand" "f")
 	  (match_operand:V2SF 2 "fr_reg_or_0_operand" "fU")
 	  (match_operand:V2SF 3 "fr_reg_or_0_operand" "fU")))]
   ""
-  "fselect %0 = %2, %3, %1"
+  "fselect %0 = %F2, %F3, %1"
   [(set_attr "itanium_class" "fmisc")])
 
 (define_expand "vec_initv2sf"


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