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Re: [Patch] MIPS: mips16e machine patterns - zeb/zeh seb/seh


Looks like we've agreed to leave in the -mips16e option then.
here is a revised patch.  I've added a few lines in the manual and now
use GENERATE_MIPS16E instead, since TARGET_MIPS16E is already generated
by mips.opt.
I've removed the check for isa < 32 in mips.exp as now -mips16e is
allowed for any isa (eg -march=mips2 -mips16e), and there's no harm
since its a compile only regression. 

bootstrap on mips-linux.  ok to commit?

David

2005-06-08  David Ung  <davidu@mips.com>

	* doc/invoke.texi (MIPS Options): Add the new -mips16e
	option. Add supported processor names 4km, 24k/kc/kf/kx.
	* config/mips/mips.opt: Add new option mips16e.
	* config/mips/mips.h (GENERATE_MIPS16E): New definition.
	(TARGET_CPU_CPP_BUILTINS): Define __mips16e.
	(ASM_SPEC): Pass through -mips16e.
	* config/mips/mips.c (override_options): Warn if -mips16e and
	-mno-mips16 are used together.  Enable -mips16, when -mips16e is
	used. 
	(mips_file_start): Print ".set mips16e" for -mips16e.
	(build_mips16_function_stub): Similarly.
	(build_mips16_call_stub): Similarly.
	* config/mips/mips.md (zero_extend<SHORT:mode><GPR:mode>2):
	Changed expand condition to exclude generating of "and" if
	GENERATE_MIPS16E is true.
	(*zero_extend<SHORT:mode><GPR:mode>2_mips16e): New pattern for
	matching mips16e zeb/zeh.
	(*extend<SHORT:mode><GPR:mode>2_mips16e): New pattern for matching
	mips16e seb/seh. 
	(*extend<SHORT:mode><GPR:mode>2): Disable this pattern for
	GENERATE_MIPS16E. 

2005-06-08  David Ung  <davidu@mips.com>

	* gcc.target/mips/mips.exp (dg-mips-options): Include check of
	-mips16e in isa.
	* gcc.target/mips/mips16e-extends.c: New test for testing the
	generation of MIPS16e zeb/zeh, seb/seh instructions.

Index: gcc/doc/invoke.texi
===================================================================
RCS file: /cvs/gcc/gcc/gcc/doc/invoke.texi,v
retrieving revision 1.632
diff -c -p -b -r1.632 invoke.texi
*** gcc/doc/invoke.texi	6 Jun 2005 02:32:27 -0000	1.632
--- gcc/doc/invoke.texi	8 Jun 2005 13:49:28 -0000
*************** Objective-C and Objective-C++ Dialects}.
*** 563,569 ****
  @emph{MIPS Options}
  @gccoptlist{-EL  -EB  -march=@var{arch}  -mtune=@var{arch} @gol
  -mips1  -mips2  -mips3  -mips4  -mips32  -mips32r2  -mips64 @gol
! -mips16  -mno-mips16  -mabi=@var{abi}  -mabicalls  -mno-abicalls @gol
  -mxgot  -mno-xgot  -mgp32  -mgp64  -mfp32  -mfp64 @gol
  -mhard-float  -msoft-float  -msingle-float  -mdouble-float @gol
  -mpaired-single  -mips3d @gol
--- 563,569 ----
  @emph{MIPS Options}
  @gccoptlist{-EL  -EB  -march=@var{arch}  -mtune=@var{arch} @gol
  -mips1  -mips2  -mips3  -mips4  -mips32  -mips32r2  -mips64 @gol
! -mips16  -mno-mips16  -mips16e -mabi=@var{abi}  -mabicalls  -mno-abicalls @gol
  -mxgot  -mno-xgot  -mgp32  -mgp64  -mfp32  -mfp64 @gol
  -mhard-float  -msoft-float  -msingle-float  -mdouble-float @gol
  -mpaired-single  -mips3d @gol
*************** The ISA names are:
*** 9756,9762 ****
  @samp{mips1}, @samp{mips2}, @samp{mips3}, @samp{mips4},
  @samp{mips32}, @samp{mips32r2}, and @samp{mips64}.
  The processor names are:
! @samp{4kc}, @samp{4kp}, @samp{5kc}, @samp{20kc},
  @samp{m4k},
  @samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400},
  @samp{r4600}, @samp{r4650}, @samp{r6000}, @samp{r8000}, @samp{rm7000},
--- 9756,9763 ----
  @samp{mips1}, @samp{mips2}, @samp{mips3}, @samp{mips4},
  @samp{mips32}, @samp{mips32r2}, and @samp{mips64}.
  The processor names are:
! @samp{4kc}, @samp{4km}, @samp{4kp}, @samp{5kc}, @samp{20kc},
! @samp{24k}, @samp{24kc}, @samp{24kf}, @samp{24kx},
  @samp{m4k},
  @samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400},
  @samp{r4600}, @samp{r4650}, @samp{r6000}, @samp{r8000}, @samp{rm7000},
*************** Equivalent to @samp{-march=mips64}.
*** 9836,9842 ****
  @itemx -mno-mips16
  @opindex mips16
  @opindex mno-mips16
! Use (do not use) the MIPS16 ISA@.
  
  @item -mabi=32
  @itemx -mabi=o64
--- 9837,9849 ----
  @itemx -mno-mips16
  @opindex mips16
  @opindex mno-mips16
! Use (do not use) the MIPS16 ASE@.
! 
! Note that if ISA is mips32/mips32r2/mips64, MIPS16e is implied.
! 
! @item -mips16e
! @opindex mips16e
! Use the MIPS16e ASE@. 
  
  @item -mabi=32
  @itemx -mabi=o64

Index: gcc/config/mips/mips.opt
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.opt,v
retrieving revision 1.6
diff -c -p -b -r1.6 mips.opt
*** gcc/config/mips/mips.opt	3 Jun 2005 19:07:39 -0000	1.6
--- gcc/config/mips/mips.opt	8 Jun 2005 13:54:11 -0000
*************** mips16
*** 141,146 ****
--- 141,150 ----
  Target Report RejectNegative Mask(MIPS16)
  Generate mips16 code
  
+ mips16e
+ Target Report RejectNegative Mask(MIPS16E)
+ Generate mips16e code
+ 
  mips3d
  Target Report RejectNegative Mask(MIPS3D)
  Use MIPS-3D instructions

Index: gcc/config/mips/mips.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.h,v
retrieving revision 1.396
diff -c -p -b -r1.396 mips.h
*** gcc/config/mips/mips.h	2 Jun 2005 18:08:19 -0000	1.396
--- gcc/config/mips/mips.h	8 Jun 2005 13:54:33 -0000
*************** extern const struct mips_rtx_cost_data *
*** 168,175 ****
     We therefore disable GP-relative switch tables for n64 on IRIX targets.  */
  #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
  
! 					/* Generate mips16 code */
  #define TARGET_MIPS16		((target_flags & MASK_MIPS16) != 0)
  
  /* Generic ISA defines.  */
  #define ISA_MIPS1		    (mips_isa == 1)
--- 168,178 ----
     We therefore disable GP-relative switch tables for n64 on IRIX targets.  */
  #define TARGET_GPWORD (TARGET_ABICALLS && !(mips_abi == ABI_64 && TARGET_IRIX))
  
! /* Generate mips16 code */
  #define TARGET_MIPS16		((target_flags & MASK_MIPS16) != 0)
+ /* Generate mips16e code. Default ASE for mips32/mips32r2/mips64 */
+ #define GENERATE_MIPS16E	(TARGET_MIPS16E	\
+ 				 || (TARGET_MIPS16 && mips_isa >= 32))
  
  /* Generic ISA defines.  */
  #define ISA_MIPS1		    (mips_isa == 1)
*************** extern const struct mips_rtx_cost_data *
*** 311,316 ****
--- 314,322 ----
        if (TARGET_MIPS16)					\
  	builtin_define ("__mips16");				\
  								\
+       if (TARGET_MIPS16E)					\
+ 	builtin_define ("__mips16e");				\
+ 								\
        if (TARGET_MIPS3D)					\
  	builtin_define ("__mips3d");				\
  								\
*************** extern const struct mips_rtx_cost_data *
*** 804,809 ****
--- 810,816 ----
  %{G*} %(endian_spec) %{mips1} %{mips2} %{mips3} %{mips4} \
  %{mips32} %{mips32r2} %{mips64} \
  %{mips16:%{!mno-mips16:-mips16}} %{mno-mips16:-no-mips16} \
+ %{mips16e:-mips16e} \
  %{mips3d:-mips3d} \
  %{mfix-vr4120} %{mfix-vr4130} \
  %(subtarget_asm_optimizing_spec) \

Index: gcc/config/mips/mips.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.c,v
retrieving revision 1.510
diff -c -p -b -r1.510 mips.c
*** gcc/config/mips/mips.c	5 Jun 2005 08:12:04 -0000	1.510
--- gcc/config/mips/mips.c	8 Jun 2005 13:58:36 -0000
*************** override_options (void)
*** 4589,4594 ****
--- 4589,4604 ----
  	warning (0, "-G is incompatible with PIC code which is the default");
      }
  
+   /* Make sure that the user didn't turn off MIPS16 support when MIPS16E
+      support is requested. */
+   if (TARGET_MIPS16E && (target_flags_explicit & MASK_MIPS16)
+       && !TARGET_MIPS16)
+     error ("-mips16e used with -mno-mips16");
+ 
+   /* If TARGET_MIPS16E, enable MASK_MIPS16 */
+   if (TARGET_MIPS16E)
+     target_flags |= MASK_MIPS16;
+ 
    /* mips_split_addresses is a half-way house between explicit
       relocations and the traditional assembler macros.  It can
       split absolute 32-bit symbolic constants into a high/lo_sum
*************** mips_file_start (void)
*** 5612,5618 ****
      /* ??? but do not want this (or want pic0) if -non-shared? */
      fprintf (asm_out_file, "\t.abicalls\n");
  
!   if (TARGET_MIPS16)
      fprintf (asm_out_file, "\t.set\tmips16\n");
  
    if (flag_verbose_asm)
--- 5622,5630 ----
      /* ??? but do not want this (or want pic0) if -non-shared? */
      fprintf (asm_out_file, "\t.abicalls\n");
  
!   if (GENERATE_MIPS16E)
!     fprintf (asm_out_file, "\t.set\tmips16e\n");
!   else if (TARGET_MIPS16)
      fprintf (asm_out_file, "\t.set\tmips16\n");
  
    if (flag_verbose_asm)
*************** build_mips16_function_stub (FILE *file)
*** 7655,7660 ****
--- 7667,7675 ----
        fputs ("\n", file);
      }
  
+   if (GENERATE_MIPS16E)
+     fprintf (file, "\t.set\tmips16e\n");
+   else
      fprintf (file, "\t.set\tmips16\n");
  
    function_section (current_function_decl);
*************** build_mips16_call_stub (rtx retval, rtx 
*** 7928,7933 ****
--- 7943,7951 ----
  	  fputs ("\n", asm_out_file);
  	}
  
+       if (GENERATE_MIPS16E)
+ 	fprintf (asm_out_file, "\t.set\tmips16e\n");
+       else
  	fprintf (asm_out_file, "\t.set\tmips16\n");
  
        /* Record this stub.  */

Index: gcc/config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.322
diff -c -p -b -r1.322 mips.md
*** gcc/config/mips/mips.md	2 Jun 2005 18:08:20 -0000	1.322
--- gcc/config/mips/mips.md	8 Jun 2005 13:59:16 -0000
*************** beq\t%2,%.,1b\;\
*** 2319,2325 ****
          (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
    ""
  {
!   if (TARGET_MIPS16 && !memory_operand (operands[1], <SHORT:MODE>mode))
      {
        emit_insn (gen_and<GPR:mode>3 (operands[0],
  				     gen_lowpart (<GPR:MODE>mode, operands[1]),
--- 2319,2326 ----
          (zero_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
    ""
  {
!   if (TARGET_MIPS16 && !GENERATE_MIPS16E
!       && !memory_operand (operands[1], <SHORT:MODE>mode))
      {
        emit_insn (gen_and<GPR:mode>3 (operands[0],
  				     gen_lowpart (<GPR:MODE>mode, operands[1]),
*************** beq\t%2,%.,1b\;\
*** 2340,2345 ****
--- 2341,2354 ----
    [(set_attr "type" "arith,load")
     (set_attr "mode" "<GPR:MODE>")])
  
+ (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16e"
+   [(set (match_operand:GPR 0 "register_operand" "=d")
+         (zero_extend:GPR (match_operand:SHORT 1 "register_operand" "0")))]
+   "GENERATE_MIPS16E"
+   "ze<SHORT:size>\t%0"
+   [(set_attr "type" "arith")
+    (set_attr "mode" "<GPR:MODE>")])
+ 
  (define_insn "*zero_extend<SHORT:mode><GPR:mode>2_mips16"
    [(set (match_operand:GPR 0 "register_operand" "=d")
          (zero_extend:GPR (match_operand:SHORT 1 "memory_operand" "m")))]
*************** beq\t%2,%.,1b\;\
*** 2418,2428 ****
          (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
    "")
  
  (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
    [(set (match_operand:GPR 0 "register_operand" "=d,d")
          (sign_extend:GPR
  	     (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
!   "!ISA_HAS_SEB_SEH"
    "@
     #
     l<SHORT:size>\t%0,%1"
--- 2427,2447 ----
          (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand")))]
    "")
  
+ (define_insn "*extend<SHORT:mode><GPR:mode>2_mips16e"
+   [(set (match_operand:GPR 0 "register_operand" "=d,d")
+         (sign_extend:GPR (match_operand:SHORT 1 "nonimmediate_operand" "0,m")))]
+   "GENERATE_MIPS16E"
+   "@
+    se<SHORT:size>\t%0
+    l<SHORT:size>\t%0,%1"
+   [(set_attr "type" "arith,load")
+    (set_attr "mode" "<GPR:MODE>")])
+ 
  (define_insn_and_split "*extend<SHORT:mode><GPR:mode>2"
    [(set (match_operand:GPR 0 "register_operand" "=d,d")
          (sign_extend:GPR
  	     (match_operand:SHORT 1 "nonimmediate_operand" "d,m")))]
!   "!ISA_HAS_SEB_SEH && !GENERATE_MIPS16E"
    "@
     #
     l<SHORT:size>\t%0,%1"

Index: gcc/testsuite/gcc.target/mips/mips.exp
===================================================================
RCS file: /cvs/gcc/gcc/gcc/testsuite/gcc.target/mips/mips.exp,v
retrieving revision 1.2
diff -c -p -b -r1.2 mips.exp
*** gcc/testsuite/gcc.target/mips/mips.exp	18 Apr 2005 20:34:36 -0000	1.2
--- gcc/testsuite/gcc.target/mips/mips.exp	8 Jun 2005 13:59:57 -0000
*************** proc dg-mips-options {args} {
*** 152,158 ****
  	    if {$mips_mips16 || ($arch != $mips_arch && $mips_forced_isa)} {
  		set matches 0
  	    }
! 	} elseif {[regexp -- {^-mips(.*)} $flag dummy isa] && $isa != 16} {
  	    if {$mips_mips16 || ($isa != $mips_isa && $mips_forced_isa)} {
  		set matches 0
  	    }
--- 152,159 ----
  	    if {$mips_mips16 || ($arch != $mips_arch && $mips_forced_isa)} {
  		set matches 0
  	    }
! 	} elseif {[regexp -- {^-mips(.*)} $flag dummy isa] 
! 		  && ![string match 16* $isa]} {
  	    if {$mips_mips16 || ($isa != $mips_isa && $mips_forced_isa)} {
  		set matches 0
  	    }

Index: gcc/testsuite/gcc.target/mips/mips16e-extends.c
===================================================================
/* { dg-do compile } */
/* { dg-mips-options "-Os -mips16e" } */

short cksum16 (unsigned long n)
{
  unsigned long l;
  l = validate (n, (n >> 16) + (n & 0xffff));
  return l;
}

char cksum8 (unsigned long n)
{
  unsigned long l;
  l = validate (n, (n >> 8) + (n & 0xff));
  return l;
}

/* { dg-final { scan-assembler "zeh" } } */
/* { dg-final { scan-assembler "seh" } } */
/* { dg-final { scan-assembler "zeb" } } */
/* { dg-final { scan-assembler "seb" } } */


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