This is the mail archive of the
mailing list for the GCC project.
Re: [csl-sol210] Patch to disable ldd and std for 32-bit SPARC
On Sat, 21 May 2005, Eric Botcazou wrote:
> > Thanks, I've applied the following patch to address those comments and to
> > fix a problem found in use of the patch (REG+REG addressing cannot be
> > allowed for DImode quantities with this option because such uses cannot be
> > split).
> I presume you ran into the problem described for TFmode just above?
> /* We prohibit REG + REG for TFmode when there are no quad move insns
> and we consequently need to split. We do this because REG+REG
> is not an offsettable address. If we get the situation in reload
> where source and destination of a movtf pattern are both MEMs with
> REG+REG address, then only one of them gets converted to an
> offsettable address. */
"error: could not split insn" - I think that's the same problem with
REG+REG not being offsettable.
Joseph S. Myers http://www.srcf.ucam.org/~jsm28/gcc/
email@example.com (personal mail)
firstname.lastname@example.org (CodeSourcery mail)
email@example.com (Bugzilla assignments and CCs)