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Re: RFC: MIPS clones without lwl/lwr/swl/swr
- From: Marek Michalkiewicz <marekm at amelek dot gda dot pl>
- To: Richard Sandiford <rsandifo at redhat dot com>
- Cc: gcc-patches at gcc dot gnu dot org
- Date: Sun, 15 May 2005 00:02:28 +0200
- Subject: Re: RFC: MIPS clones without lwl/lwr/swl/swr
- References: <20050513145612.GA17580@amelek.gda.pl> <firstname.lastname@example.org>
On Sat, May 14, 2005 at 08:39:43AM +0100, Richard Sandiford wrote:
> The MIPS port usually guards this sort of instruction selection with an
> ISA_HAS_* macro (ISA_HAS_COND_TRAP, ISA_HAS_CLZ_CLO, etc.). One thing
> I'd like to see is a new ISA_HAS_* macro to say whether lwl/lwr,
> etc. are available. The macro would be false if your new option is
> passed and would also be false for TARGET_MIPS16. If at some point
> in the future, -march is extended to support a processor without the
> patented instructions, the macro would be false when generating code
> for that processor.
After looking at the code a little more, I have a question: the lwl/lwr
etc. patterns in mips.md are conditional on !TARGET_MIPS16, but I don't
see this condition checked in mips_move_block_straight - does this mean
that gen_mov_* may still be called, or is there some logic elsewhere to
prevent this (lwl/lwr etc. on mips16)?
In other words, shouldn't mips_block_move_straight do the following?
bits = MIN (MEM_ALIGN (src), MEM_ALIGN (dest));
else if (MEM_ALIGN (src) == BITS_PER_WORD / 2
&& MEM_ALIGN (dest) == BITS_PER_WORD / 2)
bits = BITS_PER_WORD / 2;
bits = BITS_PER_WORD;
Quick look at binutils/opcodes/mips16-opc.c doesn't show lwl/lwr etc.
Probably I'm missing something here, but what exactly?