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assert frv
- From: Nathan Sidwell <nathan at codesourcery dot com>
- To: Alexandre Oliva <aoliva at redhat dot com>, GCC Patches <gcc-patches at gcc dot gnu dot org>
- Date: Sat, 07 May 2005 16:12:22 +0100
- Subject: assert frv
This patch assertifies the frv target files. Tested with i686 hosted cross
tools. The build of newlib dies both with and without the patch though,
frv-elf-gcc -B/home/nathan/newlib/frv/frv-elf/fr400/newlib/ -isystem /home/nathan/newlib/frv/frv-elf/fr400/newlib/targ-include -isystem /home/nathan/newlib/src/newlib/libc/include -mcpu=fr400 -DPACKAGE=\"newlib\" -DVERSION=\"1.13.0\" -I. -I../../../../../../src/newlib/libc/stdio -O2 -fno-builtin -O2 -g -O2 -mcpu=fr400 -c ../../../../../../src/newlib/libc/stdio/fiprintf.c
../../../../../../src/newlib/libc/stdio/fiprintf.c: In function 'fiprintf':
../../../../../../src/newlib/libc/stdio/fiprintf.c:48: error: unrecognizable insn:
(insn 15 41 16 1 ../../../../../../src/newlib/libc/stdio/fiprintf.c:41 (set (reg:SI 184)
(plus:SI (reg/f:SI 168 ap)
(const_int -16 [0xfffffff0]))) -1 (nil)
(nil))
../../../../../../src/newlib/libc/stdio/fiprintf.c:48: internal compiler error: in instantiate_virtual_regs_in_insn, at function.c:1529
ok?
nathan
--
Nathan Sidwell :: http://www.codesourcery.com :: CodeSourcery LLC
nathan@codesourcery.com :: http://www.planetfall.pwp.blueyonder.co.uk
2005-05-07 Nathan Sidwell <nathan@codesourcery.com>
* config/frv/frv.c (frv_default_flags_for_cpu): Use gcc_assert and
gcc_unreachable, as appropriate.
(frv_function_prologue, frv_alloc_temp_reg,
frv_initial_elimination_offset, frv_expand_block_move,
frv_expand_block_clear, frv_print_operand_jump_hint,
frv_legitimize_tls_address, unspec_got_name, frv_emit_move,
frv_emit_movsi, frv_split_cond_move, frv_split_minmax,
frv_ifcvt_modify_insn, frv_ifcvt_modify_final,
frv_adjust_field_align, frv_insn_unit, frv_cond_flags,
frv_sort_insn_group, frv_reorder_packet, frv_matching_accg_mode,
frv_in_small_data_p, frv_asm_out_constructor,
frv_asm_out_destructor, frv_output_dwarf_dtprel): Likewise.
* config/frv/frv.md (reload_incc_fp, *cond_exec_si_binary1,
*cond_exec_si_binary2, *cond_exec_si_divide, *cond_exec_si_unary1,
*cond_exec_sf_conv, *cond_exec_sf_add, call, sibcall, call_value,
sibcall_value, casesi): Likewise.
Index: config/frv/frv.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/frv/frv.c,v
retrieving revision 1.87
diff -c -3 -p -r1.87 frv.c
*** config/frv/frv.c 4 Apr 2005 21:53:22 -0000 1.87
--- config/frv/frv.c 7 May 2005 15:05:21 -0000
*************** frv_default_flags_for_cpu (void)
*** 571,578 ****
case FRV_CPU_FR300:
case FRV_CPU_SIMPLE:
return MASK_DEFAULT_SIMPLE;
}
- abort ();
}
/* Sometimes certain combinations of command options do not make
--- 571,580 ----
case FRV_CPU_FR300:
case FRV_CPU_SIMPLE:
return MASK_DEFAULT_SIMPLE;
+
+ default:
+ gcc_unreachable ();
}
}
/* Sometimes certain combinations of command options do not make
*************** frv_function_prologue (FILE *file, HOST_
*** 1461,1468 ****
rtx insn;
/* Just to check that the above comment is true. */
! if (regs_ever_live[GPR_FIRST + 3])
! abort ();
/* Generate the instruction that saves the link register. */
fprintf (file, "\tmovsg lr,gr3\n");
--- 1463,1469 ----
rtx insn;
/* Just to check that the above comment is true. */
! gcc_assert (!regs_ever_live[GPR_FIRST + 3]);
/* Generate the instruction that saves the link register. */
fprintf (file, "\tmovsg lr,gr3\n");
*************** frv_alloc_temp_reg (
*** 1519,1528 ****
regno = 0;
if (regno == orig_regno)
{
! if (no_abort)
! return NULL_RTX;
! else
! abort ();
}
}
--- 1520,1527 ----
regno = 0;
if (regno == orig_regno)
{
! gcc_assert (no_abort);
! return NULL_RTX;
}
}
*************** frv_initial_elimination_offset (int from
*** 2109,2115 ****
- info->pretend_size);
else
! abort ();
if (TARGET_DEBUG_STACK)
fprintf (stderr, "Eliminate %s to %s by adding %d\n",
--- 2108,2114 ----
- info->pretend_size);
else
! gcc_unreachable ();
if (TARGET_DEBUG_STACK)
fprintf (stderr, "Eliminate %s to %s by adding %d\n",
*************** frv_expand_block_move (rtx operands[])
*** 2223,2231 ****
if (! constp)
return FALSE;
! /* If this is not a fixed size alignment, abort. */
! if (GET_CODE (align_rtx) != CONST_INT)
! abort ();
align = INTVAL (align_rtx);
--- 2222,2229 ----
if (! constp)
return FALSE;
! /* This should be a fixed size alignment. */
! gcc_assert (GET_CODE (align_rtx) == CONST_INT);
align = INTVAL (align_rtx);
*************** frv_expand_block_clear (rtx operands[])
*** 2316,2324 ****
if (! constp)
return FALSE;
! /* If this is not a fixed size alignment, abort. */
! if (GET_CODE (align_rtx) != CONST_INT)
! abort ();
align = INTVAL (align_rtx);
--- 2314,2321 ----
if (! constp)
return FALSE;
! /* This should be a fixed size alignment. */
! gcc_assert (GET_CODE (align_rtx) == CONST_INT);
align = INTVAL (align_rtx);
*************** frv_print_operand_jump_hint (rtx insn)
*** 2623,2630 ****
HOST_WIDE_INT prob = -1;
enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
! if (GET_CODE (insn) != JUMP_INSN)
! abort ();
/* Assume any non-conditional jump is likely. */
if (! any_condjump_p (insn))
--- 2620,2626 ----
HOST_WIDE_INT prob = -1;
enum { UNKNOWN, BACKWARD, FORWARD } jump_type = UNKNOWN;
! gcc_assert (GET_CODE (insn) == JUMP_INSN);
/* Assume any non-conditional jump is likely. */
if (! any_condjump_p (insn))
*************** frv_legitimize_tls_address (rtx addr, en
*** 3568,3574 ****
break;
}
default:
! abort ();
}
return dest;
--- 3564,3570 ----
break;
}
default:
! gcc_unreachable ();
}
return dest;
*************** unspec_got_name (int i)
*** 3670,3676 ****
case R_FRV_TLSDESCLO: return "tlsdesclo";
case R_FRV_GOTTLSDESCHI: return "gottlsdeschi";
case R_FRV_GOTTLSDESCLO: return "gottlsdesclo";
! default: abort ();
}
}
--- 3666,3672 ----
case R_FRV_TLSDESCLO: return "tlsdesclo";
case R_FRV_GOTTLSDESCHI: return "gottlsdeschi";
case R_FRV_GOTTLSDESCLO: return "gottlsdesclo";
! default: gcc_unreachable ();
}
}
*************** frv_emit_move (enum machine_mode mode, r
*** 3919,3925 ****
break;
default:
! abort ();
}
emit_insn (gen_rtx_SET (VOIDmode, dest, src));
--- 3915,3921 ----
break;
default:
! gcc_unreachable ();
}
emit_insn (gen_rtx_SET (VOIDmode, dest, src));
*************** frv_emit_movsi (rtx dest, rtx src)
*** 4134,4141 ****
/* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
new uses of it once reload has begun. */
! if (reload_in_progress || reload_completed)
! abort ();
switch (unspec)
{
--- 4130,4136 ----
/* Since OUR_FDPIC_REG is a pseudo register, we can't safely introduce
new uses of it once reload has begun. */
! gcc_assert (!reload_in_progress && !reload_completed);
switch (unspec)
{
*************** frv_split_cond_move (rtx operands[])
*** 4933,4939 ****
}
else
! abort ();
}
else
{
--- 4928,4934 ----
}
else
! gcc_unreachable ();
}
else
{
*************** frv_split_minmax (rtx operands[])
*** 5035,5041 ****
switch (GET_CODE (minmax))
{
default:
! abort ();
case SMIN: test_code = LT; break;
case SMAX: test_code = GT; break;
--- 5030,5036 ----
switch (GET_CODE (minmax))
{
default:
! gcc_unreachable ();
case SMIN: test_code = LT; break;
case SMAX: test_code = GT; break;
*************** frv_split_minmax (rtx operands[])
*** 5061,5068 ****
then do a conditional move of the other value. */
if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
{
! if (rtx_equal_p (dest, src1))
! abort ();
emit_move_insn (dest, src2);
emit_insn (gen_rtx_COND_EXEC (VOIDmode,
--- 5056,5062 ----
then do a conditional move of the other value. */
if (GET_CODE (src2) == CONST_INT && INTVAL (src2) != 0)
{
! gcc_assert (!rtx_equal_p (dest, src1));
emit_move_insn (dest, src2);
emit_insn (gen_rtx_COND_EXEC (VOIDmode,
*************** frv_ifcvt_modify_insn (ce_if_block_t *ce
*** 5870,5877 ****
rtx op1;
rtx test;
! if (GET_CODE (pattern) != COND_EXEC)
! abort ();
test = COND_EXEC_TEST (pattern);
if (GET_CODE (test) == AND)
--- 5864,5870 ----
rtx op1;
rtx test;
! gcc_assert (GET_CODE (pattern) == COND_EXEC);
test = COND_EXEC_TEST (pattern);
if (GET_CODE (test) == AND)
*************** frv_ifcvt_modify_final (ce_if_block_t *c
*** 6137,6144 ****
/* Loop inserting the check insns. The last check insn is the first test,
and is the appropriate place to insert constants. */
! if (! p)
! abort ();
do
{
--- 6130,6136 ----
/* Loop inserting the check insns. The last check insn is the first test,
and is the appropriate place to insert constants. */
! gcc_assert (p);
do
{
*************** frv_adjust_field_align (tree field, int
*** 6486,6493 ****
prev = cur;
}
! if (!cur)
! abort ();
/* If this isn't a :0 field and if the previous element is a bitfield
also, see if the type is different, if so, we will need to align the
--- 6478,6484 ----
prev = cur;
}
! gcc_assert (cur);
/* If this isn't a :0 field and if the previous element is a bitfield
also, see if the type is different, if so, we will need to align the
*************** frv_insn_unit (rtx insn)
*** 7007,7014 ****
if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
break;
! if (unit == ARRAY_SIZE (frv_unit_codes))
! abort ();
frv_type_to_unit[type] = unit;
}
--- 6998,7004 ----
if (cpu_unit_reservation_p (state, frv_unit_codes[unit]))
break;
! gcc_assert (unit != ARRAY_SIZE (frv_unit_codes));
frv_type_to_unit[type] = unit;
}
*************** static struct {
*** 7076,7090 ****
static int
frv_cond_flags (rtx cond)
{
! if ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
! && GET_CODE (XEXP (cond, 0)) == REG
! && CR_P (REGNO (XEXP (cond, 0)))
! && XEXP (cond, 1) == const0_rtx)
! return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
! | (GET_CODE (cond) == NE
! ? REGSTATE_IF_TRUE
! : REGSTATE_IF_FALSE));
! abort ();
}
--- 7066,7079 ----
static int
frv_cond_flags (rtx cond)
{
! gcc_assert ((GET_CODE (cond) == EQ || GET_CODE (cond) == NE)
! && GET_CODE (XEXP (cond, 0)) == REG
! && CR_P (REGNO (XEXP (cond, 0)))
! && XEXP (cond, 1) == const0_rtx);
! return ((REGNO (XEXP (cond, 0)) - CR_FIRST)
! | (GET_CODE (cond) == NE
! ? REGSTATE_IF_TRUE
! : REGSTATE_IF_FALSE));
}
*************** frv_sort_insn_group (enum frv_insn_group
*** 7569,7575 ****
return;
}
}
! abort ();
}
/* Sort the current packet into assembly-language order. Set packing
--- 7558,7564 ----
return;
}
}
! gcc_unreachable ();
}
/* Sort the current packet into assembly-language order. Set packing
*************** frv_reorder_packet (void)
*** 7601,7614 ****
if (cursor[group] < packet_group->num_insns)
{
/* frv_reorg should have added nops for us. */
! if (packet_group->sorted[cursor[group]] == packet_group->nop)
! abort ();
insns[to++] = packet_group->sorted[cursor[group]++];
}
}
! if (to != frv_packet.num_insns)
! abort ();
/* Clear the last instruction's packing flag, thus marking the end of
a packet. Reorder the other instructions relative to it. */
--- 7590,7602 ----
if (cursor[group] < packet_group->num_insns)
{
/* frv_reorg should have added nops for us. */
! gcc_assert (packet_group->sorted[cursor[group]]
! != packet_group->nop);
insns[to++] = packet_group->sorted[cursor[group]++];
}
}
! gcc_assert (to == frv_packet.num_insns);
/* Clear the last instruction's packing flag, thus marking the end of
a packet. Reorder the other instructions relative to it. */
*************** frv_matching_accg_mode (enum machine_mod
*** 8258,8264 ****
return QImode;
default:
! abort ();
}
}
--- 8246,8252 ----
return QImode;
default:
! gcc_unreachable ();
}
}
*************** frv_in_small_data_p (tree decl)
*** 8980,8987 ****
section_name = DECL_SECTION_NAME (decl);
if (section_name)
{
! if (TREE_CODE (section_name) != STRING_CST)
! abort ();
if (frv_string_begins_with (section_name, ".sdata"))
return true;
if (frv_string_begins_with (section_name, ".sbss"))
--- 8968,8974 ----
section_name = DECL_SECTION_NAME (decl);
if (section_name)
{
! gcc_assert (TREE_CODE (section_name) == STRING_CST);
if (frv_string_begins_with (section_name, ".sdata"))
return true;
if (frv_string_begins_with (section_name, ".sbss"))
*************** frv_asm_out_constructor (rtx symbol, int
*** 9077,9084 ****
assemble_align (POINTER_SIZE);
if (TARGET_FDPIC)
{
! if (!frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1))
! abort ();
return;
}
assemble_integer_with_op ("\t.picptr\t", symbol);
--- 9064,9072 ----
assemble_align (POINTER_SIZE);
if (TARGET_FDPIC)
{
! int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
!
! gcc_assert (ok);
return;
}
assemble_integer_with_op ("\t.picptr\t", symbol);
*************** frv_asm_out_destructor (rtx symbol, int
*** 9091,9098 ****
assemble_align (POINTER_SIZE);
if (TARGET_FDPIC)
{
! if (!frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1))
! abort ();
return;
}
assemble_integer_with_op ("\t.picptr\t", symbol);
--- 9079,9087 ----
assemble_align (POINTER_SIZE);
if (TARGET_FDPIC)
{
! int ok = frv_assemble_integer (symbol, POINTER_SIZE / BITS_PER_UNIT, 1);
!
! gcc_assert (ok);
return;
}
assemble_integer_with_op ("\t.picptr\t", symbol);
*************** frv_struct_value_rtx (tree fntype ATTRIB
*** 9115,9122 ****
void
frv_output_dwarf_dtprel (FILE *file, int size, rtx x)
{
! if (size != 4)
! abort ();
fputs ("\t.picptr\ttlsmoff(", file);
/* We want the unbiased TLS offset, so add the bias to the
expression, such that the implicit biasing cancels out. */
--- 9104,9110 ----
void
frv_output_dwarf_dtprel (FILE *file, int size, rtx x)
{
! gcc_assert (size == 4);
fputs ("\t.picptr\ttlsmoff(", file);
/* We want the unbiased TLS offset, so add the bias to the
expression, such that the implicit biasing cancels out. */
Index: config/frv/frv.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/frv/frv.md,v
retrieving revision 1.33
diff -c -3 -p -r1.33 frv.md
*** config/frv/frv.md 4 Apr 2005 21:53:22 -0000 1.33
--- config/frv/frv.md 7 May 2005 15:05:38 -0000
***************
*** 2468,2480 ****
rtx addr;
rtx temp3 = simplify_gen_subreg (SImode, operands[2], TImode, 12);
! if (GET_CODE (operands[1]) != MEM)
! abort ();
addr = XEXP (operands[1], 0);
! if (GET_CODE (addr) != PLUS)
! abort ();
emit_move_insn (temp3, XEXP (addr, 1));
--- 2468,2478 ----
rtx addr;
rtx temp3 = simplify_gen_subreg (SImode, operands[2], TImode, 12);
! gcc_assert (GET_CODE (operands[1]) == MEM);
addr = XEXP (operands[1], 0);
! gcc_assert (GET_CODE (addr) == PLUS);
emit_move_insn (temp3, XEXP (addr, 1));
***************
*** 4479,4485 ****
case ASHIFT: return \"csll %4, %z5, %2, %1, %e0\";
case ASHIFTRT: return \"csra %4, %z5, %2, %1, %e0\";
case LSHIFTRT: return \"csrl %4, %z5, %2, %1, %e0\";
! default: abort ();
}
}"
[(set_attr "length" "4")
--- 4477,4483 ----
case ASHIFT: return \"csll %4, %z5, %2, %1, %e0\";
case ASHIFTRT: return \"csra %4, %z5, %2, %1, %e0\";
case LSHIFTRT: return \"csrl %4, %z5, %2, %1, %e0\";
! default: gcc_unreachable ();
}
}"
[(set_attr "length" "4")
***************
*** 4502,4508 ****
case AND: return \"cmand %4, %5, %2, %1, %e0\";
case IOR: return \"cmor %4, %5, %2, %1, %e0\";
case XOR: return \"cmxor %4, %5, %2, %1, %e0\";
! default: abort ();
}
}"
[(set_attr "length" "4")
--- 4500,4506 ----
case AND: return \"cmand %4, %5, %2, %1, %e0\";
case IOR: return \"cmor %4, %5, %2, %1, %e0\";
case XOR: return \"cmxor %4, %5, %2, %1, %e0\";
! default: gcc_unreachable ();
}
}"
[(set_attr "length" "4")
***************
*** 4543,4549 ****
{
case DIV: return \"csdiv %4, %z5, %2, %1, %e0\";
case UDIV: return \"cudiv %4, %z5, %2, %1, %e0\";
! default: abort ();
}
}"
[(set_attr "length" "4")
--- 4541,4547 ----
{
case DIV: return \"csdiv %4, %z5, %2, %1, %e0\";
case UDIV: return \"cudiv %4, %z5, %2, %1, %e0\";
! default: gcc_unreachable ();
}
}"
[(set_attr "length" "4")
***************
*** 4564,4570 ****
{
case NOT: return \"cnot %4, %2, %1, %e0\";
case NEG: return \"csub %., %4, %2, %1, %e0\";
! default: abort ();
}
}"
[(set_attr "length" "4")
--- 4562,4568 ----
{
case NOT: return \"cnot %4, %2, %1, %e0\";
case NEG: return \"csub %., %4, %2, %1, %e0\";
! default: gcc_unreachable ();
}
}"
[(set_attr "length" "4")
***************
*** 4639,4645 ****
{
case ABS: return \"cfabss %4, %2, %1, %e0\";
case NEG: return \"cfnegs %4, %2, %1, %e0\";
! default: abort ();
}
}"
[(set_attr "length" "4")
--- 4637,4643 ----
{
case ABS: return \"cfabss %4, %2, %1, %e0\";
case NEG: return \"cfnegs %4, %2, %1, %e0\";
! default: gcc_unreachable ();
}
}"
[(set_attr "length" "4")
***************
*** 4661,4667 ****
{
case PLUS: return \"cfadds %4, %5, %2, %1, %e0\";
case MINUS: return \"cfsubs %4, %5, %2, %1, %e0\";
! default: abort ();
}
}"
[(set_attr "length" "4")
--- 4659,4665 ----
{
case PLUS: return \"cfadds %4, %5, %2, %1, %e0\";
case MINUS: return \"cfsubs %4, %5, %2, %1, %e0\";
! default: gcc_unreachable ();
}
}"
[(set_attr "length" "4")
***************
*** 5404,5411 ****
rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
rtx addr;
! if (GET_CODE (operands[0]) != MEM)
! abort ();
addr = XEXP (operands[0], 0);
if (! call_operand (addr, Pmode))
--- 5402,5408 ----
rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
rtx addr;
! gcc_assert (GET_CODE (operands[0]) == MEM);
addr = XEXP (operands[0], 0);
if (! call_operand (addr, Pmode))
***************
*** 5490,5497 ****
{
rtx addr;
! if (GET_CODE (operands[0]) != MEM)
! abort ();
addr = XEXP (operands[0], 0);
if (! sibcall_operand (addr, Pmode))
--- 5487,5493 ----
{
rtx addr;
! gcc_assert (GET_CODE (operands[0]) == MEM);
addr = XEXP (operands[0], 0);
if (! sibcall_operand (addr, Pmode))
***************
*** 5558,5565 ****
rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
rtx addr;
! if (GET_CODE (operands[1]) != MEM)
! abort ();
addr = XEXP (operands[1], 0);
if (! call_operand (addr, Pmode))
--- 5554,5560 ----
rtx lr = gen_rtx_REG (Pmode, LR_REGNO);
rtx addr;
! gcc_assert (GET_CODE (operands[1]) == MEM);
addr = XEXP (operands[1], 0);
if (! call_operand (addr, Pmode))
***************
*** 5625,5632 ****
{
rtx addr;
! if (GET_CODE (operands[1]) != MEM)
! abort ();
addr = XEXP (operands[1], 0);
if (! sibcall_operand (addr, Pmode))
--- 5620,5626 ----
{
rtx addr;
! gcc_assert (GET_CODE (operands[1]) == MEM);
addr = XEXP (operands[1], 0);
if (! sibcall_operand (addr, Pmode))
***************
*** 5838,5848 ****
rtx reg2;
rtx reg3;
! if (GET_CODE (operands[1]) != CONST_INT)
! abort ();
! if (GET_CODE (operands[2]) != CONST_INT)
! abort ();
/* If we can't generate an immediate instruction, promote to register. */
if (! IN_RANGE_P (INTVAL (range), -2048, 2047))
--- 5832,5840 ----
rtx reg2;
rtx reg3;
! gcc_assert (GET_CODE (operands[1]) == CONST_INT);
! gcc_assert (GET_CODE (operands[2]) == CONST_INT);
/* If we can't generate an immediate instruction, promote to register. */
if (! IN_RANGE_P (INTVAL (range), -2048, 2047))