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Re: Follow-up patch to SPARC predicates
> This pattern appears several times. Consider making a special
> predicate to match it.
Sure. Does this look about right? I didn't manage to trigger them though,
but I didn't try very hard. I also realized that the 3 mov*_const64_special
special patterns are now superseded by the corresponding mov*_insn.
2005-04-22 Eric Botcazou <ebotcazou@libertysurf.fr>
* config/sparc/predicates.md (const_compl_high_operand): New.
* config/sparc/sparc.md (movhi_const64_special, movsi_const64_special,
movdi_const64_special): Delete.
(logical constant splitters): Use const_compl_high_operand.
--
Eric Botcazou
Index: config/sparc/predicates.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/predicates.md,v
retrieving revision 1.3
diff -u -r1.3 predicates.md
--- config/sparc/predicates.md 22 Apr 2005 13:25:57 -0000 1.3
+++ config/sparc/predicates.md 22 Apr 2005 19:23:55 -0000
@@ -68,6 +68,12 @@
(and (match_test "INTVAL (op) & ~(HOST_WIDE_INT)0x3ff")
(match_test "SPARC_SETHI_P (INTVAL (op) & GET_MODE_MASK (mode))"))))
+;; Return true if OP is a constant whose 1's complement can be loaded by the
+;; sethi instruction.
+(define_predicate "const_compl_high_operand"
+ (and (match_code "const_int")
+ (and (not (match_operand 0 "small_int_operand"))
+ (match_test "SPARC_SETHI_P (~INTVAL (op) & GET_MODE_MASK (mode))"))))
;; Predicates for symbolic constants.
Index: config/sparc/sparc.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sparc.md,v
retrieving revision 1.232
diff -u -r1.232 sparc.md
--- config/sparc/sparc.md 22 Apr 2005 13:25:57 -0000 1.232
+++ config/sparc/sparc.md 22 Apr 2005 19:24:00 -0000
@@ -1841,12 +1841,6 @@
;
})
-(define_insn "*movhi_const64_special"
- [(set (match_operand:HI 0 "register_operand" "=r")
- (match_operand:HI 1 "const_high_operand" "K"))]
- "TARGET_ARCH64"
- "sethi\t%%hi(%a1), %0")
-
(define_insn "*movhi_insn"
[(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,m")
(match_operand:HI 1 "input_operand" "rI,K,m,rJ"))]
@@ -1943,14 +1937,6 @@
;
})
-;; This is needed to show CSE exactly which bits are set
-;; in a 64-bit register by sethi instructions.
-(define_insn "*movsi_const64_special"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (match_operand:SI 1 "const_high_operand" "K"))]
- "TARGET_ARCH64"
- "sethi\t%%hi(%a1), %0")
-
(define_insn "*movsi_insn"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r,f,r,r,r,f,m,m,d")
(match_operand:SI 1 "input_operand" "rI,!f,K,J,m,!m,rJ,!f,J"))]
@@ -2187,14 +2173,6 @@
[(set_attr "type" "store,store,load,*,*,*,*,fpstore,fpload,*,*,*")
(set_attr "length" "2,*,*,2,2,2,2,*,*,2,2,2")])
-;; This is needed to show CSE exactly which bits are set
-;; in a 64-bit register by sethi instructions.
-(define_insn "*movdi_const64_special"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (match_operand:DI 1 "const_high_operand" "N"))]
- "TARGET_ARCH64"
- "sethi\t%%hi(%a1), %0")
-
(define_insn "*movdi_insn_sp64_novis"
[(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,r,m,?e,?e,?W")
(match_operand:DI 1 "input_operand" "rI,N,J,m,rJ,e,W,e"))]
@@ -5845,7 +5823,7 @@
"umacd\t%1, %2, %L0"
[(set_attr "type" "imul")])
-;;- Boolean instructions
+;; Boolean instructions
;; We define DImode `and' so with DImode `not' we can get
;; DImode `andn'. Other combinations are possible.
@@ -5896,9 +5874,9 @@
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(and:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "")))
+ (match_operand:SI 2 "const_compl_high_operand" "")))
(clobber (match_operand:SI 3 "register_operand" ""))]
- "!SMALL_INT (operands[2]) && (INTVAL (operands[2]) & 0x3ff) == 0x3ff"
+ ""
[(set (match_dup 3) (match_dup 4))
(set (match_dup 0) (and:SI (not:SI (match_dup 3)) (match_dup 1)))]
{
@@ -5997,9 +5975,9 @@
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(ior:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "")))
+ (match_operand:SI 2 "const_compl_high_operand" "")))
(clobber (match_operand:SI 3 "register_operand" ""))]
- "!SMALL_INT (operands[2]) && (INTVAL (operands[2]) & 0x3ff) == 0x3ff"
+ ""
[(set (match_dup 3) (match_dup 4))
(set (match_dup 0) (ior:SI (not:SI (match_dup 3)) (match_dup 1)))]
{
@@ -6098,9 +6076,9 @@
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(xor:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" "")))
+ (match_operand:SI 2 "const_compl_high_operand" "")))
(clobber (match_operand:SI 3 "register_operand" ""))]
- "!SMALL_INT (operands[2]) && (INTVAL (operands[2]) & 0x3ff) == 0x3ff"
+ ""
[(set (match_dup 3) (match_dup 4))
(set (match_dup 0) (not:SI (xor:SI (match_dup 3) (match_dup 1))))]
{
@@ -6110,9 +6088,9 @@
(define_split
[(set (match_operand:SI 0 "register_operand" "")
(not:SI (xor:SI (match_operand:SI 1 "register_operand" "")
- (match_operand:SI 2 "const_int_operand" ""))))
+ (match_operand:SI 2 "const_compl_high_operand" ""))))
(clobber (match_operand:SI 3 "register_operand" ""))]
- "!SMALL_INT (operands[2]) && (INTVAL (operands[2]) & 0x3ff) == 0x3ff"
+ ""
[(set (match_dup 3) (match_dup 4))
(set (match_dup 0) (xor:SI (match_dup 3) (match_dup 1)))]
{