This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
[PATCH] Work around PR target/20813 and improve XL compatibility
- From: David Edelsohn <dje at watson dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Fri, 22 Apr 2005 10:39:10 -0400
- Subject: [PATCH] Work around PR target/20813 and improve XL compatibility
All PPC64 processors implement the optional GFX instructions,
except for rs64a, which is rarely used. This patch adds MASK_PPC_GFXOPT
to the default and removes support for rs64a.
This patch also sets the TFmode libfunc optabs to the xlq names if
-mxl-compat is invoked.
Bootstrapped and regression tested on powerpc-ibm-aix5.2.0.0
David
PR target/20813
* config/rs6000/default64.h (TARGET_DEFAULT): Add MASK_PPC_GFXOPT.
* config/rs6000/rs6000.c (processor_target_table): Rename rs64a to
rs64. Add MASK_PPC_GFXOPT to powerpc64 and rs64.
(rs6000_init_libfuncs): Set TFmode optabs to xlq names if
TARGET_XL_COMPAT.
* doc/invoke.texi (PowerPC options): Change rs64a to rs64.
Index: default64.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/default64.h,v
retrieving revision 1.3
diff -c -p -r1.3 default64.h
*** default64.h 27 Sep 2003 04:48:28 -0000 1.3
--- default64.h 22 Apr 2005 14:22:29 -0000
*************** Boston, MA 02111-1307, USA. */
*** 21,24 ****
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
! (MASK_POWERPC | MASK_POWERPC64 | MASK_64BIT | MASK_NEW_MNEMONICS)
--- 21,25 ----
#undef TARGET_DEFAULT
#define TARGET_DEFAULT \
! (MASK_POWERPC | MASK_PPC_GFXOPT | \
! MASK_POWERPC64 | MASK_64BIT | MASK_NEW_MNEMONICS)
Index: rs6000.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.812
diff -c -p -r1.812 rs6000.c
*** rs6000.c 21 Apr 2005 21:13:36 -0000 1.812
--- rs6000.c 22 Apr 2005 14:22:32 -0000
*************** rs6000_override_options (const char *def
*** 1161,1174 ****
POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
{"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
{"powerpc64", PROCESSOR_POWERPC64,
! POWERPC_BASE_MASK | MASK_POWERPC64},
{"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
{"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
{"rios2", PROCESSOR_RIOS2,
MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
{"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
{"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
! {"rs64a", PROCESSOR_RS64A, POWERPC_BASE_MASK | MASK_POWERPC64},
};
const size_t ptt_size = ARRAY_SIZE (processor_target_table);
--- 1161,1175 ----
POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_MFCRF | MASK_POWERPC64},
{"powerpc", PROCESSOR_POWERPC, POWERPC_BASE_MASK},
{"powerpc64", PROCESSOR_POWERPC64,
! POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64},
{"rios", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
{"rios1", PROCESSOR_RIOS1, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
{"rios2", PROCESSOR_RIOS2,
MASK_POWER | MASK_POWER2 | MASK_MULTIPLE | MASK_STRING},
{"rsc", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
{"rsc1", PROCESSOR_PPC601, MASK_POWER | MASK_MULTIPLE | MASK_STRING},
! {"rs64", PROCESSOR_RS64A,
! POWERPC_BASE_MASK | MASK_PPC_GFXOPT | MASK_POWERPC64}
};
const size_t ptt_size = ARRAY_SIZE (processor_target_table);
*************** rs6000_init_libfuncs (void)
*** 8139,8149 ****
set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
}
! /* Standard AIX/Darwin/64-bit SVR4 quad floating point routines. */
! set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
! set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
! set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
! set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
}
else
{
--- 8140,8160 ----
set_conv_libfunc (ufix_optab, SImode, TFmode, "_quitrunc");
}
! /* AIX/Darwin/64-bit Linux quad floating point routines. */
! if (!TARGET_XL_COMPAT)
! {
! set_optab_libfunc (add_optab, TFmode, "__gcc_qadd");
! set_optab_libfunc (sub_optab, TFmode, "__gcc_qsub");
! set_optab_libfunc (smul_optab, TFmode, "__gcc_qmul");
! set_optab_libfunc (sdiv_optab, TFmode, "__gcc_qdiv");
! }
! else
! {
! set_optab_libfunc (add_optab, TFmode, "_xlqadd");
! set_optab_libfunc (sub_optab, TFmode, "_xlqsub");
! set_optab_libfunc (smul_optab, TFmode, "_xlqmul");
! set_optab_libfunc (sdiv_optab, TFmode, "_xlqdiv");
! }
}
else
{
Index: invoke.texi
===================================================================
RCS file: /cvs/gcc/gcc/gcc/doc/invoke.texi,v
retrieving revision 1.606
diff -c -p -r1.606 invoke.texi
*** invoke.texi 21 Apr 2005 08:48:55 -0000 1.606
--- invoke.texi 22 Apr 2005 14:27:54 -0000
*************** Supported values for @var{cpu_type} are
*** 10565,10571 ****
@samp{860}, @samp{970}, @samp{8540}, @samp{common}, @samp{ec603e}, @samp{G3},
@samp{G4}, @samp{G5}, @samp{power}, @samp{power2}, @samp{power3},
@samp{power4}, @samp{power5}, @samp{powerpc}, @samp{powerpc64},
! @samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64a}.
@option{-mcpu=common} selects a completely generic processor. Code
generated under this option will run on any POWER or PowerPC processor.
--- 10565,10571 ----
@samp{860}, @samp{970}, @samp{8540}, @samp{common}, @samp{ec603e}, @samp{G3},
@samp{G4}, @samp{G5}, @samp{power}, @samp{power2}, @samp{power3},
@samp{power4}, @samp{power5}, @samp{powerpc}, @samp{powerpc64},
! @samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64}.
@option{-mcpu=common} selects a completely generic processor. Code
generated under this option will run on any POWER or PowerPC processor.