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Patch for PR target/20924
- From: Steve Ellcey <sje at cup dot hp dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Tue, 12 Apr 2005 10:35:21 -0700 (PDT)
- Subject: Patch for PR target/20924
- Reply-to: sje at cup dot hp dot com
This patch fixes PR target/20924 where the inline division sequences
were not correctly setting the floating point flags. This was because
the frcpa (floating point reciprical approximation) instruction was
being done with floating point status register 1 instead of 0.
This patch makes the inline sequence use fprca with fpsr 0 and makes it
match the code in the assembly routines in lib1funcs.asm.
I tested it on IA64 HP-UX and Linux with no regressions and tested
the test case in PR 20924 to verify that my fix fixed the problem
there.
OK for checkin on ToT?
Steve Ellcey
sje@cup.hp.com
2005-04-12 Steve Ellcey <sje@cup.hp.com>
PR target/20924
* config/ia64/ia64.md (divsf3_internal_lat): Generate frcpa with
fpsr 0 instead of fpsr 1.
(divsf3_internal_thr): Ditto.
(divdf3_internal_lat): Ditto.
(divdf3_internal_thr): Ditto.
(divxf3_internal_lat): Ditto.
(divxf3_internal_thr): Ditto.
*** gcc.orig/gcc/config/ia64/ia64.md Tue Apr 12 10:12:37 2005
--- gcc/gcc/config/ia64/ia64.md Tue Apr 12 10:12:22 2005
***************
*** 2699,2705 ****
[(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
(set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
UNSPEC_FR_RECIP_APPROX))
! (use (const_int 1))])
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3) (mult:XF (match_dup 7) (match_dup 6)))
(use (const_int 1))]))
--- 2699,2705 ----
[(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
(set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
UNSPEC_FR_RECIP_APPROX))
! (use (const_int 0))])
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3) (mult:XF (match_dup 7) (match_dup 6)))
(use (const_int 1))]))
***************
*** 2756,2762 ****
[(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
(set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
UNSPEC_FR_RECIP_APPROX))
! (use (const_int 1))])
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
(minus:XF (match_dup 10)
--- 2756,2762 ----
[(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
(set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
UNSPEC_FR_RECIP_APPROX))
! (use (const_int 0))])
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
(minus:XF (match_dup 10)
***************
*** 3182,3188 ****
[(parallel [(set (match_dup 7) (div:XF (const_int 1) (match_dup 9)))
(set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)]
UNSPEC_FR_RECIP_APPROX))
! (use (const_int 1))])
(cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 3) (mult:XF (match_dup 8) (match_dup 7)))
(use (const_int 1))]))
--- 3182,3188 ----
[(parallel [(set (match_dup 7) (div:XF (const_int 1) (match_dup 9)))
(set (match_dup 6) (unspec:BI [(match_dup 8) (match_dup 9)]
UNSPEC_FR_RECIP_APPROX))
! (use (const_int 0))])
(cond_exec (ne (match_dup 6) (const_int 0))
(parallel [(set (match_dup 3) (mult:XF (match_dup 8) (match_dup 7)))
(use (const_int 1))]))
***************
*** 3262,3268 ****
[(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
(set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
UNSPEC_FR_RECIP_APPROX))
! (use (const_int 1))])
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
(minus:XF (match_dup 10)
--- 3262,3268 ----
[(parallel [(set (match_dup 6) (div:XF (const_int 1) (match_dup 8)))
(set (match_dup 5) (unspec:BI [(match_dup 7) (match_dup 8)]
UNSPEC_FR_RECIP_APPROX))
! (use (const_int 0))])
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
(minus:XF (match_dup 10)
***************
*** 3847,3853 ****
[(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
(set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)]
UNSPEC_FR_RECIP_APPROX))
! (use (const_int 1))])
(cond_exec (ne (match_dup 7) (const_int 0))
(parallel [(set (match_dup 3)
(minus:XF (match_dup 8)
--- 3847,3853 ----
[(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
(set (match_dup 7) (unspec:BI [(match_dup 1) (match_dup 2)]
UNSPEC_FR_RECIP_APPROX))
! (use (const_int 0))])
(cond_exec (ne (match_dup 7) (const_int 0))
(parallel [(set (match_dup 3)
(minus:XF (match_dup 8)
***************
*** 3925,3931 ****
[(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
(set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)]
UNSPEC_FR_RECIP_APPROX))
! (use (const_int 1))])
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
(minus:XF (match_dup 6)
--- 3925,3931 ----
[(parallel [(set (match_dup 0) (div:XF (const_int 1) (match_dup 2)))
(set (match_dup 5) (unspec:BI [(match_dup 1) (match_dup 2)]
UNSPEC_FR_RECIP_APPROX))
! (use (const_int 0))])
(cond_exec (ne (match_dup 5) (const_int 0))
(parallel [(set (match_dup 3)
(minus:XF (match_dup 6)