This is the mail archive of the gcc-patches@gcc.gnu.org mailing list for the GCC project.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]
Other format: [Raw text]

[committed] [Patch] RS6000: Rename vector shift patterns


Renaming vector shift insn patterns, allow vectorization of shift
operations. Bootstrapped and tested on powerpc-darwin.

         * config/rs600/altivec.md (altivec_vsr<VI_char>): Rename to ..
         (lhsr<mode>3): ... new name.
         (altivec_vsra<VI_char>): Rename to ..
         (ashr<mode>3): ... new name.
         * config/rs6000/rs6000.c (builtin_description): Rename shift
         operations.

testsuite:
* lib/target-supports.exp (check_effective_target_vect_shif): New.
* gcc.dg/vect/vect-shift-1.c: New test.


Geoff already approved this for 4.1 on Jan 28th.
I tested it again on powerpc-darwin. Applied to mainline.

-
Devang

[ Ref: http://gcc.gnu.org/ml/gcc-patches/2005-01/msg02154.html ]

Index: config/rs6000/altivec.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/altivec.md,v
retrieving revision 1.31
diff -Idpatel.pbxuser -c -3 -p -r1.31 altivec.md
*** config/rs6000/altivec.md    7 Feb 2005 15:53:36 -0000       1.31
--- config/rs6000/altivec.md    5 Apr 2005 16:02:49 -0000
***************
*** 968,985 ****
    "vslo %0,%1,%2"
    [(set_attr "type" "vecperm")])

! (define_insn "altivec_vsr<VI_char>"
[(set (match_operand:VI 0 "register_operand" "=v")
! (unspec:VI [(match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v")] 112))]
"TARGET_ALTIVEC"
"vsr<VI_char> %0,%1,%2"
[(set_attr "type" "vecsimple")])

! (define_insn "altivec_vsra<VI_char>"
[(set (match_operand:VI 0 "register_operand" "=v")
! (unspec:VI [(match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v")] 115))]
"TARGET_ALTIVEC"
"vsra<VI_char> %0,%1,%2"
[(set_attr "type" "vecsimple")])
--- 968,985 ----
"vslo %0,%1,%2"
[(set_attr "type" "vecperm")])

! (define_insn "lshr<mode>3"
    [(set (match_operand:VI 0 "register_operand" "=v")
!         (lshiftrt:VI (match_operand:VI 1 "register_operand" "v")
!                     (match_operand:VI 2 "register_operand" "v") ))]
    "TARGET_ALTIVEC"
    "vsr<VI_char> %0,%1,%2"
    [(set_attr "type" "vecsimple")])

! (define_insn "ashr<mode>3"
[(set (match_operand:VI 0 "register_operand" "=v")
! (ashiftrt:VI (match_operand:VI 1 "register_operand" "v")
! (match_operand:VI 2 "register_operand" "v") ))]
"TARGET_ALTIVEC"
"vsra<VI_char> %0,%1,%2"
[(set_attr "type" "vecsimple")])
Index: config/rs6000/rs6000.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.803
diff -Idpatel.pbxuser -c -3 -p -r1.803 rs6000.c
*** config/rs6000/rs6000.c 2 Apr 2005 10:46:03 -0000 1.803
--- config/rs6000/rs6000.c 5 Apr 2005 16:02:57 -0000
*************** static struct builtin_description bdesc_
*** 5590,5601 ****
{ MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
{ MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsrb, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsrh, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsrw, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsrab, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsrah, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
! { MASK_ALTIVEC, CODE_FOR_altivec_vsraw, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
{ MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
--- 5590,5601 ----
{ MASK_ALTIVEC, CODE_FOR_altivec_vspltb, "__builtin_altivec_vspltb", ALTIVEC_BUILTIN_VSPLTB },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsplth, "__builtin_altivec_vsplth", ALTIVEC_BUILTIN_VSPLTH },
{ MASK_ALTIVEC, CODE_FOR_altivec_vspltw, "__builtin_altivec_vspltw", ALTIVEC_BUILTIN_VSPLTW },
! { MASK_ALTIVEC, CODE_FOR_lshrv16qi3, "__builtin_altivec_vsrb", ALTIVEC_BUILTIN_VSRB },
! { MASK_ALTIVEC, CODE_FOR_lshrv8hi3, "__builtin_altivec_vsrh", ALTIVEC_BUILTIN_VSRH },
! { MASK_ALTIVEC, CODE_FOR_lshrv4si3, "__builtin_altivec_vsrw", ALTIVEC_BUILTIN_VSRW },
! { MASK_ALTIVEC, CODE_FOR_ashrv16qi3, "__builtin_altivec_vsrab", ALTIVEC_BUILTIN_VSRAB },
! { MASK_ALTIVEC, CODE_FOR_ashrv8hi3, "__builtin_altivec_vsrah", ALTIVEC_BUILTIN_VSRAH },
! { MASK_ALTIVEC, CODE_FOR_ashrv4si3, "__builtin_altivec_vsraw", ALTIVEC_BUILTIN_VSRAW },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsr, "__builtin_altivec_vsr", ALTIVEC_BUILTIN_VSR },
{ MASK_ALTIVEC, CODE_FOR_altivec_vsro, "__builtin_altivec_vsro", ALTIVEC_BUILTIN_VSRO },
{ MASK_ALTIVEC, CODE_FOR_subv16qi3, "__builtin_altivec_vsububm", ALTIVEC_BUILTIN_VSUBUBM },
Index: testsuite/gcc.dg/vect/vect-shift-1.c
===================================================================
RCS file: testsuite/gcc.dg/vect/vect-shift-1.c
diff -N testsuite/gcc.dg/vect/vect-shift-1.c
*** /dev/null 1 Jan 1970 00:00:00 -0000
--- testsuite/gcc.dg/vect/vect-shift-1.c 5 Apr 2005 16:03:07 -0000
***************
*** 0 ****
--- 1,28 ----
+ /* { dg-require-effective-target vect_shift } */
+
+ #include <stdarg.h>
+ #include <signal.h>
+
+ #define N 16
+ #define MAX 42
+
+ extern void abort(void);
+
+ int main ()
+ {
+ unsigned int A[4] = {0x08000000,0x08000001,0xff0000ff,0xf0000001};
+ unsigned int Answer[4] = {0x01000000,0x01000000,0x01fe0001f, 0x1e000000};
+ unsigned int B[4];
+ int i, j;
+
+ for (i=0; i<4; i++)
+ B[i] = A[i] >> 3;
+ for (i=0; i<4; i++)
+ if (B[i] != Answer[i])
+ abort ();
+ return 0;
+ }
+
+
+
+ /* { dg-final { scan-tree-dump-times "vectorized 1 loops" 1 "vect" { xfail i?86-*-* x86_64-*-* } } } */
Index: testsuite/lib/target-supports.exp
===================================================================
RCS file: /cvs/gcc/gcc/gcc/testsuite/lib/target-supports.exp,v
retrieving revision 1.46
diff -Idpatel.pbxuser -c -3 -p -r1.46 target-supports.exp
*** testsuite/lib/target-supports.exp 25 Mar 2005 02:21:01 -0000 1.46
--- testsuite/lib/target-supports.exp 5 Apr 2005 16:03:08 -0000
*************** proc check_effective_target_vect_int { }
*** 640,645 ****
--- 640,658 ----
return $et_vect_int_saved
}

+ # Return 1 if the target supports hardware vector shift operation.
+
+ proc check_effective_target_vect_shift { } {
+ if { [istarget powerpc*-*-*] } {
+ set answer 1
+ } else {
+ set answer 0
+ }
+
+ verbose "check_effective_target_vect_shift: returning $answer" 2
+ return $answer
+ }
+
# Return 1 if the target supports hardware vectors of long, 0 otherwise.
#
# This can change for different subtargets so do not cache the result.

Index Nav: [Date Index] [Subject Index] [Author Index] [Thread Index]
Message Nav: [Date Prev] [Date Next] [Thread Prev] [Thread Next]