[patch] Dwarf output for overlapping registers

[Paul Brook <paul at codesourcery dot com>]

If a register value overlaps several registers gcc currently outputs 
DW_OP_piece describing this mapping. In most cases this is correct.

However for Arm VFP registers we want to output a single DW_OP_reg, and it's 
up to the debugger to figure out if we're referring to a single or double 
precision register. 

The attached patch extends the TARGET_DWARF_REGISTER_SPAN hook to allow this.
Tested with cross to arm-none-eabi.
Applied to csl-arm-branch.

Ok for mainline?

Paul

2005-03-30  Paul Brook  <pau@codesourcery.com>

 * dwarf2out.c (multiple_reg_loc_descriptor): Handle single REG.
 * config/arm/arm.c (arm_dwarf_register_span): New function.
 (TARGET_DWARF_REGISTER_SPAN): Define.
 * doc/tm.dexi: Update documentation for TARGET_DWARF_REGISTER_SPAN.

Index: dwarf2out.c
===================================================================
RCS file: /var/cvsroot/gcc-cvs/gcc/gcc/dwarf2out.c,v
retrieving revision 1.574
diff -u -p -r1.574 dwarf2out.c
--- dwarf2out.c	22 Mar 2005 23:18:42 -0000	1.574
+++ dwarf2out.c	30 Mar 2005 16:35:51 -0000
@@ -8372,6 +8372,16 @@ multiple_reg_loc_descriptor (rtx rtl, rt
       return loc_result;
     }
 
+  /* A single register.  This happens when a single dwarf register overlaps
+     multiple gcc registers.  */
+
+  if (GET_CODE (regs) == REG)
+    {
+      reg = dbx_reg_number (regs);
+
+      return one_reg_loc_descriptor (reg);
+    }
+
   /* Now onto stupid register sets in non contiguous locations.  */
 
   gcc_assert (GET_CODE (regs) == PARALLEL);
Index: config/arm/arm.c
===================================================================
RCS file: /var/cvsroot/gcc-cvs/gcc/gcc/config/arm/arm.c,v
retrieving revision 1.432
diff -u -p -r1.432 arm.c
--- config/arm/arm.c	29 Mar 2005 03:00:23 -0000	1.432
+++ config/arm/arm.c	30 Mar 2005 16:37:12 -0000
@@ -176,6 +176,7 @@ static bool arm_cxx_key_method_may_be_in
 static bool arm_cxx_export_class_data (void);
 static void arm_init_libfuncs (void);
 static unsigned HOST_WIDE_INT arm_shift_truncation_mask (enum machine_mode);
+static rtx arm_dwarf_register_span (rtx);
 
 /* Initialize the GCC target structure.  */
 #if TARGET_DLLIMPORT_DECL_ATTRIBUTES
@@ -311,6 +312,9 @@ static unsigned HOST_WIDE_INT arm_shift_
 #undef TARGET_CXX_EXPORT_CLASS_DATA
 #define TARGET_CXX_EXPORT_CLASS_DATA arm_cxx_export_class_data
 
+#undef TARGET_DWARF_REGISTER_SPAN
+#define TARGET_DWARF_REGISTER_SPAN arm_dwarf_register_span
+
 struct gcc_target targetm = TARGET_INITIALIZER;
 
 /* Obstack for minipool constant handling.  */
@@ -14522,6 +14526,7 @@ arm_cxx_key_method_may_be_inline (void)
    behavior if there is no key method, but there is no harm in
    exporting the class data in that case too.  */
 
+
 static bool
 arm_cxx_export_class_data (void)
 {
@@ -14668,3 +14673,21 @@ arm_dbx_register_number (unsigned int re
   abort ();
 }
 
+
+/* Double precision VFP registers are referenced by a single DWARF register,
+   even though they cover two gcc registers.  Return the REG rtx so that gcc
+   doesn't ouptu DW_OP_piece for these.  */
+
+static rtx
+arm_dwarf_register_span (rtx reg)
+{
+  unsigned regno;
+
+  regno = REGNO (reg);
+  /* We could return NULL for single precision values, but it's safe
+     (and easier) to return the REG all the time.  */
+  if (IS_VFP_REGNUM (regno))
+    return reg;
+
+  return NULL;
+}
Index: doc/tm.texi
===================================================================
RCS file: /var/cvsroot/gcc-cvs/gcc/gcc/doc/tm.texi,v
retrieving revision 1.420
diff -u -p -r1.420 tm.texi
--- doc/tm.texi	23 Mar 2005 03:55:32 -0000	1.420
+++ doc/tm.texi	30 Mar 2005 16:35:51 -0000
@@ -7791,7 +7791,10 @@ Given a register, this hook should retur
 represent where to find the register pieces.  Define this hook if the
 register and its mode are represented in Dwarf in non-contiguous
 locations, or if the register should be represented in more than one
-register in Dwarf.  Otherwise, this hook should return @code{NULL_RTX}.
+register in Dwarf.  This hook can also return @code{reg} to force the
+register to be referenced as a single register, even if gcc thinks it is
+split over multiple consecutive registers.  Otherwise, this hook should
+return @code{NULL_RTX}.
 If not defined, the default is to return @code{NULL_RTX}.
 @end deftypefn