Re: [PATCH] [4.0] Fix performance regressions due to inlining

[Richard Sandiford <rsandifo at redhat dot com>]

Richard Earnshaw <rearnsha@gcc.gnu.org> writes:
> On Tue, 2005-03-08 at 08:40, Richard Sandiford wrote:
>> Paul Schlie <schlie@comcast.net> writes:
>> > - although I may misunderstand, on a typical 3-operand machine:
>> >
>> >     add r<a> r<b> c<> ; therefore a cost estimate of 1 seems good.
>> >
>> >   but on a 2-operand machine, typical of lower-end arm, mips, etc.:
>> >
>> >     mov r<a> c<c>  ; being typical, a cost of 2 seems reasonable
>> >     add r<a> r<b>  ; as it stands today.
>> 
>> Huh?  MIPS and ARM are basically three-operand ISAs.  The new heuristics
>> definitely make sense to me from a MIPS POV.
>
> Thumb is a two-operand ISA.

Oh sorry, was that he meant by "lower-end"?  And MIPS16 being
"lower-end MIPS" presumably.

It's just that "lower-end MIPS" to me means "cheaper than usual MIPS",
whereas supporting two ISAs instead of one has nothing to with being
cheaper...

Richard