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Re: [PATCH] [4.0] Fix performance regressions due to inlining


Paul Schlie <schlie@comcast.net> writes:
> - although I may misunderstand, on a typical 3-operand machine:
>
>     add r<a> r<b> c<> ; therefore a cost estimate of 1 seems good.
>
>   but on a 2-operand machine, typical of lower-end arm, mips, etc.:
>
>     mov r<a> c<c>  ; being typical, a cost of 2 seems reasonable
>     add r<a> r<b>  ; as it stands today.

Huh?  MIPS and ARM are basically three-operand ISAs.  The new heuristics
definitely make sense to me from a MIPS POV.

Richard


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