2005-02-17 James E. Wilson * doc/invoke.texi (IA-64 Options): Delete -mb-step. * config/ia64/ia64.c (last_group, group_idx): Delete variables. (errata_find_address_regs, errata_emit_nops, fixup_errata): Delete functions. (ia64_reorg): Delete fixup_errata call. * config/ia64/ia64.h (MASK_B_STEP, TARGET_B_STEP): Delete. (TARGET_SWITCHES): Delete -mb-step entry. Index: doc/invoke.texi =================================================================== RCS file: /cvs/gcc/gcc/gcc/doc/invoke.texi,v retrieving revision 1.579 diff -p -r1.579 invoke.texi *** doc/invoke.texi 14 Feb 2005 20:46:29 -0000 1.579 --- doc/invoke.texi 17 Feb 2005 22:48:15 -0000 *************** Objective-C and Objective-C++ Dialects}. *** 499,505 **** @emph{IA-64 Options} @gccoptlist{-mbig-endian -mlittle-endian -mgnu-as -mgnu-ld -mno-pic @gol ! -mvolatile-asm-stop -mb-step -mregister-names -mno-sdata @gol -mconstant-gp -mauto-pic -minline-float-divide-min-latency @gol -minline-float-divide-max-throughput @gol -minline-int-divide-min-latency @gol --- 499,505 ---- @emph{IA-64 Options} @gccoptlist{-mbig-endian -mlittle-endian -mgnu-as -mgnu-ld -mno-pic @gol ! -mvolatile-asm-stop -mregister-names -mno-sdata @gol -mconstant-gp -mauto-pic -minline-float-divide-min-latency @gol -minline-float-divide-max-throughput @gol -minline-int-divide-min-latency @gol *************** is not position independent code, and vi *** 8866,8875 **** Generate (or don't) a stop bit immediately before and after volatile asm statements. - @item -mb-step - @opindex mb-step - Generate code that works around Itanium B step errata. - @item -mregister-names @itemx -mno-register-names @opindex mregister-names --- 8866,8871 ---- Index: config/ia64/ia64.c =================================================================== RCS file: /cvs/gcc/gcc/gcc/config/ia64/ia64.c,v retrieving revision 1.345 diff -p -r1.345 ia64.c *** config/ia64/ia64.c 28 Jan 2005 00:55:04 -0000 1.345 --- config/ia64/ia64.c 17 Feb 2005 22:48:18 -0000 *************** emit_all_insn_group_barriers (FILE *dump *** 5684,5830 **** } - static int errata_find_address_regs (rtx *, void *); - static void errata_emit_nops (rtx); - static void fixup_errata (void); - - /* This structure is used to track some details about the previous insns - groups so we can determine if it may be necessary to insert NOPs to - workaround hardware errata. */ - static struct group - { - HARD_REG_SET p_reg_set; - HARD_REG_SET gr_reg_conditionally_set; - } last_group[2]; - - /* Index into the last_group array. */ - static int group_idx; - - /* Called through for_each_rtx; determines if a hard register that was - conditionally set in the previous group is used as an address register. - It ensures that for_each_rtx returns 1 in that case. */ - static int - errata_find_address_regs (rtx *xp, void *data ATTRIBUTE_UNUSED) - { - rtx x = *xp; - if (GET_CODE (x) != MEM) - return 0; - x = XEXP (x, 0); - if (GET_CODE (x) == POST_MODIFY) - x = XEXP (x, 0); - if (GET_CODE (x) == REG) - { - struct group *prev_group = last_group + (group_idx ^ 1); - if (TEST_HARD_REG_BIT (prev_group->gr_reg_conditionally_set, - REGNO (x))) - return 1; - return -1; - } - return 0; - } - - /* Called for each insn; this function keeps track of the state in - last_group and emits additional NOPs if necessary to work around - an Itanium A/B step erratum. */ - static void - errata_emit_nops (rtx insn) - { - struct group *this_group = last_group + group_idx; - struct group *prev_group = last_group + (group_idx ^ 1); - rtx pat = PATTERN (insn); - rtx cond = GET_CODE (pat) == COND_EXEC ? COND_EXEC_TEST (pat) : 0; - rtx real_pat = cond ? COND_EXEC_CODE (pat) : pat; - enum attr_type type; - rtx set = real_pat; - - if (GET_CODE (real_pat) == USE - || GET_CODE (real_pat) == CLOBBER - || GET_CODE (real_pat) == ASM_INPUT - || GET_CODE (real_pat) == ADDR_VEC - || GET_CODE (real_pat) == ADDR_DIFF_VEC - || asm_noperands (PATTERN (insn)) >= 0) - return; - - /* single_set doesn't work for COND_EXEC insns, so we have to duplicate - parts of it. */ - - if (GET_CODE (set) == PARALLEL) - { - int i; - set = XVECEXP (real_pat, 0, 0); - for (i = 1; i < XVECLEN (real_pat, 0); i++) - if (GET_CODE (XVECEXP (real_pat, 0, i)) != USE - && GET_CODE (XVECEXP (real_pat, 0, i)) != CLOBBER) - { - set = 0; - break; - } - } - - if (set && GET_CODE (set) != SET) - set = 0; - - type = get_attr_type (insn); - - if (type == TYPE_F - && set && REG_P (SET_DEST (set)) && PR_REGNO_P (REGNO (SET_DEST (set)))) - SET_HARD_REG_BIT (this_group->p_reg_set, REGNO (SET_DEST (set))); - - if ((type == TYPE_M || type == TYPE_A) && cond && set - && REG_P (SET_DEST (set)) - && GET_CODE (SET_SRC (set)) != PLUS - && GET_CODE (SET_SRC (set)) != MINUS - && (GET_CODE (SET_SRC (set)) != ASHIFT - || !shladd_operand (XEXP (SET_SRC (set), 1), VOIDmode)) - && (GET_CODE (SET_SRC (set)) != MEM - || GET_CODE (XEXP (SET_SRC (set), 0)) != POST_MODIFY) - && GENERAL_REGNO_P (REGNO (SET_DEST (set)))) - { - if (!COMPARISON_P (cond) - || !REG_P (XEXP (cond, 0))) - abort (); - - if (TEST_HARD_REG_BIT (prev_group->p_reg_set, REGNO (XEXP (cond, 0)))) - SET_HARD_REG_BIT (this_group->gr_reg_conditionally_set, REGNO (SET_DEST (set))); - } - if (for_each_rtx (&real_pat, errata_find_address_regs, NULL)) - { - emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn); - emit_insn_before (gen_nop (), insn); - emit_insn_before (gen_insn_group_barrier (GEN_INT (3)), insn); - group_idx = 0; - memset (last_group, 0, sizeof last_group); - } - } - - /* Emit extra nops if they are required to work around hardware errata. */ - - static void - fixup_errata (void) - { - rtx insn; - - if (! TARGET_B_STEP) - return; - - group_idx = 0; - memset (last_group, 0, sizeof last_group); - - for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) - { - if (!INSN_P (insn)) - continue; - - if (ia64_safe_type (insn) == TYPE_S) - { - group_idx ^= 1; - memset (last_group + group_idx, 0, sizeof last_group[group_idx]); - } - else - errata_emit_nops (insn); - } - } - /* Instruction scheduling support. */ --- 5684,5689 ---- *************** ia64_reorg (void) *** 7583,7589 **** } } - fixup_errata (); emit_predicate_relation_info (); if (ia64_flag_var_tracking) --- 7442,7447 ---- Index: config/ia64/ia64.h =================================================================== RCS file: /cvs/gcc/gcc/gcc/config/ia64/ia64.h,v retrieving revision 1.191 diff -p -r1.191 ia64.h *** config/ia64/ia64.h 18 Jan 2005 12:01:31 -0000 1.191 --- config/ia64/ia64.h 17 Feb 2005 22:48:19 -0000 *************** extern int target_flags; *** 75,82 **** #define MASK_ILP32 0x00000020 /* Generate ILP32 code. */ - #define MASK_B_STEP 0x00000040 /* Emit code for Itanium B step. */ - #define MASK_REG_NAMES 0x00000080 /* Use in/loc/out register names. */ #define MASK_NO_SDATA 0x00000100 /* Disable sdata/scommon/sbss. */ --- 75,80 ---- *************** extern int target_flags; *** 113,120 **** #define TARGET_ILP32 (target_flags & MASK_ILP32) - #define TARGET_B_STEP (target_flags & MASK_B_STEP) - #define TARGET_REG_NAMES (target_flags & MASK_REG_NAMES) #define TARGET_NO_SDATA (target_flags & MASK_NO_SDATA) --- 111,116 ---- *************** extern int ia64_tls_size; *** 196,203 **** N_("Emit stop bits before and after volatile extended asms") }, \ { "no-volatile-asm-stop", -MASK_VOL_ASM_STOP, \ N_("Don't emit stop bits before and after volatile extended asms") }, \ - { "b-step", MASK_B_STEP, \ - N_("Emit code for Itanium (TM) processor B step")}, \ { "register-names", MASK_REG_NAMES, \ N_("Use in/loc/out register names")}, \ { "no-sdata", MASK_NO_SDATA, \ --- 192,197 ----