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Committed, Fix part of PR target/19065; an autoincrement-free mem constraint for CRIS.
- From: Hans-Peter Nilsson <hans-peter dot nilsson at axis dot com>
- To: gcc-patches at gcc dot gnu dot org, mark at codesourcery dot com
- Date: Mon, 28 Feb 2005 03:24:23 +0100
- Subject: Committed, Fix part of PR target/19065; an autoincrement-free mem constraint for CRIS.
This is necessary for PR target/19065. Actually, 'Q' was used
all along in cris.md to only mean (mem reg) and never (reg), so
the work there was mostly formatting adjustment and review to
make sure, which found the miss in "cmphi".
This change, particularly telling register allocation that Q is
a memory constraint, should have only beneficial effect, but
surprisingly this led to pessimized code (but correctness trumps
that). I'm opening a PR for the pessimization.
Tested cris-axis-elf, committed to trunk.
Mark, I'd really really want this on the 4.0 branch too.
Pretty please. Gi's a break; us maintainers of lowly
non-primary, non-secondary targets, for whom the 4.0 release is
not to be held up, no matter into how many pieces they would be
broken! (I humbly suggest that relation to be somewhat
reflexive).
I blame PR 20204 and the pessimization issue for me not making
it to commit this before the 4.0 branch (though I leave no
further explanation for the earlier delay; PR target/19065 was
opened last December).
Next, also necessary, is a follow-up patch for
libstdc++-v3/config/cpu/cris/atomicity.h.
(Not included is the copyright update line to cris.md)
PR target/19065.
* config/cris/cris.h (EXTRA_CONSTRAINT_Q): Accept only (mem (reg)),
not including (reg). Do not check for reg being CRIS_PC_REGNUM.
(EXTRA_MEMORY_CONSTRAINT): Define as 'Q'.
* config/cris/cris.md: Tweak comments referring to Q.
("cmpsi", "cmphi", "cmpqi", "*movsi_internal", "movhi")
("movstricthi", "movqi", "movstrictqi", "movsf", "addsi3")
("addhi3", "addqi3", "subsi3", "subhi3", "subqi3")
("*expanded_andsi", "*expanded_andhi", "*andhi_lowpart", "andqi3")
("*andqi_lowpart", "iorsi3", "iorhi3", "iorqi3", "uminsi3"):
Insert spaces in constraints to align alternatives vertically for
readability.
("cmphi"): Ditto. Add separate alternative for operand 0 "Q>",
operand 1: "M".
Index: gcc/config/cris/cris.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/cris/cris.h,v
retrieving revision 1.84
diff -c -p -r1.84 cris.h
*** gcc/config/cris/cris.h 8 Feb 2005 15:35:12 -0000 1.84
--- gcc/config/cris/cris.h 28 Feb 2005 02:13:14 -0000
*************** enum reg_class {NO_REGS, ALL_REGS, LIM_R
*** 772,785 ****
(C) == 'U' ? EXTRA_CONSTRAINT_U (X) : \
0)
#define EXTRA_CONSTRAINT_Q(X) \
( \
! /* Slottable addressing modes: \
! A register? FIXME: Unnecessary. */ \
! (BASE_P (X) && REGNO (X) != CRIS_PC_REGNUM) \
! /* Indirect register: [reg]? */ \
! || (GET_CODE (X) == MEM && BASE_P (XEXP (X, 0)) \
! && REGNO (XEXP (X, 0)) != CRIS_PC_REGNUM) \
)
#define EXTRA_CONSTRAINT_R(X) \
--- 772,785 ----
(C) == 'U' ? EXTRA_CONSTRAINT_U (X) : \
0)
+ #define EXTRA_MEMORY_CONSTRAINT(X, STR) ((X) == 'Q')
+
#define EXTRA_CONSTRAINT_Q(X) \
( \
! /* Just an indirect register (happens to also be \
! "all" slottable memory addressing modes not \
! covered by other constraints, i.e. '>'). */ \
! GET_CODE (X) == MEM && BASE_P (XEXP (X, 0)) \
)
#define EXTRA_CONSTRAINT_R(X) \
Index: gcc/config/cris/cris.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/cris/cris.md,v
retrieving revision 1.22
diff -c -p -r1.22 cris.md
*** gcc/config/cris/cris.md 24 Feb 2005 16:59:25 -0000 1.22
--- gcc/config/cris/cris.md 28 Feb 2005 02:13:14 -0000
***************
*** 91,99 ****
;; mode, but that would need more attributes and hairier, more error
;; prone code.
;;
! ;; There is an extra constraint, 'Q', which recognizes indirect reg,
! ;; except when the reg is pc. The constraints 'Q' and '>' together match
! ;; all possible memory operands that are slottable.
;; For other operands, you need to check if it has a valid "slottable"
;; quick-immediate operand, where the particular signedness-variation
;; may match the constraints 'I' or 'J'.), and include it in the
--- 91,99 ----
;; mode, but that would need more attributes and hairier, more error
;; prone code.
;;
! ;; There is an extra memory constraint, 'Q', which recognizes an indirect
! ;; register. The constraints 'Q' and '>' together match all possible
! ;; memory operands that are slottable.
;; For other operands, you need to check if it has a valid "slottable"
;; quick-immediate operand, where the particular signedness-variation
;; may match the constraints 'I' or 'J'.), and include it in the
***************
*** 268,275 ****
(define_insn "cmpsi"
[(set (cc0)
(compare
! (match_operand:SI 0 "nonimmediate_operand" "r,r,r,r,Q>,Q>,r,r,m,m")
! (match_operand:SI 1 "general_operand" "I,r,Q>,M,M,r,P,g,M,r")))]
""
"@
cmpq %1,%0
--- 268,275 ----
(define_insn "cmpsi"
[(set (cc0)
(compare
! (match_operand:SI 0 "nonimmediate_operand" "r,r,r, r,Q>,Q>,r,r,m,m")
! (match_operand:SI 1 "general_operand" "I,r,Q>,M,M, r, P,g,M,r")))]
""
"@
cmpq %1,%0
***************
*** 286,309 ****
(define_insn "cmphi"
[(set (cc0)
! (compare (match_operand:HI 0 "nonimmediate_operand" "r,r,Q>,Q>,r,m,m")
! (match_operand:HI 1 "general_operand" "r,Q>,M,r,g,M,r")))]
""
"@
cmp.w %1,%0
cmp.w %1,%0
test.w %0
cmp.w %0,%1
cmp.w %1,%0
test.w %0
cmp.w %0,%1"
! [(set_attr "slottable" "yes,yes,yes,yes,no,no,no")])
(define_insn "cmpqi"
[(set (cc0)
(compare
! (match_operand:QI 0 "nonimmediate_operand" "r,r,r,Q>,Q>,r,m,m")
! (match_operand:QI 1 "general_operand" "r,Q>,M,M,r,g,M,r")))]
""
"@
cmp.b %1,%0
--- 286,310 ----
(define_insn "cmphi"
[(set (cc0)
! (compare (match_operand:HI 0 "nonimmediate_operand" "r,r, r,Q>,Q>,r,m,m")
! (match_operand:HI 1 "general_operand" "r,Q>,M,M, r, g,M,r")))]
""
"@
cmp.w %1,%0
cmp.w %1,%0
test.w %0
+ test.w %0
cmp.w %0,%1
cmp.w %1,%0
test.w %0
cmp.w %0,%1"
! [(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
(define_insn "cmpqi"
[(set (cc0)
(compare
! (match_operand:QI 0 "nonimmediate_operand" "r,r, r,Q>,Q>,r,m,m")
! (match_operand:QI 1 "general_operand" "r,Q>,M,M, r, g,M,r")))]
""
"@
cmp.b %1,%0
***************
*** 993,1003 ****
(define_insn "*movsi_internal"
[(set
! (match_operand:SI 0 "nonimmediate_operand" "=r,r,r,Q>,r,Q>,g,r,r,r,g")
(match_operand:SI 1
;; FIXME: We want to put S last, but apparently g matches S.
;; It's a bug: an S is not a general_operand and shouldn't match g.
! "cris_general_operand_or_gotless_symbol" "r,Q>,M,M,I,r,M,n,!S,g,r"))]
""
"*
{
--- 994,1004 ----
(define_insn "*movsi_internal"
[(set
! (match_operand:SI 0 "nonimmediate_operand" "=r,r, r,Q>,r,Q>,g,r,r,r,g")
(match_operand:SI 1
;; FIXME: We want to put S last, but apparently g matches S.
;; It's a bug: an S is not a general_operand and shouldn't match g.
! "cris_general_operand_or_gotless_symbol" "r,Q>,M,M, I,r, M,n,!S,g,r"))]
""
"*
{
***************
*** 1206,1213 ****
(define_insn "movhi"
[(set
! (match_operand:HI 0 "nonimmediate_operand" "=r,r,r,Q>,r,Q>,r,r,r,g,g,r")
! (match_operand:HI 1 "general_operand" "r,Q>,M,M,I,r,L,O,n,M,r,g"))]
""
"*
{
--- 1207,1214 ----
(define_insn "movhi"
[(set
! (match_operand:HI 0 "nonimmediate_operand" "=r,r, r,Q>,r,Q>,r,r,r,g,g,r")
! (match_operand:HI 1 "general_operand" "r,Q>,M,M, I,r, L,O,n,M,r,g"))]
""
"*
{
***************
*** 1249,1256 ****
(define_insn "movstricthi"
[(set
(strict_low_part
! (match_operand:HI 0 "nonimmediate_operand" "+r,r,r,Q>,Q>,g,r,g"))
! (match_operand:HI 1 "general_operand" "r,Q>,M,M,r,M,g,r"))]
""
"@
move.w %1,%0
--- 1250,1257 ----
(define_insn "movstricthi"
[(set
(strict_low_part
! (match_operand:HI 0 "nonimmediate_operand" "+r,r, r,Q>,Q>,g,r,g"))
! (match_operand:HI 1 "general_operand" "r,Q>,M,M, r, M,g,r"))]
""
"@
move.w %1,%0
***************
*** 1264,1271 ****
[(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
(define_insn "movqi"
! [(set (match_operand:QI 0 "nonimmediate_operand" "=r,Q>,r,r,Q>,r,g,g,r,r")
! (match_operand:QI 1 "general_operand" "r,r,Q>,M,M,I,M,r,O,g"))]
""
"@
move.b %1,%0
--- 1265,1272 ----
[(set_attr "slottable" "yes,yes,yes,yes,yes,no,no,no")])
(define_insn "movqi"
! [(set (match_operand:QI 0 "nonimmediate_operand" "=r,Q>,r, r,Q>,r,g,g,r,r")
! (match_operand:QI 1 "general_operand" "r,r, Q>,M,M, I,M,r,O,g"))]
""
"@
move.b %1,%0
***************
*** 1286,1293 ****
(define_insn "movstrictqi"
[(set (strict_low_part
! (match_operand:QI 0 "nonimmediate_operand" "+r,Q>,r,r,Q>,g,g,r"))
! (match_operand:QI 1 "general_operand" "r,r,Q>,M,M,M,r,g"))]
""
"@
move.b %1,%0
--- 1287,1294 ----
(define_insn "movstrictqi"
[(set (strict_low_part
! (match_operand:QI 0 "nonimmediate_operand" "+r,Q>,r, r,Q>,g,g,r"))
! (match_operand:QI 1 "general_operand" "r,r, Q>,M,M, M,r,g"))]
""
"@
move.b %1,%0
***************
*** 1306,1313 ****
;; It will use clear, so we know ALL types of immediate 0 never change cc.
(define_insn "movsf"
! [(set (match_operand:SF 0 "nonimmediate_operand" "=r,Q>,r,r,Q>,g,g,r")
! (match_operand:SF 1 "general_operand" "r,r,Q>,G,G,G,r,g"))]
""
"@
move.d %1,%0
--- 1307,1314 ----
;; It will use clear, so we know ALL types of immediate 0 never change cc.
(define_insn "movsf"
! [(set (match_operand:SF 0 "nonimmediate_operand" "=r,Q>,r, r,Q>,g,g,r")
! (match_operand:SF 1 "general_operand" "r,r, Q>,G,G, G,r,g"))]
""
"@
move.d %1,%0
***************
*** 1720,1729 ****
add.d %M2,%M1,%M0\;ax\;add.d %H2,%H1,%H0")
(define_insn "addsi3"
! [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
(plus:SI
! (match_operand:SI 1 "register_operand" "%0,0,0,0,0,0,r,r")
! (match_operand:SI 2 "general_operand" "r,Q>,J,N,n,g,!To,0")))]
;; The last constraint is due to that after reload, the '%' is not
;; honored, and canonicalization doesn't care about keeping the same
--- 1721,1730 ----
add.d %M2,%M1,%M0\;ax\;add.d %H2,%H1,%H0")
(define_insn "addsi3"
! [(set (match_operand:SI 0 "register_operand" "=r,r, r,r,r,r,r, r")
(plus:SI
! (match_operand:SI 1 "register_operand" "%0,0, 0,0,0,0,r, r")
! (match_operand:SI 2 "general_operand" "r,Q>,J,N,n,g,!To,0")))]
;; The last constraint is due to that after reload, the '%' is not
;; honored, and canonicalization doesn't care about keeping the same
***************
*** 1773,1781 ****
[(set_attr "slottable" "yes,yes,yes,yes,no,no,no,yes")])
(define_insn "addhi3"
! [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
! (plus:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,r")
! (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))]
""
"@
add.w %2,%0
--- 1774,1782 ----
[(set_attr "slottable" "yes,yes,yes,yes,no,no,no,yes")])
(define_insn "addhi3"
! [(set (match_operand:HI 0 "register_operand" "=r,r, r,r,r,r")
! (plus:HI (match_operand:HI 1 "register_operand" "%0,0, 0,0,0,r")
! (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))]
""
"@
add.w %2,%0
***************
*** 1788,1796 ****
(set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
(define_insn "addqi3"
! [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r,r")
! (plus:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,0,r")
! (match_operand:QI 2 "general_operand" "r,Q>,J,N,O,g,!To")))]
""
"@
add.b %2,%0
--- 1789,1797 ----
(set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
(define_insn "addqi3"
! [(set (match_operand:QI 0 "register_operand" "=r,r, r,r,r,r,r")
! (plus:QI (match_operand:QI 1 "register_operand" "%0,0, 0,0,0,0,r")
! (match_operand:QI 2 "general_operand" "r,Q>,J,N,O,g,!To")))]
""
"@
add.b %2,%0
***************
*** 1824,1833 ****
sub.d %M2,%M1,%M0\;ax\;sub.d %H2,%H1,%H0")
(define_insn "subsi3"
! [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r,r,r")
(minus:SI
! (match_operand:SI 1 "register_operand" "0,0,0,0,0,0,0,r")
! (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g,!To")))]
""
;; This does not do the optimal: "addu.w 65535,r0" when %2 is negative.
--- 1825,1834 ----
sub.d %M2,%M1,%M0\;ax\;sub.d %H2,%H1,%H0")
(define_insn "subsi3"
! [(set (match_operand:SI 0 "register_operand" "=r,r, r,r,r,r,r,r")
(minus:SI
! (match_operand:SI 1 "register_operand" "0,0, 0,0,0,0,0,r")
! (match_operand:SI 2 "general_operand" "r,Q>,J,N,P,n,g,!To")))]
""
;; This does not do the optimal: "addu.w 65535,r0" when %2 is negative.
***************
*** 1845,1853 ****
[(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no")])
(define_insn "subhi3"
! [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r")
! (minus:HI (match_operand:HI 1 "register_operand" "0,0,0,0,0,r")
! (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))]
""
"@
sub.w %2,%0
--- 1846,1854 ----
[(set_attr "slottable" "yes,yes,yes,yes,no,no,no,no")])
(define_insn "subhi3"
! [(set (match_operand:HI 0 "register_operand" "=r,r, r,r,r,r")
! (minus:HI (match_operand:HI 1 "register_operand" "0,0, 0,0,0,r")
! (match_operand:HI 2 "general_operand" "r,Q>,J,N,g,!To")))]
""
"@
sub.w %2,%0
***************
*** 1860,1868 ****
(set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
(define_insn "subqi3"
! [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r")
! (minus:QI (match_operand:QI 1 "register_operand" "0,0,0,0,0,r")
! (match_operand:QI 2 "general_operand" "r,Q>,J,N,g,!To")))]
""
"@
sub.b %2,%0
--- 1861,1869 ----
(set_attr "cc" "normal,normal,clobber,clobber,normal,normal")])
(define_insn "subqi3"
! [(set (match_operand:QI 0 "register_operand" "=r,r, r,r,r,r")
! (minus:QI (match_operand:QI 1 "register_operand" "0,0, 0,0,0,r")
! (match_operand:QI 2 "general_operand" "r,Q>,J,N,g,!To")))]
""
"@
sub.b %2,%0
***************
*** 2734,2742 ****
;; improved reload pass.
(define_insn "*expanded_andsi"
! [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
! (and:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,r")
! (match_operand:SI 2 "general_operand" "I,r,Q>,g,!To")))]
""
"@
andq %2,%0
--- 2735,2743 ----
;; improved reload pass.
(define_insn "*expanded_andsi"
! [(set (match_operand:SI 0 "register_operand" "=r,r,r, r,r")
! (and:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0,r")
! (match_operand:SI 2 "general_operand" "I,r,Q>,g,!To")))]
""
"@
andq %2,%0
***************
*** 2810,2818 ****
;; Catch-all andhi3 pattern.
(define_insn "*expanded_andhi"
! [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
! (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0,r")
! (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))]
;; Sidenote: the tightening from "general_operand" to
;; "register_operand" for operand 1 actually increased the register
--- 2811,2819 ----
;; Catch-all andhi3 pattern.
(define_insn "*expanded_andhi"
! [(set (match_operand:HI 0 "register_operand" "=r,r,r, r,r,r,r")
! (and:HI (match_operand:HI 1 "register_operand" "%0,0,0, 0,0,0,r")
! (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))]
;; Sidenote: the tightening from "general_operand" to
;; "register_operand" for operand 1 actually increased the register
***************
*** 2835,2843 ****
(define_insn "*andhi_lowpart"
[(set (strict_low_part
! (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r"))
! (and:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,r")
! (match_operand:HI 2 "general_operand" "r,Q>,L,O,g,!To")))]
""
"@
and.w %2,%0
--- 2836,2844 ----
(define_insn "*andhi_lowpart"
[(set (strict_low_part
! (match_operand:HI 0 "register_operand" "=r,r, r,r,r,r"))
! (and:HI (match_operand:HI 1 "register_operand" "%0,0, 0,0,0,r")
! (match_operand:HI 2 "general_operand" "r,Q>,L,O,g,!To")))]
""
"@
and.w %2,%0
***************
*** 2850,2858 ****
(set_attr "cc" "normal,normal,normal,clobber,normal,normal")])
(define_insn "andqi3"
! [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r")
! (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,r")
! (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))]
""
"@
andq %2,%0
--- 2851,2859 ----
(set_attr "cc" "normal,normal,normal,clobber,normal,normal")])
(define_insn "andqi3"
! [(set (match_operand:QI 0 "register_operand" "=r,r,r, r,r,r")
! (and:QI (match_operand:QI 1 "register_operand" "%0,0,0, 0,0,r")
! (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))]
""
"@
andq %2,%0
***************
*** 2866,2874 ****
(define_insn "*andqi_lowpart"
[(set (strict_low_part
! (match_operand:QI 0 "register_operand" "=r,r,r,r,r"))
! (and:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,r")
! (match_operand:QI 2 "general_operand" "r,Q>,O,g,!To")))]
""
"@
and.b %2,%0
--- 2867,2875 ----
(define_insn "*andqi_lowpart"
[(set (strict_low_part
! (match_operand:QI 0 "register_operand" "=r,r, r,r,r"))
! (and:QI (match_operand:QI 1 "register_operand" "%0,0, 0,0,r")
! (match_operand:QI 2 "general_operand" "r,Q>,O,g,!To")))]
""
"@
and.b %2,%0
***************
*** 2887,2895 ****
;; with andsi3.
(define_insn "iorsi3"
! [(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r,r")
! (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,r")
! (match_operand:SI 2 "general_operand" "I,r,Q>,n,g,!To")))]
""
"@
orq %2,%0
--- 2888,2896 ----
;; with andsi3.
(define_insn "iorsi3"
! [(set (match_operand:SI 0 "register_operand" "=r,r,r, r,r,r")
! (ior:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0,0,r")
! (match_operand:SI 2 "general_operand" "I, r,Q>,n,g,!To")))]
""
"@
orq %2,%0
***************
*** 2902,2910 ****
(set_attr "cc" "normal,normal,normal,clobber,normal,normal")])
(define_insn "iorhi3"
! [(set (match_operand:HI 0 "register_operand" "=r,r,r,r,r,r,r")
! (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0,0,0,0,r")
! (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))]
""
"@
orq %2,%0
--- 2903,2911 ----
(set_attr "cc" "normal,normal,normal,clobber,normal,normal")])
(define_insn "iorhi3"
! [(set (match_operand:HI 0 "register_operand" "=r,r,r, r,r,r,r")
! (ior:HI (match_operand:HI 1 "register_operand" "%0,0,0, 0,0,0,r")
! (match_operand:HI 2 "general_operand" "I,r,Q>,L,O,g,!To")))]
""
"@
orq %2,%0
***************
*** 2918,2926 ****
(set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")])
(define_insn "iorqi3"
! [(set (match_operand:QI 0 "register_operand" "=r,r,r,r,r,r")
! (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0,0,0,r")
! (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))]
""
"@
orq %2,%0
--- 2919,2927 ----
(set_attr "cc" "clobber,normal,normal,normal,clobber,normal,normal")])
(define_insn "iorqi3"
! [(set (match_operand:QI 0 "register_operand" "=r,r,r, r,r,r")
! (ior:QI (match_operand:QI 1 "register_operand" "%0,0,0, 0,0,r")
! (match_operand:QI 2 "general_operand" "I,r,Q>,O,g,!To")))]
""
"@
orq %2,%0
***************
*** 3340,3348 ****
;; normal code too.
(define_insn "uminsi3"
! [(set (match_operand:SI 0 "register_operand" "=r,r,r,r")
! (umin:SI (match_operand:SI 1 "register_operand" "%0,0,0,r")
! (match_operand:SI 2 "general_operand" "r,Q>,g,!STo")))]
""
"*
{
--- 3341,3349 ----
;; normal code too.
(define_insn "uminsi3"
! [(set (match_operand:SI 0 "register_operand" "=r,r, r,r")
! (umin:SI (match_operand:SI 1 "register_operand" "%0,0, 0,r")
! (match_operand:SI 2 "general_operand" "r,Q>,g,!STo")))]
""
"*
{
***************
*** 3858,3864 ****
}")
;; Accept *anything* as operand 1. Accept operands for operand 0 in
! ;; order of preference (Q includes r, but r is shorter, faster)
(define_insn "*expanded_call"
[(call (mem:QI (match_operand:SI
--- 3859,3865 ----
}")
;; Accept *anything* as operand 1. Accept operands for operand 0 in
! ;; order of preference.
(define_insn "*expanded_call"
[(call (mem:QI (match_operand:SI
brgds, H-P