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fix some ia64 compat failures


Fixes 

FAIL: tmpdir-gcc.dg-struct-layout-1/t001 c_compat_x_tst.o-c_compat_y_tst.o execute
FAIL: tmpdir-gcc.dg-struct-layout-1/t011 c_compat_x_tst.o compile
FAIL: tmpdir-gcc.dg-struct-layout-1/t024 c_compat_x_tst.o-c_compat_y_tst.o execute

The comment is pretty self-explanitory.


r~


        * config/ia64/ia64.c (ia64_function_value): Use PARALLEL for
        aggregates with XF/XCmode.

Index: config/ia64/ia64.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/ia64/ia64.c,v
retrieving revision 1.336
diff -c -p -d -r1.336 ia64.c
*** config/ia64/ia64.c	30 Dec 2004 03:07:49 -0000	1.336
--- config/ia64/ia64.c	30 Dec 2004 08:57:37 -0000
*************** ia64_function_value (tree valtype, tree 
*** 3522,3529 ****
--- 3522,3545 ----
      return gen_rtx_REG (mode, FR_ARG_FIRST);
    else
      {
+       bool need_parallel = false;
+ 
+       /* In big-endian mode, we need to manage the layout of aggregates
+ 	 in the registers so that we get the bits properly aligned in
+ 	 the highpart of the registers.  */
        if (BYTES_BIG_ENDIAN
  	  && (mode == BLKmode || (valtype && AGGREGATE_TYPE_P (valtype))))
+ 	need_parallel = true;
+ 
+       /* Something like struct S { long double x; char a[0] } is not an
+ 	 HFA structure, and therefore doesn't go in fp registers.  But
+ 	 the middle-end will give it XFmode anyway, and XFmode values
+ 	 don't normally fit in integer registers.  So we need to smuggle
+ 	 the value inside a parallel.  */
+       else if (mode == XFmode || mode == XCmode)
+ 	need_parallel = true;
+ 
+       if (need_parallel)
  	{
  	  rtx loc[8];
  	  int offset;
*************** ia64_function_value (tree valtype, tree 
*** 3542,3549 ****
  	    }
  	  return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
  	}
!       else
! 	return gen_rtx_REG (mode, GR_RET_FIRST);
      }
  }
  
--- 3558,3565 ----
  	    }
  	  return gen_rtx_PARALLEL (mode, gen_rtvec_v (i, loc));
  	}
! 
!       return gen_rtx_REG (mode, GR_RET_FIRST);
      }
  }
  


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