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"fix" target/19102


So exceedingly ugly I'm embarrased posting it.  The Problem is two-fold.

(1) Not all the move patterns are updated on the branch to support SSE1.
    That's more churn on the branch than is necessary to support the ABI,
    so I'm not going to try.  Fixing that is the subject of the second hunk.

(2) With -march=pentium[34], it's *possible* for folks to suddenly start
    getting SSE registers used when we run out of integer registers.  This
    is going to surprise some kernel folk.  I don't like that suddenly
    starting to happen in the middle of a release branch.  So the first
    hunk is there to force the compiler to do all moves between units
    through memory.  Which is enough to convince the compiler not to
    randomly allocate integer variables to SSE registers in *most* cases.
    Nothing short of disabling SSE is 100% certain, however.

    For 4.0, folks will just have to remember to use the correct set of
    compilation flags.  But as I said, I'm not happy about this change of
    behaviour on the existing release branch.

Tested on i686 and x86-64 linux.


r~


        PR target/19102
        * config/i386/i386.c (x86_inter_unit_moves): Disable.
        (ix86_hard_regno_mode_ok): Disallow SSE2 and MMX scalar modes
        in SSE registers when only SSE1 enabled.

Index: config/i386/i386.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.c,v
retrieving revision 1.635.2.18
diff -c -p -d -r1.635.2.18 i386.c
*** config/i386/i386.c	20 Dec 2004 05:37:36 -0000	1.635.2.18
--- config/i386/i386.c	23 Dec 2004 01:29:01 -0000
*************** const int x86_sse_typeless_stores = m_AT
*** 522,528 ****
  const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4;
  const int x86_use_ffreep = m_ATHLON_K8;
  const int x86_rep_movl_optimal = m_386 | m_PENT | m_PPRO | m_K6;
! const int x86_inter_unit_moves = ~(m_ATHLON_K8);
  const int x86_ext_80387_constants = m_K6 | m_ATHLON | m_PENT4 | m_PPRO;
  
  /* In case the average insn count for single function invocation is
--- 522,535 ----
  const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4;
  const int x86_use_ffreep = m_ATHLON_K8;
  const int x86_rep_movl_optimal = m_386 | m_PENT | m_PPRO | m_K6;
! 
! /* ??? HACK!  The following is a lie.  SSE can hold e.g. SImode, and
!    indeed *must* be able to hold SImode so that SSE2 shifts are able
!    to work right.  But this can result in some mighty surprising 
!    register allocation when building kernels.  Turning this off should
!    make us less likely to all-of-the-sudden select an SSE register.  */
! const int x86_inter_unit_moves = 0;  /* ~(m_ATHLON_K8) */
! 
  const int x86_ext_80387_constants = m_K6 | m_ATHLON | m_PENT4 | m_PPRO;
  
  /* In case the average insn count for single function invocation is
*************** ix86_hard_regno_mode_ok (int regno, enum
*** 14927,14932 ****
--- 14934,14945 ----
      return VALID_FP_MODE_P (mode);
    if (SSE_REGNO_P (regno))
      {
+       /* HACK!  We didn't change all of the constraints for SSE1 for the
+ 	 scalar modes on the branch.  Fortunately, they're not required
+ 	 for ABI compatibility.  */
+       if (!TARGET_SSE2 && !VECTOR_MODE_P (mode))
+ 	return VALID_SSE_REG_MODE (mode);
+ 
        /* We implement the move patterns for all vector modes into and
           out of SSE registers, even when no operation instructions
           are available.  */


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