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Rename TARGET_SSE_PARTIAL_REGS


There are too many uses of "partial" in the x86 backend, and this one
didn't have the same denotation as the others, which made it confusing.


r~


        * config/i386/i386.c (x86_sse_split_regs): Rename from
        x86_sse_partial_regs.
        * config/i386/i386.h (x86_sse_split_regs): Likewise.
        (TARGET_SSE_SPLIT_REGS): Rename from TARGET_SSE_PARTIAL_REGS.
        * config/i386/i386.md (*): Update to match.  Remove two
        floatsisf splitters that use it.

Index: config/i386/i386.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.c,v
retrieving revision 1.759
diff -u -p -r1.759 i386.c
--- config/i386/i386.c	21 Dec 2004 16:06:49 -0000	1.759
+++ config/i386/i386.c	21 Dec 2004 16:42:38 -0000
@@ -562,10 +562,11 @@ const int x86_decompose_lea = m_PENT4 | 
 const int x86_shift1 = ~m_486;
 const int x86_arch_always_fancy_math_387 = m_PENT | m_PPRO | m_ATHLON_K8 | m_PENT4 | m_NOCONA;
 const int x86_sse_partial_reg_dependency = m_PENT4 | m_NOCONA | m_PPRO;
-/* Set for machines where the type and dependencies are resolved on SSE register
-   parts instead of whole registers, so we may maintain just lower part of
-   scalar values in proper format leaving the upper part undefined.  */
-const int x86_sse_partial_regs = m_ATHLON_K8;
+/* Set for machines where the type and dependencies are resolved on SSE
+   register parts instead of whole registers, so we may maintain just
+   lower part of scalar values in proper format leaving the upper part
+   undefined.  */
+const int x86_sse_split_regs = m_ATHLON_K8;
 const int x86_sse_typeless_stores = m_ATHLON_K8;
 const int x86_sse_load0_by_pxor = m_PPRO | m_PENT4 | m_NOCONA;
 const int x86_use_ffreep = m_ATHLON_K8;
Index: config/i386/i386.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.h,v
retrieving revision 1.411
diff -u -p -r1.411 i386.h
--- config/i386/i386.h	21 Dec 2004 16:06:50 -0000	1.411
+++ config/i386/i386.h	21 Dec 2004 16:42:38 -0000
@@ -243,9 +243,9 @@ extern const int x86_partial_reg_depende
 extern const int x86_accumulate_outgoing_args, x86_prologue_using_move;
 extern const int x86_epilogue_using_move, x86_decompose_lea;
 extern const int x86_arch_always_fancy_math_387, x86_shift1;
-extern const int x86_sse_partial_reg_dependency, x86_sse_partial_regs;
+extern const int x86_sse_partial_reg_dependency, x86_sse_split_regs;
 extern const int x86_sse_typeless_stores, x86_sse_load0_by_pxor;
-extern const int x86_use_ffreep, x86_sse_partial_regs_for_cvtsd2ss;
+extern const int x86_use_ffreep;
 extern const int x86_inter_unit_moves, x86_schedule;
 extern const int x86_use_bt;
 extern int x86_prefetch_sse;
@@ -286,7 +286,7 @@ extern int x86_prefetch_sse;
 #define TARGET_PARTIAL_REG_DEPENDENCY (x86_partial_reg_dependency & TUNEMASK)
 #define TARGET_SSE_PARTIAL_REG_DEPENDENCY \
 				      (x86_sse_partial_reg_dependency & TUNEMASK)
-#define TARGET_SSE_PARTIAL_REGS (x86_sse_partial_regs & TUNEMASK)
+#define TARGET_SSE_SPLIT_REGS (x86_sse_split_regs & TUNEMASK)
 #define TARGET_SSE_TYPELESS_STORES (x86_sse_typeless_stores & TUNEMASK)
 #define TARGET_SSE_LOAD0_BY_PXOR (x86_sse_load0_by_pxor & TUNEMASK)
 #define TARGET_MEMORY_MISMATCH_STALL (x86_memory_mismatch_stall & TUNEMASK)
Index: config/i386/i386.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.md,v
retrieving revision 1.587
diff -u -p -r1.587 i386.md
--- config/i386/i386.md	21 Dec 2004 16:06:50 -0000	1.587
+++ config/i386/i386.md	21 Dec 2004 16:42:40 -0000
@@ -2268,7 +2268,7 @@
 		 (if_then_else
 		   (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
 			    (const_int 0))
-			(ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
+			(ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
 			    (const_int 0)))
 		   (const_string "V4SF")
 		   (const_string "SF"))
@@ -2358,7 +2358,7 @@
 		 (if_then_else
 		   (ior (ne (symbol_ref "TARGET_SSE_PARTIAL_REG_DEPENDENCY")
 			    (const_int 0))
-			(ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
+			(ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
 			    (const_int 0)))
 		   (const_string "V4SF")
 		   (const_string "SF"))
@@ -2554,7 +2554,7 @@
 		  of register.  */
 	       (eq_attr "alternative" "7")
 		 (if_then_else
-		   (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
+		   (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
 		       (const_int 0))
 		   (const_string "V1DF")
 		   (const_string "DF"))
@@ -2674,7 +2674,7 @@
 		  of register.  */
 	       (eq_attr "alternative" "7")
 		 (if_then_else
-		   (ne (symbol_ref "TARGET_SSE_PARTIAL_REGS")
+		   (ne (symbol_ref "TARGET_SSE_SPLIT_REGS")
 		       (const_int 0))
 		   (const_string "V1DF")
 		   (const_string "DF"))
@@ -4480,23 +4480,6 @@
    (set_attr "athlon_decode" "vector,double")
    (set_attr "fp_int_src" "true")])
 
-; Avoid possible reformatting penalty on the destination by first
-; zeroing it out
-(define_split
-  [(set (match_operand:SF 0 "register_operand" "")
-	(float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
-  "reload_completed
-   && TARGET_SSE_MATH && TARGET_SSE_PARTIAL_REGS
-   && SSE_REG_P (operands[0])"
-  [(const_int 0)]
-{
-  rtx dest;
-  dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
-  emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
-  emit_insn (gen_cvtsi2ss (dest, dest, operands[1]));
-  DONE;
-})
-
 (define_insn "*floatsisf2_i387"
   [(set (match_operand:SF 0 "register_operand" "=f,f")
 	(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
@@ -4538,23 +4521,6 @@
    (set_attr "athlon_decode" "vector,double")
    (set_attr "fp_int_src" "true")])
 
-; Avoid possible reformatting penalty on the destination by first
-; zeroing it out
-(define_split
-  [(set (match_operand:SF 0 "register_operand" "")
-	(float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
-  "reload_completed
-   && TARGET_64BIT && TARGET_SSE_MATH && TARGET_SSE_PARTIAL_REGS
-   && SSE_REG_P (operands[0])"
-  [(const_int 0)]
-{
-  rtx dest;
-  dest = simplify_gen_subreg (V4SFmode, operands[0], SFmode, 0);
-  emit_insn (gen_sse_clrv4sf (dest, CONST0_RTX (V4SFmode)));
-  emit_insn (gen_cvtsi2ssq (dest, dest, operands[1]));
-  DONE;
-})
-
 (define_insn "*floatdisf2_i387"
   [(set (match_operand:SF 0 "register_operand" "=f,f")
 	(float:SF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
@@ -18266,8 +18232,7 @@
    (set (match_dup 0) (ior:V2DF (match_dup 6)
 			        (match_dup 7)))]
 {
-  if (GET_MODE (operands[2]) == DFmode
-      && TARGET_SSE_PARTIAL_REGS && !optimize_size)
+  if (TARGET_SSE_SPLIT_REGS && !optimize_size)
     {
       rtx op = simplify_gen_subreg (V2DFmode, operands[2], DFmode, 0);
       emit_insn (gen_sse2_unpcklpd (op, op, op));
@@ -18429,8 +18394,7 @@
   [(set (match_dup 0) (match_op_dup 1 [(match_dup 0) (match_dup 5)]))
    (set (match_dup 8) (and:V2DF (match_dup 6) (match_dup 7)))]
 {
-  if (TARGET_SSE_PARTIAL_REGS && !optimize_size
-      && GET_MODE (operands[2]) == DFmode)
+  if (TARGET_SSE_SPLIT_REGS && !optimize_size)
     {
       if (REG_P (operands[2]))
 	{


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