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[PATCH, i386]: Unify TARGET_SSE_MATH for sqrt* patterns


Hello!

This patch unifies TARGET_SSE_MATH for sqrt* patterns. Patch is bootstrapped i686-pc-linux-gnu, regtested c,c++.

2004-12-16 Uros Bizjak <uros@kss-loka.si>

       * config/i386/i386.md (sqrt{s,d}f2_1, sqrt{s,d}f2_1_sse_only,
       sqrt{s,d}f2_i387): Unify enable constraint with respect to
       TARGET_SSE, TARGET_SSE2, TARGET_USE_FANCY_MATH_387,
       TARGET_SSE_MATH and TARGET_MIX_SSE_I387.
       (sqrt{s,d}f2_1): Rename to *sqrt{s,d}f2_mixed.
       (sqrt{s,d}f2_1_sse_only): Rename to *sqrt{s,d}f2_sse.
       (sqrt{s,d}f2_i387): Rename to *sqrt{s,d}f2_i387.
       (*sqrtextendsfdf2): Also enable for TARGET_MIX_SSE_I387.
       (*sqrtextend?f?f2): Rename to *sqrtextendsfdf2_i387.

Uros.
Index: config/i386/i386.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.md,v
retrieving revision 1.577
diff -u -p -r1.577 i386.md
--- config/i386/i386.md	16 Dec 2004 06:35:57 -0000	1.577
+++ config/i386/i386.md	16 Dec 2004 08:23:13 -0000
@@ -14647,11 +14647,10 @@
     operands[1] = force_reg (SFmode, operands[1]);
 })
 
-(define_insn "sqrtsf2_1"
+(define_insn "*sqrtsf2_mixed"
   [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
 	(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
-  "TARGET_USE_FANCY_MATH_387
-   && (TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
+  "TARGET_USE_FANCY_MATH_387 && TARGET_MIX_SSE_I387"
   "@
    fsqrt
    sqrtss\t{%1, %0|%0, %1}"
@@ -14659,20 +14658,19 @@
    (set_attr "mode" "SF,SF")
    (set_attr "athlon_decode" "direct,*")])
 
-(define_insn "sqrtsf2_1_sse_only"
+(define_insn "*sqrtsf2_sse"
   [(set (match_operand:SF 0 "register_operand" "=x")
 	(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
-  "TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
+  "TARGET_SSE_MATH && !(TARGET_USE_FANCY_MATH_387 && TARGET_MIX_SSE_I387)"
   "sqrtss\t{%1, %0|%0, %1}"
   [(set_attr "type" "sse")
    (set_attr "mode" "SF")
    (set_attr "athlon_decode" "*")])
 
-(define_insn "sqrtsf2_i387"
+(define_insn "*sqrtsf2_i387"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
-  "TARGET_USE_FANCY_MATH_387
-   && !TARGET_SSE_MATH"
+  "TARGET_USE_FANCY_MATH_387"
   "fsqrt"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "SF")
@@ -14681,18 +14679,16 @@
 (define_expand "sqrtdf2"
   [(set (match_operand:DF 0 "register_operand" "")
 	(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
-  "TARGET_USE_FANCY_MATH_387
-   || (TARGET_SSE2 && TARGET_SSE_MATH)"
+  "TARGET_USE_FANCY_MATH_387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
 {
-  if (!TARGET_SSE2 || !TARGET_SSE_MATH)
+  if (!(TARGET_SSE2 && TARGET_SSE_MATH))
     operands[1] = force_reg (DFmode, operands[1]);
 })
 
-(define_insn "sqrtdf2_1"
+(define_insn "*sqrtdf2_mixed"
   [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
 	(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
-  "TARGET_USE_FANCY_MATH_387
-   && (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
+  "TARGET_USE_FANCY_MATH_387 && TARGET_SSE2 && TARGET_MIX_SSE_I387"
   "@
    fsqrt
    sqrtsd\t{%1, %0|%0, %1}"
@@ -14700,31 +14696,31 @@
    (set_attr "mode" "DF,DF")
    (set_attr "athlon_decode" "direct,*")])
 
-(define_insn "sqrtdf2_1_sse_only"
+(define_insn "*sqrtdf2_sse"
   [(set (match_operand:DF 0 "register_operand" "=Y")
 	(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
-  "TARGET_SSE2 && TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
+  "TARGET_SSE2 && TARGET_SSE_MATH
+   && !(TARGET_USE_FANCY_MATH_387 && TARGET_MIX_SSE_I387)"
   "sqrtsd\t{%1, %0|%0, %1}"
   [(set_attr "type" "sse")
    (set_attr "mode" "DF")
    (set_attr "athlon_decode" "*")])
 
-(define_insn "sqrtdf2_i387"
+(define_insn "*sqrtdf2_i387"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
-  "TARGET_USE_FANCY_MATH_387
-   && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
+  "TARGET_USE_FANCY_MATH_387"
   "fsqrt"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "DF")
    (set_attr "athlon_decode" "direct")])
 
-(define_insn "*sqrtextendsfdf2"
+(define_insn "*sqrtextendsfdf2_i387"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(sqrt:DF (float_extend:DF
 		  (match_operand:SF 1 "register_operand" "0"))))]
   "TARGET_USE_FANCY_MATH_387
-   && !(TARGET_SSE2 && TARGET_SSE_MATH)"
+   && (!(TARGET_SSE2 && TARGET_SSE_MATH) || TARGET_MIX_SSE_I387)"
   "fsqrt"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "DF")
@@ -14740,20 +14736,20 @@
    (set_attr "mode" "XF")
    (set_attr "athlon_decode" "direct")])
 
-(define_insn "*sqrtextenddfxf2"
+(define_insn "*sqrtextendsfxf2_i387"
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(sqrt:XF (float_extend:XF
-		  (match_operand:DF 1 "register_operand" "0"))))]
+		  (match_operand:SF 1 "register_operand" "0"))))]
   "TARGET_USE_FANCY_MATH_387"
   "fsqrt"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "XF")
    (set_attr "athlon_decode" "direct")])
 
-(define_insn "*sqrtextendsfxf2"
+(define_insn "*sqrtextenddfxf2_i387"
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(sqrt:XF (float_extend:XF
-		  (match_operand:SF 1 "register_operand" "0"))))]
+		  (match_operand:DF 1 "register_operand" "0"))))]
   "TARGET_USE_FANCY_MATH_387"
   "fsqrt"
   [(set_attr "type" "fpspc")

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