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[PATCH, i386] Unify TARGET_SSE_MATH and TARGET_MIX_SSE_I387 in insnconstraints


Hello!

There is a big mess regarding TARGET_SSE_MATH and TARGET_MIX_SSE_I387 handling in i386.md file. Actually every pattern handles these macros in its own way and it is very difficult to figure out the conditions under which certain pattern is enabled.

I have encoutered a problem with float* patterns, which have wrong enable condition defined, so SSE cvtsi2s{s,d} instruction was
generated unconditinally for -mfpmath=387,sse and -mfpmath=i387. This is int->float conversion instruction, and i387 insn is quite faster than SSE one. Additional trouble with this insn is, that it converts from integer to SSE register, so additional sse->mem>fp moves were needed to get value into FP register. The produced asm code was horrible, something like this:
...
cvtsi2ss 12(%ebp), %xmm0
movss %xmm0, -8(%ebp)
flds -8(%ebp)
...


To avoid this problems, I would like to propose unified handling of TARGET_SSE_MATH and TARGET_MIX_SSE_I387 macros in following way:

SF pattern that can be implemented with either sse or i387 code would have a constraint:
"TARGET_80387 || TARGET_SSE_MATH"
When SF i387 insn should be generated its constraint would be:
"TARGET_80387 && !TARGET_SSE_MATH"
SF SSE pattern:
"TARGET_SSE_MATH && !TARGET_MIX_SSE_I387"
SF mixed pattern:
"TARGET_80387 && TARGET_MIX_SSE_I387"


DF pattern that can be implemented with either sse or i387 code:
  "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
DF i387 pattern:
 "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
DF SSE pattern:
 "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_MIX_SSE_I387"
DF mixed pattern:
 "TARGET_80387 && TARGET_SSE2 && TARGET_MIX_SSE_I387"

In this way, TARGET_64BIT "float" pattern could easily be added as:
SF enabled:
 "TARGET_80387 || (TARGET_64BIT && TARGET_SSE_MATH)"
SF i387:
 "TARGET_80387 && !(TARGET_64BIT && TARGET_SSE_MATH)"
SF sse:
 "TARGET_64BIT && TARGET_SSE_MATH && !TARGET_MIX_SSE_I387"
SF mixed:
 "TARGET_80387 && TARGET_64BIT && TARGET_MIX_SSE_I387"

DF 64bit:
DF enabled:
 "TARGET_80387 || (TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH)"
DF i387:
 "TARGET_80387 && !(TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH)"
DF sse:
 "TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_MIX_SSE_I387"
DF mixed:
 "TARGET_80387 && TARGET_64BIT && TARGET_SSE2 && TARGET_MIX_SSE_I387"

I would like to point out that TARGET_SSE_MATH enables TARGET_SSE, and TARGET_MIX_SSE_I387 enables TARGET_SSE_MATH _and_ TARGET_SSE. By replacing TARGET_80387 with TARGET_USE_FANCY_MATH_387, fsqrt patterns can be handled.

It would also be very nice to unify pattern names in some logical way. I would like to propose names like: "whatever_i387", "whatever_sse" and "whatever_mixed".

Attached patch implements proposed solution for all FP operators that can be implemented in both sse and i387 form: (add, sub, mul, div, sqrt). This solution is also implemented for float* patterns. The patch was bootstrapped for i686-pc-linux-gnu, regression testing is in progress. As the patch is already big, I will prepare a followup patch to also change fix* patterns this way, where cvttsd2si is faster than fistp everywhere and perhaps with the proposed implementation of new fisttp insn.

In addition, povray-3.50c was built using combinations of -march={pentium, pentium3 and pentium4} with -mfpmath=387, -mfpmath=sse and -mfpmath=sse,387. Asm code was checked for correct instructions and a standard povray benchmark was run, where resulting picture was visually checked for correctnes.

The patch may look big, but it is only a mechanical change/rename thing following proposed solutions.

2004-12-08 Uros Bizjak <uros@kss-loka.si>

   * config/i386/i386.md (floathisf2, *floathisf2_1, floatsisf2,
   *floatsisf2_i387, *floatsisf2_sse, floatdisf2,
   *floatdisf2_i387_only, *floatdisf2_i387, *floatdisf2_sse,
   floathidf2, *floathidf2_1, *floatsidf2_i387, *floatsidf2_sse,
   floatdidf2, *floatdidf2_i387_only, *floatdidf2_i387,
   *floatdidf2_sse, floatunssisf2, floatunsdisf2, floatunsdidf2,
   *fop_sf_comm_nosse, *fop_sf_comm, *fop_sf_comm_sse,
   *fop_df_comm_nosse, *fop_df_comm, *fop_df_comm_sse,
   *fop_sf_1_nosse, *fop_sf_1, *fop_sf_1_sse, *fop_sf_2,
   *fop_sf_3, *fop_df_1_nosse, *fop_df_1, *fop_df_1_sse,
   *fop_df_2, *fop_df_3, *fop_df_4, *fop_df_5, *fop_df_6,
   *fop_xf_1, *fop_xf_2, *fop_xf_3, *fop_xf_4, *fop_xf_5,
   *fop_xf_6, sqrtsf2_1, sqrtsf2_1_sse_only, sqrtsf2_i387,
   sqrtdf2, sqrtdf2_1, sqrtdf2_1_sse_only, sqrtdf2_i387,
   *sqrtextendsfdf2, *mindf): Unify enable constraint with
   respect to TARGET_80387, TARGET_64BIT, TARGET_SSE,
   TARGET_SSE2, TARGET_SSE_MATH and TARGET_MIX_SSE_I387.
   (*float?i?f2_1): Rename to *float?i?f2_i387.
   (*float?i?f_i387): Rename to *float?i?f2_mixed.
   (*float?i?f2_i387_only): Rename to *float?i?f2_i387.
   (float?ixf2): Penalize integer register constraint.
   (*fop_?f_comm_nosse, *fop_?f_1_nosse): Rename to
   *fop_?f_comm_i387, *fop_?f_1_i387
   (*fop_?f_comm, *fop_?f_1): Rename to *fop_?f_comm_mixed,
   *fop_?f_1_mixed.
   (*fop_df_{2,3,4,5,6}): Rename to *fop_df_{2,3,4,5,6}_i387.
   (*fop_xf_{2,3,4,5,6}): Rename to *fop_xf_{2,3,4,5,6}_i387.
   (sqrtsf2_1, sqrtdf2_1): Rename to *sqrtsf2_mixed and
   *sqrtdf2_mixed.
   (sqrtsf2_i387, sqrtdf2_i387): Rename to *sqrtsf2_i387 and
   *sqrtdf2_i387.
   (sqrtsf2_1_sse_only, sqrtdf2_1_sse_only): Rename to
   *sqrtsf2_sse and *sqrtdf2_sse.

Uros.
Index: gcc/config/i386/i386.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/i386/i386.md,v
retrieving revision 1.567
diff -u -p -r1.567 i386.md
--- gcc/config/i386/i386.md	8 Dec 2004 06:50:56 -0000	1.567
+++ gcc/config/i386/i386.md	8 Dec 2004 16:16:52 -0000
@@ -4440,9 +4440,9 @@
 (define_expand "floathisf2"
   [(set (match_operand:SF 0 "register_operand" "")
 	(float:SF (match_operand:HI 1 "nonimmediate_operand" "")))]
-  "TARGET_SSE || TARGET_80387"
+  "TARGET_80387 || TARGET_SSE_MATH"
 {
-  if (TARGET_SSE && TARGET_SSE_MATH)
+  if (TARGET_SSE_MATH)
     {
       emit_insn (gen_floatsisf2 (operands[0],
 				 convert_to_mode (SImode, operands[1], 0)));
@@ -4450,10 +4450,10 @@
     }
 })
 
-(define_insn "*floathisf2_1"
+(define_insn "*floathisf2_i387"
   [(set (match_operand:SF 0 "register_operand" "=f,f")
-	(float:SF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
-  "TARGET_80387 && (!TARGET_SSE || !TARGET_SSE_MATH)"
+	(float:SF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
+  "TARGET_80387 && !TARGET_SSE_MATH"
   "@
    fild%z1\t%1
    #"
@@ -4464,39 +4464,51 @@
 (define_expand "floatsisf2"
   [(set (match_operand:SF 0 "register_operand" "")
 	(float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
-  "TARGET_SSE || TARGET_80387"
+  "TARGET_80387 || TARGET_SSE_MATH"
   "")
 
 (define_insn "*floatsisf2_i387"
-  [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
-	(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
-  "TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
+  [(set (match_operand:SF 0 "register_operand" "=f,f")
+	(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
+  "TARGET_80387 && !TARGET_SSE_MATH"
   "@
    fild%z1\t%1
-   #
-   cvtsi2ss\t{%1, %0|%0, %1}
-   cvtsi2ss\t{%1, %0|%0, %1}"
-  [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
+   #"
+  [(set_attr "type" "fmov,multi")
    (set_attr "mode" "SF")
-   (set_attr "athlon_decode" "*,*,vector,double")
    (set_attr "fp_int_src" "true")])
 
 (define_insn "*floatsisf2_sse"
   [(set (match_operand:SF 0 "register_operand" "=x,x")
 	(float:SF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
-  "TARGET_SSE"
+  "TARGET_SSE_MATH && !TARGET_MIX_SSE_I387"
   "cvtsi2ss\t{%1, %0|%0, %1}"
   [(set_attr "type" "sseicvt")
    (set_attr "mode" "SF")
    (set_attr "athlon_decode" "vector,double")
    (set_attr "fp_int_src" "true")])
 
+(define_insn "*floatsisf2_mixed"
+  [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
+	(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
+  "TARGET_80387 && TARGET_MIX_SSE_I387"
+  "@
+   fild%z1\t%1
+   #
+   cvtsi2ss\t{%1, %0|%0, %1}
+   cvtsi2ss\t{%1, %0|%0, %1}"
+  [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
+   (set_attr "mode" "SF")
+   (set_attr "athlon_decode" "*,*,vector,double")
+   (set_attr "fp_int_src" "true")])
+
 ; Avoid possible reformatting penalty on the destination by first
 ; zeroing it out
 (define_split
   [(set (match_operand:SF 0 "register_operand" "")
 	(float:SF (match_operand:SI 1 "nonimmediate_operand" "")))]
-  "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
+  "reload_completed
+   && TARGET_80387 && TARGET_SSE_PARTIAL_REGS
    && SSE_REG_P (operands[0])"
   [(const_int 0)]
 {
@@ -4510,13 +4522,13 @@
 (define_expand "floatdisf2"
   [(set (match_operand:SF 0 "register_operand" "")
 	(float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
-  "(TARGET_64BIT && TARGET_SSE) || TARGET_80387"
+  "TARGET_80387 || (TARGET_64BIT && TARGET_SSE_MATH)"
   "")
 
-(define_insn "*floatdisf2_i387_only"
-  [(set (match_operand:SF 0 "register_operand" "=f,?f")
-	(float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
-  "TARGET_80387 && (!TARGET_SSE || !TARGET_64BIT || TARGET_MIX_SSE_I387)"
+(define_insn "*floatdisf2_i387"
+  [(set (match_operand:SF 0 "register_operand" "=f,f")
+	(float:SF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
+  "TARGET_80387 && !(TARGET_64BIT && TARGET_SSE_MATH)"
   "@
    fild%z1\t%1
    #"
@@ -4524,10 +4536,20 @@
    (set_attr "mode" "SF")
    (set_attr "fp_int_src" "true")])
 
-(define_insn "*floatdisf2_i387"
+(define_insn "*floatdisf2_sse"
+  [(set (match_operand:SF 0 "register_operand" "=x,x")
+	(float:SF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
+  "TARGET_64BIT && TARGET_SSE_MATH && !TARGET_MIX_SSE_I387"
+  "cvtsi2ss{q}\t{%1, %0|%0, %1}"
+  [(set_attr "type" "sseicvt")
+   (set_attr "mode" "SF")
+   (set_attr "athlon_decode" "vector,double")
+   (set_attr "fp_int_src" "true")])
+
+(define_insn "*floatdisf2_mixed"
   [(set (match_operand:SF 0 "register_operand" "=f#x,?f#x,x#f,x#f")
 	(float:SF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
-  "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE || TARGET_MIX_SSE_I387)"
+  "TARGET_80387 && TARGET_64BIT && TARGET_MIX_SSE_I387"
   "@
    fild%z1\t%1
    #
@@ -4538,22 +4560,13 @@
    (set_attr "athlon_decode" "*,*,vector,double")
    (set_attr "fp_int_src" "true")])
 
-(define_insn "*floatdisf2_sse"
-  [(set (match_operand:SF 0 "register_operand" "=x,x")
-	(float:SF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
-  "TARGET_64BIT && TARGET_SSE"
-  "cvtsi2ss{q}\t{%1, %0|%0, %1}"
-  [(set_attr "type" "sseicvt")
-   (set_attr "mode" "SF")
-   (set_attr "athlon_decode" "vector,double")
-   (set_attr "fp_int_src" "true")])
-
 ; Avoid possible reformatting penalty on the destination by first
 ; zeroing it out
 (define_split
   [(set (match_operand:SF 0 "register_operand" "")
 	(float:SF (match_operand:DI 1 "nonimmediate_operand" "")))]
-  "TARGET_80387 && reload_completed && TARGET_SSE_PARTIAL_REGS
+  "reload_completed
+   && TARGET_80387 && TARGET_SSE_PARTIAL_REGS
    && SSE_REG_P (operands[0])"
   [(const_int 0)]
 {
@@ -4567,9 +4580,9 @@
 (define_expand "floathidf2"
   [(set (match_operand:DF 0 "register_operand" "")
 	(float:DF (match_operand:HI 1 "nonimmediate_operand" "")))]
-  "TARGET_SSE2 || TARGET_80387"
+  "TARGET_80387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
 {
-  if (TARGET_SSE && TARGET_SSE_MATH)
+  if (TARGET_SSE_MATH)
     {
       emit_insn (gen_floatsidf2 (operands[0],
 				 convert_to_mode (SImode, operands[1], 0)));
@@ -4577,10 +4590,10 @@
     }
 })
 
-(define_insn "*floathidf2_1"
+(define_insn "*floathidf2_i387"
   [(set (match_operand:DF 0 "register_operand" "=f,f")
-	(float:DF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
-  "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
+	(float:DF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
+  "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
   "@
    fild%z1\t%1
    #"
@@ -4595,39 +4608,50 @@
   "")
 
 (define_insn "*floatsidf2_i387"
-  [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
-	(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
-  "TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
+  [(set (match_operand:DF 0 "register_operand" "=f,f")
+	(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
+  "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
   "@
    fild%z1\t%1
-   #
-   cvtsi2sd\t{%1, %0|%0, %1}
-   cvtsi2sd\t{%1, %0|%0, %1}"
-  [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
+   #"
+  [(set_attr "type" "fmov,multi")
    (set_attr "mode" "DF")
-   (set_attr "athlon_decode" "*,*,double,direct")
    (set_attr "fp_int_src" "true")])
 
 (define_insn "*floatsidf2_sse"
   [(set (match_operand:DF 0 "register_operand" "=Y,Y")
 	(float:DF (match_operand:SI 1 "nonimmediate_operand" "r,mr")))]
-  "TARGET_SSE2"
+  "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_MIX_SSE_I387"
   "cvtsi2sd\t{%1, %0|%0, %1}"
   [(set_attr "type" "sseicvt")
    (set_attr "mode" "DF")
    (set_attr "athlon_decode" "double,direct")
    (set_attr "fp_int_src" "true")])
 
+(define_insn "*floatsidf2_mixed"
+  [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
+	(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,r,r,mr")))]
+  "TARGET_80387 && TARGET_SSE2 && TARGET_MIX_SSE_I387"
+  "@
+   fild%z1\t%1
+   #
+   cvtsi2sd\t{%1, %0|%0, %1}
+   cvtsi2sd\t{%1, %0|%0, %1}"
+  [(set_attr "type" "fmov,multi,sseicvt,sseicvt")
+   (set_attr "mode" "DF")
+   (set_attr "athlon_decode" "*,*,double,direct")
+   (set_attr "fp_int_src" "true")])
+
 (define_expand "floatdidf2"
   [(set (match_operand:DF 0 "register_operand" "")
 	(float:DF (match_operand:DI 1 "nonimmediate_operand" "")))]
-  "(TARGET_64BIT && TARGET_SSE2) || TARGET_80387"
+  "TARGET_80387 || (TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH)"
   "")
 
-(define_insn "*floatdidf2_i387_only"
-  [(set (match_operand:DF 0 "register_operand" "=f,?f")
-	(float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
-  "TARGET_80387 && (!TARGET_SSE2 || !TARGET_64BIT)"
+(define_insn "*floatdidf2_i387"
+  [(set (match_operand:DF 0 "register_operand" "=f,f")
+	(float:DF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
+  "TARGET_80387 && !(TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH)"
   "@
    fild%z1\t%1
    #"
@@ -4635,10 +4659,20 @@
    (set_attr "mode" "DF")
    (set_attr "fp_int_src" "true")])
 
-(define_insn "*floatdidf2_i387"
+(define_insn "*floatdidf2_sse"
+  [(set (match_operand:DF 0 "register_operand" "=Y,Y")
+	(float:DF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
+  "TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_MIX_SSE_I387"
+  "cvtsi2sd{q}\t{%1, %0|%0, %1}"
+  [(set_attr "type" "sseicvt")
+   (set_attr "mode" "DF")
+   (set_attr "athlon_decode" "double,direct")
+   (set_attr "fp_int_src" "true")])
+
+(define_insn "*floatdidf2_mixed"
   [(set (match_operand:DF 0 "register_operand" "=f#Y,?f#Y,Y#f,Y#f")
 	(float:DF (match_operand:DI 1 "nonimmediate_operand" "m,r,r,mr")))]
-  "TARGET_64BIT && TARGET_80387 && (!TARGET_SSE2 || TARGET_MIX_SSE_I387)"
+  "TARGET_80387 && TARGET_64BIT && TARGET_SSE2 && TARGET_MIX_SSE_I387"
   "@
    fild%z1\t%1
    #
@@ -4649,19 +4683,9 @@
    (set_attr "athlon_decode" "*,*,double,direct")
    (set_attr "fp_int_src" "true")])
 
-(define_insn "*floatdidf2_sse"
-  [(set (match_operand:DF 0 "register_operand" "=Y,Y")
-	(float:DF (match_operand:DI 1 "nonimmediate_operand" "r,mr")))]
-  "TARGET_SSE2"
-  "cvtsi2sd{q}\t{%1, %0|%0, %1}"
-  [(set_attr "type" "sseicvt")
-   (set_attr "mode" "DF")
-   (set_attr "athlon_decode" "double,direct")
-   (set_attr "fp_int_src" "true")])
-
 (define_insn "floathixf2"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
-	(float:XF (match_operand:HI 1 "nonimmediate_operand" "m,r")))]
+	(float:XF (match_operand:HI 1 "nonimmediate_operand" "m,?r")))]
   "TARGET_80387"
   "@
    fild%z1\t%1
@@ -4672,7 +4696,7 @@
 
 (define_insn "floatsixf2"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
-	(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,r")))]
+	(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r")))]
   "TARGET_80387"
   "@
    fild%z1\t%1
@@ -4683,7 +4707,7 @@
 
 (define_insn "floatdixf2"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
-	(float:XF (match_operand:DI 1 "nonimmediate_operand" "m,r")))]
+	(float:XF (match_operand:DI 1 "nonimmediate_operand" "m,?r")))]
   "TARGET_80387"
   "@
    fild%z1\t%1
@@ -4709,19 +4733,19 @@
 (define_expand "floatunssisf2"
   [(use (match_operand:SF 0 "register_operand" ""))
    (use (match_operand:SI 1 "register_operand" ""))]
-  "TARGET_SSE && TARGET_SSE_MATH && !TARGET_64BIT"
+  "!TARGET_64BIT && TARGET_SSE_MATH"
   "x86_emit_floatuns (operands); DONE;")
 
 (define_expand "floatunsdisf2"
   [(use (match_operand:SF 0 "register_operand" ""))
    (use (match_operand:DI 1 "register_operand" ""))]
-  "TARGET_SSE && TARGET_SSE_MATH && TARGET_64BIT"
+  "TARGET_64BIT && TARGET_SSE_MATH"
   "x86_emit_floatuns (operands); DONE;")
 
 (define_expand "floatunsdidf2"
   [(use (match_operand:DF 0 "register_operand" ""))
    (use (match_operand:DI 1 "register_operand" ""))]
-  "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_64BIT"
+  "TARGET_64BIT && TARGET_SSE2 && TARGET_SSE_MATH"
   "x86_emit_floatuns (operands); DONE;")
 
 ;; SSE extract/set expanders
@@ -14342,7 +14366,7 @@
 
 ;; Gcc is slightly more smart about handling normal two address instructions
 ;; so use special patterns for add and mull.
-(define_insn "*fop_sf_comm_nosse"
+(define_insn "*fop_sf_comm_i387"
   [(set (match_operand:SF 0 "register_operand" "=f")
 	(match_operator:SF 3 "binary_fp_operator"
 			[(match_operand:SF 1 "nonimmediate_operand" "%0")
@@ -14357,12 +14381,27 @@
 	   (const_string "fop")))
    (set_attr "mode" "SF")])
 
-(define_insn "*fop_sf_comm"
+(define_insn "*fop_sf_comm_sse"
+  [(set (match_operand:SF 0 "register_operand" "=x")
+	(match_operator:SF 3 "binary_fp_operator"
+			[(match_operand:SF 1 "nonimmediate_operand" "%0")
+			 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
+  "TARGET_SSE_MATH && !TARGET_MIX_SSE_I387
+   && COMMUTATIVE_ARITH_P (operands[3])
+   && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
+  "* return output_387_binary_op (insn, operands);"
+  [(set (attr "type") 
+        (if_then_else (match_operand:SF 3 "mult_operator" "") 
+	   (const_string "ssemul")
+	   (const_string "sseadd")))
+   (set_attr "mode" "SF")])
+
+(define_insn "*fop_sf_comm_mixed"
   [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
 	(match_operator:SF 3 "binary_fp_operator"
 			[(match_operand:SF 1 "nonimmediate_operand" "%0,0")
 			 (match_operand:SF 2 "nonimmediate_operand" "fm#x,xm#f")]))]
-  "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
+  "TARGET_80387 && TARGET_MIX_SSE_I387
    && COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
@@ -14376,26 +14415,12 @@
 	      (const_string "fop"))))
    (set_attr "mode" "SF")])
 
-(define_insn "*fop_sf_comm_sse"
-  [(set (match_operand:SF 0 "register_operand" "=x")
-	(match_operator:SF 3 "binary_fp_operator"
-			[(match_operand:SF 1 "nonimmediate_operand" "%0")
-			 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
-  "TARGET_SSE_MATH && COMMUTATIVE_ARITH_P (operands[3])
-   && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
-  "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (if_then_else (match_operand:SF 3 "mult_operator" "") 
-	   (const_string "ssemul")
-	   (const_string "sseadd")))
-   (set_attr "mode" "SF")])
-
-(define_insn "*fop_df_comm_nosse"
+(define_insn "*fop_df_comm_i387"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(match_operator:DF 3 "binary_fp_operator"
 			[(match_operand:DF 1 "nonimmediate_operand" "%0")
 			 (match_operand:DF 2 "nonimmediate_operand" "fm")]))]
-  "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
+   "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)
    && COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
@@ -14405,12 +14430,27 @@
 	   (const_string "fop")))
    (set_attr "mode" "DF")])
 
-(define_insn "*fop_df_comm"
+(define_insn "*fop_df_comm_sse"
+  [(set (match_operand:DF 0 "register_operand" "=Y")
+	(match_operator:DF 3 "binary_fp_operator"
+			[(match_operand:DF 1 "nonimmediate_operand" "%0")
+			 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
+  "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_MIX_SSE_I387
+   && COMMUTATIVE_ARITH_P (operands[3])
+   && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
+  "* return output_387_binary_op (insn, operands);"
+  [(set (attr "type") 
+        (if_then_else (match_operand:SF 3 "mult_operator" "") 
+	   (const_string "ssemul")
+	   (const_string "sseadd")))
+   (set_attr "mode" "DF")])
+
+(define_insn "*fop_df_comm_mixed"
   [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
 	(match_operator:DF 3 "binary_fp_operator"
 			[(match_operand:DF 1 "nonimmediate_operand" "%0,0")
 			 (match_operand:DF 2 "nonimmediate_operand" "fm#Y,Ym#f")]))]
-  "TARGET_80387 && TARGET_SSE_MATH && TARGET_SSE2 && TARGET_MIX_SSE_I387
+  "TARGET_80387 && TARGET_SSE2 && TARGET_MIX_SSE_I387
    && COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
@@ -14424,21 +14464,6 @@
 	      (const_string "fop"))))
    (set_attr "mode" "DF")])
 
-(define_insn "*fop_df_comm_sse"
-  [(set (match_operand:DF 0 "register_operand" "=Y")
-	(match_operator:DF 3 "binary_fp_operator"
-			[(match_operand:DF 1 "nonimmediate_operand" "%0")
-			 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
-  "TARGET_SSE2 && TARGET_SSE_MATH
-   && COMMUTATIVE_ARITH_P (operands[3])
-   && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
-  "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (if_then_else (match_operand:SF 3 "mult_operator" "") 
-	   (const_string "ssemul")
-	   (const_string "sseadd")))
-   (set_attr "mode" "DF")])
-
 (define_insn "*fop_xf_comm"
   [(set (match_operand:XF 0 "register_operand" "=f")
 	(match_operator:XF 3 "binary_fp_operator"
@@ -14453,7 +14478,7 @@
            (const_string "fop")))
    (set_attr "mode" "XF")])
 
-(define_insn "*fop_sf_1_nosse"
+(define_insn "*fop_sf_1_i387"
   [(set (match_operand:SF 0 "register_operand" "=f,f")
 	(match_operator:SF 3 "binary_fp_operator"
 			[(match_operand:SF 1 "nonimmediate_operand" "0,fm")
@@ -14471,12 +14496,29 @@
               (const_string "fop")))
    (set_attr "mode" "SF")])
 
-(define_insn "*fop_sf_1"
+(define_insn "*fop_sf_1_sse"
+  [(set (match_operand:SF 0 "register_operand" "=x")
+	(match_operator:SF 3 "binary_fp_operator"
+			[(match_operand:SF 1 "register_operand" "0")
+			 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
+  "TARGET_SSE_MATH && !TARGET_MIX_SSE_I387
+   && !COMMUTATIVE_ARITH_P (operands[3])"
+  "* return output_387_binary_op (insn, operands);"
+  [(set (attr "type") 
+        (cond [(match_operand:SF 3 "mult_operator" "")
+                 (const_string "ssemul")
+	       (match_operand:SF 3 "div_operator" "")
+                 (const_string "ssediv")
+              ]
+              (const_string "sseadd")))
+   (set_attr "mode" "SF")])
+
+(define_insn "*fop_sf_1_mixed"
   [(set (match_operand:SF 0 "register_operand" "=f,f,x")
 	(match_operator:SF 3 "binary_fp_operator"
 			[(match_operand:SF 1 "nonimmediate_operand" "0,fm,0")
 			 (match_operand:SF 2 "nonimmediate_operand" "fm,0,xm#f")]))]
-  "TARGET_80387 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
+  "TARGET_80387 && TARGET_MIX_SSE_I387
    && !COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
@@ -14497,30 +14539,13 @@
               (const_string "fop")))
    (set_attr "mode" "SF")])
 
-(define_insn "*fop_sf_1_sse"
-  [(set (match_operand:SF 0 "register_operand" "=x")
-	(match_operator:SF 3 "binary_fp_operator"
-			[(match_operand:SF 1 "register_operand" "0")
-			 (match_operand:SF 2 "nonimmediate_operand" "xm")]))]
-  "TARGET_SSE_MATH
-   && !COMMUTATIVE_ARITH_P (operands[3])"
-  "* return output_387_binary_op (insn, operands);"
-  [(set (attr "type") 
-        (cond [(match_operand:SF 3 "mult_operator" "")
-                 (const_string "ssemul")
-	       (match_operand:SF 3 "div_operator" "")
-                 (const_string "ssediv")
-              ]
-              (const_string "sseadd")))
-   (set_attr "mode" "SF")])
-
 ;; ??? Add SSE splitters for these!
-(define_insn "*fop_sf_2"
+(define_insn "*fop_sf_2_i387"
   [(set (match_operand:SF 0 "register_operand" "=f,f")
 	(match_operator:SF 3 "binary_fp_operator"
 	  [(float:SF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
 	   (match_operand:SF 2 "register_operand" "0,0")]))]
-  "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
+  "TARGET_80387 && !TARGET_SSE_MATH && TARGET_USE_FIOP"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
   [(set (attr "type") 
         (cond [(match_operand:SF 3 "mult_operator" "") 
@@ -14532,12 +14557,12 @@
    (set_attr "fp_int_src" "true")
    (set_attr "mode" "SI")])
 
-(define_insn "*fop_sf_3"
+(define_insn "*fop_sf_3_i387"
   [(set (match_operand:SF 0 "register_operand" "=f,f")
 	(match_operator:SF 3 "binary_fp_operator"
 	  [(match_operand:SF 1 "register_operand" "0,0")
 	   (float:SF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
-  "TARGET_80387 && TARGET_USE_FIOP && !TARGET_SSE_MATH"
+  "TARGET_80387 && !TARGET_SSE_MATH && TARGET_USE_FIOP"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
   [(set (attr "type") 
         (cond [(match_operand:SF 3 "mult_operator" "") 
@@ -14549,12 +14574,12 @@
    (set_attr "fp_int_src" "true")
    (set_attr "mode" "SI")])
 
-(define_insn "*fop_df_1_nosse"
+(define_insn "*fop_df_1_i387"
   [(set (match_operand:DF 0 "register_operand" "=f,f")
 	(match_operator:DF 3 "binary_fp_operator"
 			[(match_operand:DF 1 "nonimmediate_operand" "0,fm")
 			 (match_operand:DF 2 "nonimmediate_operand" "fm,0")]))]
-  "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
+  "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)
    && !COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
@@ -14567,13 +14592,29 @@
               (const_string "fop")))
    (set_attr "mode" "DF")])
 
+(define_insn "*fop_df_1_sse"
+  [(set (match_operand:DF 0 "register_operand" "=Y")
+	(match_operator:DF 3 "binary_fp_operator"
+			[(match_operand:DF 1 "register_operand" "0")
+			 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
+  "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_MIX_SSE_I387
+   && !COMMUTATIVE_ARITH_P (operands[3])"
+  "* return output_387_binary_op (insn, operands);"
+  [(set_attr "mode" "DF")
+   (set (attr "type") 
+        (cond [(match_operand:SF 3 "mult_operator" "")
+                 (const_string "ssemul")
+	       (match_operand:SF 3 "div_operator" "")
+                 (const_string "ssediv")
+              ]
+              (const_string "sseadd")))])
 
-(define_insn "*fop_df_1"
+(define_insn "*fop_df_1_mixed"
   [(set (match_operand:DF 0 "register_operand" "=f#Y,f#Y,Y#f")
 	(match_operator:DF 3 "binary_fp_operator"
 			[(match_operand:DF 1 "nonimmediate_operand" "0,fm,0")
 			 (match_operand:DF 2 "nonimmediate_operand" "fm,0,Ym#f")]))]
-  "TARGET_80387 && TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387
+  "TARGET_80387 && TARGET_SSE2 && TARGET_MIX_SSE_I387
    && !COMMUTATIVE_ARITH_P (operands[3])
    && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
   "* return output_387_binary_op (insn, operands);"
@@ -14594,30 +14635,13 @@
               (const_string "fop")))
    (set_attr "mode" "DF")])
 
-(define_insn "*fop_df_1_sse"
-  [(set (match_operand:DF 0 "register_operand" "=Y")
-	(match_operator:DF 3 "binary_fp_operator"
-			[(match_operand:DF 1 "register_operand" "0")
-			 (match_operand:DF 2 "nonimmediate_operand" "Ym")]))]
-  "TARGET_SSE2 && TARGET_SSE_MATH
-   && !COMMUTATIVE_ARITH_P (operands[3])"
-  "* return output_387_binary_op (insn, operands);"
-  [(set_attr "mode" "DF")
-   (set (attr "type") 
-        (cond [(match_operand:SF 3 "mult_operator" "")
-                 (const_string "ssemul")
-	       (match_operand:SF 3 "div_operator" "")
-                 (const_string "ssediv")
-              ]
-              (const_string "sseadd")))])
-
 ;; ??? Add SSE splitters for these!
-(define_insn "*fop_df_2"
+(define_insn "*fop_df_2_i387"
   [(set (match_operand:DF 0 "register_operand" "=f,f")
 	(match_operator:DF 3 "binary_fp_operator"
 	   [(float:DF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
 	    (match_operand:DF 2 "register_operand" "0,0")]))]
-  "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
+  "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH) && TARGET_USE_FIOP"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
   [(set (attr "type") 
         (cond [(match_operand:DF 3 "mult_operator" "") 
@@ -14629,12 +14653,12 @@
    (set_attr "fp_int_src" "true")
    (set_attr "mode" "SI")])
 
-(define_insn "*fop_df_3"
+(define_insn "*fop_df_3_i387"
   [(set (match_operand:DF 0 "register_operand" "=f,f")
 	(match_operator:DF 3 "binary_fp_operator"
 	   [(match_operand:DF 1 "register_operand" "0,0")
 	    (float:DF (match_operand:SI 2 "nonimmediate_operand" "m,?r"))]))]
-  "TARGET_80387 && TARGET_USE_FIOP && !(TARGET_SSE2 && TARGET_SSE_MATH)"
+  "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH) && TARGET_USE_FIOP"
   "* return which_alternative ? \"#\" : output_387_binary_op (insn, operands);"
   [(set (attr "type") 
         (cond [(match_operand:DF 3 "mult_operator" "") 
@@ -14646,13 +14670,12 @@
    (set_attr "fp_int_src" "true")
    (set_attr "mode" "SI")])
 
-(define_insn "*fop_df_4"
+(define_insn "*fop_df_4_i387"
   [(set (match_operand:DF 0 "register_operand" "=f,f")
 	(match_operator:DF 3 "binary_fp_operator"
 	   [(float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "fm,0"))
 	    (match_operand:DF 2 "register_operand" "0,f")]))]
-  "TARGET_80387 && (!TARGET_SSE2 || !TARGET_SSE_MATH)
-   && (GET_CODE (operands[1]) != MEM || GET_CODE (operands[2]) != MEM)"
+  "TARGET_80387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
   "* return output_387_binary_op (insn, operands);"
   [(set (attr "type") 
         (cond [(match_operand:DF 3 "mult_operator" "") 
@@ -14663,7 +14686,7 @@
               (const_string "fop")))
    (set_attr "mode" "SF")])
 
-(define_insn "*fop_df_5"
+(define_insn "*fop_df_5_i387"
   [(set (match_operand:DF 0 "register_operand" "=f,f")
 	(match_operator:DF 3 "binary_fp_operator"
 	  [(match_operand:DF 1 "register_operand" "0,f")
@@ -14680,7 +14703,7 @@
               (const_string "fop")))
    (set_attr "mode" "SF")])
 
-(define_insn "*fop_df_6"
+(define_insn "*fop_df_6_i387"
   [(set (match_operand:DF 0 "register_operand" "=f,f")
 	(match_operator:DF 3 "binary_fp_operator"
 	  [(float_extend:DF
@@ -14698,7 +14721,7 @@
               (const_string "fop")))
    (set_attr "mode" "SF")])
 
-(define_insn "*fop_xf_1"
+(define_insn "*fop_xf_1_i387"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
 	(match_operator:XF 3 "binary_fp_operator"
 			[(match_operand:XF 1 "register_operand" "0,f")
@@ -14715,7 +14738,7 @@
               (const_string "fop")))
    (set_attr "mode" "XF")])
 
-(define_insn "*fop_xf_2"
+(define_insn "*fop_xf_2_i387"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
 	(match_operator:XF 3 "binary_fp_operator"
 	   [(float:XF (match_operand:SI 1 "nonimmediate_operand" "m,?r"))
@@ -14732,7 +14755,7 @@
    (set_attr "fp_int_src" "true")
    (set_attr "mode" "SI")])
 
-(define_insn "*fop_xf_3"
+(define_insn "*fop_xf_3_i387"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
 	(match_operator:XF 3 "binary_fp_operator"
 	  [(match_operand:XF 1 "register_operand" "0,0")
@@ -14749,7 +14772,7 @@
    (set_attr "fp_int_src" "true")
    (set_attr "mode" "SI")])
 
-(define_insn "*fop_xf_4"
+(define_insn "*fop_xf_4_i387"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
 	(match_operator:XF 3 "binary_fp_operator"
 	   [(float_extend:XF (match_operand 1 "nonimmediate_operand" "fm,0"))
@@ -14765,7 +14788,7 @@
               (const_string "fop")))
    (set_attr "mode" "SF")])
 
-(define_insn "*fop_xf_5"
+(define_insn "*fop_xf_5_i387"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
 	(match_operator:XF 3 "binary_fp_operator"
 	  [(match_operand:XF 1 "register_operand" "0,f")
@@ -14782,7 +14805,7 @@
               (const_string "fop")))
    (set_attr "mode" "SF")])
 
-(define_insn "*fop_xf_6"
+(define_insn "*fop_xf_6_i387"
   [(set (match_operand:XF 0 "register_operand" "=f,f")
 	(match_operator:XF 3 "binary_fp_operator"
 	  [(float_extend:XF
@@ -14851,84 +14874,78 @@
     operands[1] = force_reg (SFmode, operands[1]);
 })
 
-(define_insn "sqrtsf2_1"
-  [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
-	(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
-  "TARGET_USE_FANCY_MATH_387
-   && (TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
-  "@
-   fsqrt
-   sqrtss\t{%1, %0|%0, %1}"
-  [(set_attr "type" "fpspc,sse")
-   (set_attr "mode" "SF,SF")
-   (set_attr "athlon_decode" "direct,*")])
+(define_insn "*sqrtsf2_i387"
+  [(set (match_operand:SF 0 "register_operand" "=f")
+	(sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
+  "TARGET_USE_FANCY_MATH_387 && !TARGET_SSE_MATH"
+  "fsqrt"
+  [(set_attr "type" "fpspc")
+   (set_attr "mode" "SF")
+   (set_attr "athlon_decode" "direct")])
 
-(define_insn "sqrtsf2_1_sse_only"
+(define_insn "*sqrtsf2_sse"
   [(set (match_operand:SF 0 "register_operand" "=x")
 	(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "xm")))]
-  "TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
+  "TARGET_SSE_MATH && !TARGET_MIX_SSE_I387"
   "sqrtss\t{%1, %0|%0, %1}"
   [(set_attr "type" "sse")
    (set_attr "mode" "SF")
    (set_attr "athlon_decode" "*")])
 
-(define_insn "sqrtsf2_i387"
-  [(set (match_operand:SF 0 "register_operand" "=f")
-	(sqrt:SF (match_operand:SF 1 "register_operand" "0")))]
-  "TARGET_USE_FANCY_MATH_387
-   && !TARGET_SSE_MATH"
-  "fsqrt"
-  [(set_attr "type" "fpspc")
-   (set_attr "mode" "SF")
-   (set_attr "athlon_decode" "direct")])
+(define_insn "*sqrtsf2_mixed"
+  [(set (match_operand:SF 0 "register_operand" "=f#x,x#f")
+	(sqrt:SF (match_operand:SF 1 "nonimmediate_operand" "0#x,xm#f")))]
+  "TARGET_USE_FANCY_MATH_387 && TARGET_MIX_SSE_I387"
+  "@
+   fsqrt
+   sqrtss\t{%1, %0|%0, %1}"
+  [(set_attr "type" "fpspc,sse")
+   (set_attr "mode" "SF,SF")
+   (set_attr "athlon_decode" "direct,*")])
 
 (define_expand "sqrtdf2"
   [(set (match_operand:DF 0 "register_operand" "")
 	(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "")))]
-  "TARGET_USE_FANCY_MATH_387
-   || (TARGET_SSE2 && TARGET_SSE_MATH)"
+  "TARGET_USE_FANCY_MATH_387 || (TARGET_SSE2 && TARGET_SSE_MATH)"
 {
-  if (!TARGET_SSE2 || !TARGET_SSE_MATH)
+  if (!(TARGET_SSE2 && TARGET_SSE_MATH))
     operands[1] = force_reg (DFmode, operands[1]);
 })
 
-(define_insn "sqrtdf2_1"
-  [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
-	(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
-  "TARGET_USE_FANCY_MATH_387
-   && (TARGET_SSE2 && TARGET_SSE_MATH && TARGET_MIX_SSE_I387)"
-  "@
-   fsqrt
-   sqrtsd\t{%1, %0|%0, %1}"
-  [(set_attr "type" "fpspc,sse")
-   (set_attr "mode" "DF,DF")
-   (set_attr "athlon_decode" "direct,*")])
+(define_insn "*sqrtdf2_i387"
+  [(set (match_operand:DF 0 "register_operand" "=f")
+	(sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
+  "TARGET_USE_FANCY_MATH_387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
+  "fsqrt"
+  [(set_attr "type" "fpspc")
+   (set_attr "mode" "DF")
+   (set_attr "athlon_decode" "direct")])
 
-(define_insn "sqrtdf2_1_sse_only"
+(define_insn "*sqrtdf2_sse"
   [(set (match_operand:DF 0 "register_operand" "=Y")
 	(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "Ym")))]
-  "TARGET_SSE2 && TARGET_SSE_MATH && (!TARGET_80387 || !TARGET_MIX_SSE_I387)"
+  "TARGET_SSE2 && TARGET_SSE_MATH && !TARGET_MIX_SSE_I387"
   "sqrtsd\t{%1, %0|%0, %1}"
   [(set_attr "type" "sse")
    (set_attr "mode" "DF")
    (set_attr "athlon_decode" "*")])
 
-(define_insn "sqrtdf2_i387"
-  [(set (match_operand:DF 0 "register_operand" "=f")
-	(sqrt:DF (match_operand:DF 1 "register_operand" "0")))]
-  "TARGET_USE_FANCY_MATH_387
-   && (!TARGET_SSE2 || !TARGET_SSE_MATH)"
-  "fsqrt"
-  [(set_attr "type" "fpspc")
-   (set_attr "mode" "DF")
-   (set_attr "athlon_decode" "direct")])
+(define_insn "*sqrtdf2_mixed"
+  [(set (match_operand:DF 0 "register_operand" "=f#Y,Y#f")
+	(sqrt:DF (match_operand:DF 1 "nonimmediate_operand" "0#Y,Ym#f")))]
+  "TARGET_80387 && TARGET_SSE2 && TARGET_MIX_SSE_I387"
+  "@
+   fsqrt
+   sqrtsd\t{%1, %0|%0, %1}"
+  [(set_attr "type" "fpspc,sse")
+   (set_attr "mode" "DF,DF")
+   (set_attr "athlon_decode" "direct,*")])
 
 (define_insn "*sqrtextendsfdf2"
   [(set (match_operand:DF 0 "register_operand" "=f")
 	(sqrt:DF (float_extend:DF
 		  (match_operand:SF 1 "register_operand" "0"))))]
-  "TARGET_USE_FANCY_MATH_387
-   && !(TARGET_SSE2 && TARGET_SSE_MATH)"
+  "TARGET_USE_FANCY_MATH_387 && !(TARGET_SSE2 && TARGET_SSE_MATH)"
   "fsqrt"
   [(set_attr "type" "fpspc")
    (set_attr "mode" "DF")
@@ -17982,7 +17999,7 @@
 			 (match_dup 1)
 			 (match_dup 2)))
    (clobber (reg:CC FLAGS_REG))]
-  "TARGET_SSE2 && TARGET_IEEE_FP && TARGET_SSE_MATH"
+  "TARGET_SSE2 && TARGET_SSE_MATH && TARGET_IEEE_FP "
   "#")
 
 (define_insn "*mindf_nonieee"

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