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Rationalize altivec.md 1/n
- From: Nathan Sidwell <nathan at codesourcery dot com>
- To: GCC Patches <gcc-patches at gcc dot gnu dot org>, David Edelsohn <dje at watson dot ibm dot com>
- Date: Thu, 18 Nov 2004 11:56:46 +0000
- Subject: Rationalize altivec.md 1/n
- Organization: Codesourcery LLC
This patch is the first in a series to use mode macros in the altivec
md file. This will cut down its size considerably, and make sure we cover
all the mode variants -- for instance right now, there's only a v4si vandc
pattern.
booted & tested on powerpc-linux-gnu, ok?
nathan
--
Nathan Sidwell :: http://www.codesourcery.com :: CodeSourcery LLC
nathan@codesourcery.com :: http://www.planetfall.pwp.blueyonder.co.uk
2004-11-18 Nathan Sidwell <nathan@codesourcery.com>
* config/rs6000/altivec.md (VI, VF, V): New mode macros.
(altivec_lvx_4si, altivec_lvx_8hi, altivec_lvx_16qi,
altivec_lvx_4sf): Rename and replace with ...
(altivec_lvx_<mode>): ... mode macro version.
(altivec_stvx_4si, altivec_stvx_8hi, altivec_stvx_16qi,
altivec_stvx_4sf): Rename and replace with ...
(altivec_stvx_<mode>): ... mode macro version.
(movv4si, movv8hi, movv16qi, movv4sf}): Replace with ...
(mov<mode>): ... mode macro version.
(*movv4si_internal, *movv8hi_internal1, *movv16qi_internal1,
*movv4sf_internal1): Replace with ...
(*mov<mode>_internal): ... mode macro version.
(get_vrsave_internal, *set_vrsave_internal, *save_world,
*restore_world): Unquote output statements.
* config/rs6000/rs6000.c (altivec_expand_ld_builtin,
altivec_expand_st_builtin): Adjust insn names.
Index: config/rs6000/rs6000.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.743
diff -c -3 -p -r1.743 rs6000.c
*** config/rs6000/rs6000.c 17 Nov 2004 02:19:17 -0000 1.743
--- config/rs6000/rs6000.c 18 Nov 2004 11:47:28 -0000
*************** altivec_expand_ld_builtin (tree exp, rtx
*** 6889,6904 ****
switch (fcode)
{
case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
! icode = CODE_FOR_altivec_lvx_16qi;
break;
case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
! icode = CODE_FOR_altivec_lvx_8hi;
break;
case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
! icode = CODE_FOR_altivec_lvx_4si;
break;
case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
! icode = CODE_FOR_altivec_lvx_4sf;
break;
default:
*expandedp = false;
--- 6889,6904 ----
switch (fcode)
{
case ALTIVEC_BUILTIN_LD_INTERNAL_16qi:
! icode = CODE_FOR_altivec_lvx_v16qi;
break;
case ALTIVEC_BUILTIN_LD_INTERNAL_8hi:
! icode = CODE_FOR_altivec_lvx_v8hi;
break;
case ALTIVEC_BUILTIN_LD_INTERNAL_4si:
! icode = CODE_FOR_altivec_lvx_v4si;
break;
case ALTIVEC_BUILTIN_LD_INTERNAL_4sf:
! icode = CODE_FOR_altivec_lvx_v4sf;
break;
default:
*expandedp = false;
*************** altivec_expand_st_builtin (tree exp, rtx
*** 6943,6958 ****
switch (fcode)
{
case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
! icode = CODE_FOR_altivec_stvx_16qi;
break;
case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
! icode = CODE_FOR_altivec_stvx_8hi;
break;
case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
! icode = CODE_FOR_altivec_stvx_4si;
break;
case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
! icode = CODE_FOR_altivec_stvx_4sf;
break;
default:
*expandedp = false;
--- 6943,6958 ----
switch (fcode)
{
case ALTIVEC_BUILTIN_ST_INTERNAL_16qi:
! icode = CODE_FOR_altivec_stvx_v16qi;
break;
case ALTIVEC_BUILTIN_ST_INTERNAL_8hi:
! icode = CODE_FOR_altivec_stvx_v8hi;
break;
case ALTIVEC_BUILTIN_ST_INTERNAL_4si:
! icode = CODE_FOR_altivec_stvx_v4si;
break;
case ALTIVEC_BUILTIN_ST_INTERNAL_4sf:
! icode = CODE_FOR_altivec_stvx_v4sf;
break;
default:
*expandedp = false;
Index: config/rs6000/altivec.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/altivec.md,v
retrieving revision 1.26
diff -c -3 -p -r1.26 altivec.md
*** config/rs6000/altivec.md 16 Nov 2004 18:52:36 -0000 1.26
--- config/rs6000/altivec.md 18 Nov 2004 11:47:33 -0000
***************
*** 46,136 ****
(UNSPEC_VCONDU_V16QI 307)
])
! ;; Generic LVX load instruction.
! (define_insn "altivec_lvx_4si"
! [(set (match_operand:V4SI 0 "altivec_register_operand" "=v")
! (match_operand:V4SI 1 "memory_operand" "m"))]
! "TARGET_ALTIVEC"
! "lvx %0,%y1"
! [(set_attr "type" "vecload")])
!
! (define_insn "altivec_lvx_8hi"
! [(set (match_operand:V8HI 0 "altivec_register_operand" "=v")
! (match_operand:V8HI 1 "memory_operand" "m"))]
! "TARGET_ALTIVEC"
! "lvx %0,%y1"
! [(set_attr "type" "vecload")])
! (define_insn "altivec_lvx_16qi"
! [(set (match_operand:V16QI 0 "altivec_register_operand" "=v")
! (match_operand:V16QI 1 "memory_operand" "m"))]
! "TARGET_ALTIVEC"
! "lvx %0,%y1"
! [(set_attr "type" "vecload")])
!
! (define_insn "altivec_lvx_4sf"
! [(set (match_operand:V4SF 0 "altivec_register_operand" "=v")
! (match_operand:V4SF 1 "memory_operand" "m"))]
"TARGET_ALTIVEC"
"lvx %0,%y1"
[(set_attr "type" "vecload")])
;; Generic STVX store instruction.
! (define_insn "altivec_stvx_4si"
! [(set (match_operand:V4SI 0 "memory_operand" "=m")
! (match_operand:V4SI 1 "altivec_register_operand" "v"))]
! "TARGET_ALTIVEC"
! "stvx %1,%y0"
! [(set_attr "type" "vecstore")])
!
! (define_insn "altivec_stvx_8hi"
! [(set (match_operand:V8HI 0 "memory_operand" "=m")
! (match_operand:V8HI 1 "altivec_register_operand" "v"))]
! "TARGET_ALTIVEC"
! "stvx %1,%y0"
! [(set_attr "type" "vecstore")])
!
! (define_insn "altivec_stvx_16qi"
! [(set (match_operand:V16QI 0 "memory_operand" "=m")
! (match_operand:V16QI 1 "altivec_register_operand" "v"))]
! "TARGET_ALTIVEC"
! "stvx %1,%y0"
! [(set_attr "type" "vecstore")])
!
! (define_insn "altivec_stvx_4sf"
! [(set (match_operand:V4SF 0 "memory_operand" "=m")
! (match_operand:V4SF 1 "altivec_register_operand" "v"))]
"TARGET_ALTIVEC"
"stvx %1,%y0"
[(set_attr "type" "vecstore")])
;; Vector move instructions.
! (define_expand "movv4si"
! [(set (match_operand:V4SI 0 "nonimmediate_operand" "")
! (match_operand:V4SI 1 "any_operand" ""))]
"TARGET_ALTIVEC"
! "{ rs6000_emit_move (operands[0], operands[1], V4SImode); DONE; }")
! (define_insn "*movv4si_internal"
! [(set (match_operand:V4SI 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
! (match_operand:V4SI 1 "input_operand" "v,m,v,r,o,r,W"))]
"TARGET_ALTIVEC
! && (register_operand (operands[0], V4SImode)
! || register_operand (operands[1], V4SImode))"
! "*
{
switch (which_alternative)
{
! case 0: return \"stvx %1,%y0\";
! case 1: return \"lvx %0,%y1\";
! case 2: return \"vor %0,%1,%1\";
! case 3: return \"#\";
! case 4: return \"#\";
! case 5: return \"#\";
case 6: return output_vec_const_move (operands);
default: abort();
}
! }"
[(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
(define_split
--- 46,103 ----
(UNSPEC_VCONDU_V16QI 307)
])
! ;; Vec int modes
! (define_mode_macro VI [V4SI V8HI V16QI])
! ;; Vec float modes
! (define_mode_macro VF [V4SF])
! ;; Vec modes, pity mode macros are not composable
! (define_mode_macro V [V4SI V8HI V16QI V4SF])
! ;; Generic LVX load instruction.
! (define_insn "altivec_lvx_<mode>"
! [(set (match_operand:V 0 "altivec_register_operand" "=v")
! (match_operand:V 1 "memory_operand" "m"))]
"TARGET_ALTIVEC"
"lvx %0,%y1"
[(set_attr "type" "vecload")])
;; Generic STVX store instruction.
! (define_insn "altivec_stvx_<mode>"
! [(set (match_operand:V 0 "memory_operand" "=m")
! (match_operand:V 1 "altivec_register_operand" "v"))]
"TARGET_ALTIVEC"
"stvx %1,%y0"
[(set_attr "type" "vecstore")])
;; Vector move instructions.
! (define_expand "mov<mode>"
! [(set (match_operand:V 0 "nonimmediate_operand" "")
! (match_operand:V 1 "any_operand" ""))]
"TARGET_ALTIVEC"
! {
! rs6000_emit_move (operands[0], operands[1], <MODE>mode);
! DONE;
! })
! (define_insn "*mov<mode>_internal"
! [(set (match_operand:V 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
! (match_operand:V 1 "input_operand" "v,m,v,r,o,r,W"))]
"TARGET_ALTIVEC
! && (register_operand (operands[0], <MODE>mode)
! || register_operand (operands[1], <MODE>mode))"
{
switch (which_alternative)
{
! case 0: return "stvx %1,%y0";
! case 1: return "lvx %0,%y1";
! case 2: return "vor %0,%1,%1";
! case 3: return "#";
! case 4: return "#";
! case 5: return "#";
case 6: return output_vec_const_move (operands);
default: abort();
}
! }
[(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
(define_split
***************
*** 139,145 ****
"TARGET_ALTIVEC && reload_completed
&& gpr_or_gpr_p (operands[0], operands[1])"
[(pc)]
! { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
(define_split
[(set (match_operand:V4SI 0 "altivec_register_operand" "")
--- 106,114 ----
"TARGET_ALTIVEC && reload_completed
&& gpr_or_gpr_p (operands[0], operands[1])"
[(pc)]
! {
! rs6000_split_multireg_move (operands[0], operands[1]); DONE;
! })
(define_split
[(set (match_operand:V4SI 0 "altivec_register_operand" "")
***************
*** 149,186 ****
(set (match_dup 0)
(plus:V4SI (match_dup 0)
(match_dup 0)))]
- "
{
operands[3] = gen_easy_vector_constant_add_self (operands[1]);
! }")
!
! (define_expand "movv8hi"
! [(set (match_operand:V8HI 0 "nonimmediate_operand" "")
! (match_operand:V8HI 1 "any_operand" ""))]
! "TARGET_ALTIVEC"
! "{ rs6000_emit_move (operands[0], operands[1], V8HImode); DONE; }")
!
! (define_insn "*movv8hi_internal1"
! [(set (match_operand:V8HI 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
! (match_operand:V8HI 1 "input_operand" "v,m,v,r,o,r,W"))]
! "TARGET_ALTIVEC
! && (register_operand (operands[0], V8HImode)
! || register_operand (operands[1], V8HImode))"
! "*
! {
! switch (which_alternative)
! {
! case 0: return \"stvx %1,%y0\";
! case 1: return \"lvx %0,%y1\";
! case 2: return \"vor %0,%1,%1\";
! case 3: return \"#\";
! case 4: return \"#\";
! case 5: return \"#\";
! case 6: return output_vec_const_move (operands);
! default: abort ();
! }
! }"
! [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
(define_split
[(set (match_operand:V8HI 0 "nonimmediate_operand" "")
--- 118,126 ----
(set (match_dup 0)
(plus:V4SI (match_dup 0)
(match_dup 0)))]
{
operands[3] = gen_easy_vector_constant_add_self (operands[1]);
! })
(define_split
[(set (match_operand:V8HI 0 "nonimmediate_operand" "")
***************
*** 198,235 ****
(set (match_dup 0)
(plus:V8HI (match_dup 0)
(match_dup 0)))]
- "
{
operands[3] = gen_easy_vector_constant_add_self (operands[1]);
! }")
!
! (define_expand "movv16qi"
! [(set (match_operand:V16QI 0 "nonimmediate_operand" "")
! (match_operand:V16QI 1 "any_operand" ""))]
! "TARGET_ALTIVEC"
! "{ rs6000_emit_move (operands[0], operands[1], V16QImode); DONE; }")
!
! (define_insn "*movv16qi_internal1"
! [(set (match_operand:V16QI 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
! (match_operand:V16QI 1 "input_operand" "v,m,v,r,o,r,W"))]
! "TARGET_ALTIVEC
! && (register_operand (operands[0], V16QImode)
! || register_operand (operands[1], V16QImode))"
! "*
! {
! switch (which_alternative)
! {
! case 0: return \"stvx %1,%y0\";
! case 1: return \"lvx %0,%y1\";
! case 2: return \"vor %0,%1,%1\";
! case 3: return \"#\";
! case 4: return \"#\";
! case 5: return \"#\";
! case 6: return output_vec_const_move (operands);
! default: abort ();
! }
! }"
! [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
(define_split
[(set (match_operand:V16QI 0 "nonimmediate_operand" "")
--- 138,146 ----
(set (match_dup 0)
(plus:V8HI (match_dup 0)
(match_dup 0)))]
{
operands[3] = gen_easy_vector_constant_add_self (operands[1]);
! })
(define_split
[(set (match_operand:V16QI 0 "nonimmediate_operand" "")
***************
*** 247,284 ****
(set (match_dup 0)
(plus:V16QI (match_dup 0)
(match_dup 0)))]
- "
{
operands[3] = gen_easy_vector_constant_add_self (operands[1]);
! }")
!
! (define_expand "movv4sf"
! [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
! (match_operand:V4SF 1 "any_operand" ""))]
! "TARGET_ALTIVEC"
! "{ rs6000_emit_move (operands[0], operands[1], V4SFmode); DONE; }")
!
! (define_insn "*movv4sf_internal1"
! [(set (match_operand:V4SF 0 "nonimmediate_operand" "=m,v,v,o,r,r,v")
! (match_operand:V4SF 1 "input_operand" "v,m,v,r,o,r,W"))]
! "TARGET_ALTIVEC
! && (register_operand (operands[0], V4SFmode)
! || register_operand (operands[1], V4SFmode))"
! "*
! {
! switch (which_alternative)
! {
! case 0: return \"stvx %1,%y0\";
! case 1: return \"lvx %0,%y1\";
! case 2: return \"vor %0,%1,%1\";
! case 3: return \"#\";
! case 4: return \"#\";
! case 5: return \"#\";
! case 6: return output_vec_const_move (operands);
! default: abort ();
! }
! }"
! [(set_attr "type" "vecstore,vecload,vecsimple,store,load,*,*")])
(define_split
[(set (match_operand:V4SF 0 "nonimmediate_operand" "")
--- 158,166 ----
(set (match_dup 0)
(plus:V16QI (match_dup 0)
(match_dup 0)))]
{
operands[3] = gen_easy_vector_constant_add_self (operands[1]);
! })
(define_split
[(set (match_operand:V4SF 0 "nonimmediate_operand" "")
***************
*** 286,304 ****
"TARGET_ALTIVEC && reload_completed
&& gpr_or_gpr_p (operands[0], operands[1])"
[(pc)]
! { rs6000_split_multireg_move (operands[0], operands[1]); DONE; })
(define_insn "get_vrsave_internal"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(reg:SI 109)] 214))]
"TARGET_ALTIVEC"
- "*
{
if (TARGET_MACHO)
! return \"mfspr %0,256\";
else
! return \"mfvrsave %0\";
! }"
[(set_attr "type" "*")])
(define_insn "*set_vrsave_internal"
--- 168,187 ----
"TARGET_ALTIVEC && reload_completed
&& gpr_or_gpr_p (operands[0], operands[1])"
[(pc)]
! {
! rs6000_split_multireg_move (operands[0], operands[1]); DONE;
! })
(define_insn "get_vrsave_internal"
[(set (match_operand:SI 0 "register_operand" "=r")
(unspec:SI [(reg:SI 109)] 214))]
"TARGET_ALTIVEC"
{
if (TARGET_MACHO)
! return "mfspr %0,256";
else
! return "mfvrsave %0";
! }
[(set_attr "type" "*")])
(define_insn "*set_vrsave_internal"
***************
*** 307,319 ****
(unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
(reg:SI 109)] 30))])]
"TARGET_ALTIVEC"
- "*
{
if (TARGET_MACHO)
! return \"mtspr 256,%1\";
else
! return \"mtvrsave %1\";
! }"
[(set_attr "type" "*")])
(define_insn "*save_world"
--- 190,201 ----
(unspec_volatile:SI [(match_operand:SI 1 "register_operand" "r")
(reg:SI 109)] 30))])]
"TARGET_ALTIVEC"
{
if (TARGET_MACHO)
! return "mtspr 256,%1";
else
! return "mtvrsave %1";
! }
[(set_attr "type" "*")])
(define_insn "*save_world"
***************
*** 321,329 ****
[(clobber (match_operand:SI 1 "register_operand" "=l"))
(use (match_operand:SI 2 "call_operand" "s"))])]
"TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
! {
! return "bl %z2";
! }
[(set_attr "type" "branch")
(set_attr "length" "4")])
--- 203,209 ----
[(clobber (match_operand:SI 1 "register_operand" "=l"))
(use (match_operand:SI 2 "call_operand" "s"))])]
"TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
! "bl %z2"
[(set_attr "type" "branch")
(set_attr "length" "4")])
***************
*** 334,342 ****
(use (match_operand:SI 2 "call_operand" "s"))
(clobber (match_operand:SI 3 "gpc_reg_operand" "=r"))])]
"TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
! {
! return "b %z2";
! })
;; Simple binary operations.
--- 214,220 ----
(use (match_operand:SI 2 "call_operand" "s"))
(clobber (match_operand:SI 3 "gpc_reg_operand" "=r"))])]
"TARGET_MACHO && (DEFAULT_ABI == ABI_DARWIN) && TARGET_32BIT"
! "b %z2")
;; Simple binary operations.