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patterns for HImode with predec/preinc on ARM

From: Nicolas Pitre <nico at cam dot org>
To: gcc-patches at gcc dot gnu dot org
Cc: Richard Earnshaw <rearnsha at arm dot com>
Date: Thu, 11 Nov 2004 16:23:06 -0500 (EST)
Subject: patterns for HImode with predec/preinc on ARM

This patch adds HImode with predec/preinc and writeback addressing for 
ARM.  This is particularly useful to have with some audio processing 
algorithms for example.  Currently there are patterns for SImode and 
QImode but HImode were missing.  Asking permission to commit.

[date]  Nicolas Pitre <nico@cam.org>

	* config/arm/arm.md (strhi_preinc, strhi_predec, loadhi_preinc,
	loadhi_predec, loadhisi_preinc, loadhisi_predec): New patterns.

Index: gcc/config/arm/arm.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.md,v
retrieving revision 1.185
diff -u -r1.185 arm.md
--- gcc/config/arm/arm.md	14 Oct 2004 07:37:10 -0000	1.185
+++ gcc/config/arm/arm.md	11 Nov 2004 20:11:32 -0000
@@ -9282,6 +9282,110 @@
    (set_attr "predicable" "yes")]
 )
 
+(define_insn "*strhi_preinc"
+  [(set (mem:HI (plus:SI (match_operand:SI 1 "s_register_operand" "%0")
+			 (match_operand:SI 2 "index_operand" "rJ")))
+	(match_operand:HI 3 "s_register_operand" "r"))
+   (set (match_operand:SI 0 "s_register_operand" "=r")
+	(plus:SI (match_dup 1) (match_dup 2)))]
+  "TARGET_ARM && arm_arch4
+   && REGNO (operands[0]) != FRAME_POINTER_REGNUM
+   && REGNO (operands[1]) != FRAME_POINTER_REGNUM
+   && (GET_CODE (operands[2]) != REG
+       || REGNO (operands[2]) != FRAME_POINTER_REGNUM)
+   && (GET_CODE (operands[2]) == REG
+       || (INTVAL (operands[2]) < 256 && INTVAL (operands[2]) > -256))"
+  "str%?h\\t%3, [%0, %2]!"
+  [(set_attr "type" "store1")
+   (set_attr "predicable" "yes")]
+)
+
+(define_insn "*strhi_predec"
+  [(set (mem:HI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
+			  (match_operand:SI 2 "s_register_operand" "r")))
+	(match_operand:HI 3 "s_register_operand" "r"))
+   (set (match_operand:SI 0 "s_register_operand" "=r")
+	(minus:SI (match_dup 1) (match_dup 2)))]
+  "TARGET_ARM && arm_arch4
+   && REGNO (operands[0]) != FRAME_POINTER_REGNUM
+   && REGNO (operands[1]) != FRAME_POINTER_REGNUM
+   && (GET_CODE (operands[2]) != REG
+       || REGNO (operands[2]) != FRAME_POINTER_REGNUM)"
+  "str%?h\\t%3, [%0, -%2]!"
+  [(set_attr "type" "store1")
+   (set_attr "predicable" "yes")]
+)
+
+(define_insn "*loadhi_preinc"
+  [(set (match_operand:HI 3 "s_register_operand" "=r")
+	(mem:HI (plus:SI (match_operand:SI 1 "s_register_operand" "%0")
+			 (match_operand:SI 2 "index_operand" "rJ"))))
+   (set (match_operand:SI 0 "s_register_operand" "=r")
+	(plus:SI (match_dup 1) (match_dup 2)))]
+  "TARGET_ARM && arm_arch4
+   && REGNO (operands[0]) != FRAME_POINTER_REGNUM
+   && REGNO (operands[1]) != FRAME_POINTER_REGNUM
+   && (GET_CODE (operands[2]) != REG
+       || REGNO (operands[2]) != FRAME_POINTER_REGNUM)
+   && (GET_CODE (operands[2]) == REG
+       || (INTVAL (operands[2]) < 256 && INTVAL (operands[2]) > -256))"
+  "ldr%?h\\t%3, [%0, %2]!"
+  [(set_attr "type" "load_byte")
+   (set_attr "predicable" "yes")]
+)
+
+(define_insn "*loadhi_predec"
+  [(set (match_operand:HI 3 "s_register_operand" "=r")
+	(mem:HI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
+			  (match_operand:SI 2 "s_register_operand" "r"))))
+   (set (match_operand:SI 0 "s_register_operand" "=r")
+	(minus:SI (match_dup 1) (match_dup 2)))]
+  "TARGET_ARM && arm_arch4
+   && REGNO (operands[0]) != FRAME_POINTER_REGNUM
+   && REGNO (operands[1]) != FRAME_POINTER_REGNUM
+   && (GET_CODE (operands[2]) != REG
+       || REGNO (operands[2])!= FRAME_POINTER_REGNUM)"
+  "ldr%?h\\t%3, [%0, -%2]!"
+  [(set_attr "type" "load_byte")
+   (set_attr "predicable" "yes")]
+)
+
+(define_insn "*loadhisi_preinc"
+  [(set (match_operand:SI 3 "s_register_operand" "=r")
+	(zero_extend:SI
+	 (mem:HI (plus:SI (match_operand:SI 1 "s_register_operand" "%0")
+			  (match_operand:SI 2 "index_operand" "rJ")))))
+   (set (match_operand:SI 0 "s_register_operand" "=r")
+	(plus:SI (match_dup 1) (match_dup 2)))]
+  "TARGET_ARM && arm_arch4
+   && REGNO (operands[0]) != FRAME_POINTER_REGNUM
+   && REGNO (operands[1]) != FRAME_POINTER_REGNUM
+   && (GET_CODE (operands[2]) != REG
+       || REGNO (operands[2]) != FRAME_POINTER_REGNUM)
+   && (GET_CODE (operands[2]) == REG
+       || (INTVAL (operands[2]) < 256 && INTVAL (operands[2]) > -256))"
+  "ldr%?h\\t%3, [%0, %2]!\\t%@ z_extendhisi"
+  [(set_attr "type" "load_byte")
+   (set_attr "predicable" "yes")]
+)
+
+(define_insn "*loadhisi_predec"
+  [(set (match_operand:SI 3 "s_register_operand" "=r")
+	(zero_extend:SI
+	 (mem:HI (minus:SI (match_operand:SI 1 "s_register_operand" "0")
+			   (match_operand:SI 2 "s_register_operand" "r")))))
+   (set (match_operand:SI 0 "s_register_operand" "=r")
+	(minus:SI (match_dup 1) (match_dup 2)))]
+  "TARGET_ARM && arm_arch4
+   && REGNO (operands[0]) != FRAME_POINTER_REGNUM
+   && REGNO (operands[1]) != FRAME_POINTER_REGNUM
+   && (GET_CODE (operands[2]) != REG
+       || REGNO (operands[2]) != FRAME_POINTER_REGNUM)"
+  "ldr%?h\\t%3, [%0, -%2]!\\t%@ z_extendhisi"
+  [(set_attr "type" "load_byte")
+   (set_attr "predicable" "yes")]
+)
+
 (define_insn "*strsi_preinc"
   [(set (mem:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%0")
 			 (match_operand:SI 2 "index_operand" "rJ")))

Follow-Ups:
- Re: patterns for HImode with predec/preinc on ARM
  - From: Richard Earnshaw

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