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Re: [patch] SPARC VIS instructions or PR1820
> Cool, thanks. As for the rest of the patch, I found a problem in the
> 64bit and description, and have fixed up a bunch of testcases for sparc64,
> so I'll post an updated patch after I resolve any conflicts I find.
I forgot to say that I applied another chunk yesterday, the new patterns for
the arithmetic vector operations, unmodified. I only added the 'fptype'
attribute to 'addsi3' and 'subsi3'.
I also commited the corresponding testcases, with 2 changes:
- "useless_function" spells "foo" in GCC dialect :-),
- I unXFAILed fpadd32s.c and fpsub32s.c after adding -O and tweaking them to
work around the problem with the 32-bit calling conventions.
2004-11-10 James A. Morrison <phython@gcc.gnu.org>
PR target/18230
(addsi3, subsi3): Set "fptype" attribute.
(addv2si, addv4hi, addv2hi, subv2si, subv4hi, subv2hi): New patterns.
--
Eric Botcazou
Index: config/sparc/sparc.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/sparc/sparc.md,v
retrieving revision 1.219
diff -u -r1.219 sparc.md
--- config/sparc/sparc.md 9 Nov 2004 17:06:03 -0000 1.219
+++ config/sparc/sparc.md 10 Nov 2004 09:30:11 -0000
@@ -5062,7 +5062,8 @@
add\t%1, %2, %0
sub\t%1, -%2, %0
fpadd32s\t%1, %2, %0"
- [(set_attr "type" "*,*,fga")])
+ [(set_attr "type" "*,*,fga")
+ (set_attr "fptype" "*,*,single")])
(define_insn "*cmp_cc_plus"
[(set (reg:CC_NOOV 100)
@@ -5218,7 +5219,8 @@
sub\t%1, %2, %0
add\t%1, -%2, %0
fpsub32s\t%1, %2, %0"
- [(set_attr "type" "*,*,fga")])
+ [(set_attr "type" "*,*,fga")
+ (set_attr "fptype" "*,*,single")])
(define_insn "*cmp_minus_cc"
[(set (reg:CC_NOOV 100)
@@ -8866,3 +8868,63 @@
"TARGET_TLS && TARGET_ARCH64"
"stx\t%0, [%1 + %2], %%tldo_add(%3)"
[(set_attr "type" "store")])
+
+;; Vector instructions.
+
+(define_insn "addv2si3"
+ [(set (match_operand:V2SI 0 "register_operand" "=e")
+ (plus:V2SI (match_operand:V2SI 1 "register_operand" "%e")
+ (match_operand:V2SI 2 "register_operand" "e")))]
+ "TARGET_VIS"
+ "fpadd32\t%1, %2, %0"
+ [(set_attr "type" "fga")
+ (set_attr "fptype" "double")])
+
+(define_insn "addv4hi3"
+ [(set (match_operand:V4HI 0 "register_operand" "=e")
+ (plus:V4HI (match_operand:V4HI 1 "register_operand" "%e")
+ (match_operand:V4HI 2 "register_operand" "e")))]
+ "TARGET_VIS"
+ "fpadd16\t%1, %2, %0"
+ [(set_attr "type" "fga")
+ (set_attr "fptype" "double")])
+
+;; fpadd32s is emitted by the addsi3 pattern.
+
+(define_insn "addv2hi3"
+ [(set (match_operand:V2HI 0 "register_operand" "=f")
+ (plus:V2HI (match_operand:V2HI 1 "register_operand" "%f")
+ (match_operand:V2HI 2 "register_operand" "f")))]
+ "TARGET_VIS"
+ "fpadd16s\t%1, %2, %0"
+ [(set_attr "type" "fga")
+ (set_attr "fptype" "single")])
+
+(define_insn "subv2si3"
+ [(set (match_operand:V2SI 0 "register_operand" "=e")
+ (minus:V2SI (match_operand:V2SI 1 "register_operand" "e")
+ (match_operand:V2SI 2 "register_operand" "e")))]
+ "TARGET_VIS"
+ "fpsub32\t%1, %2, %0"
+ [(set_attr "type" "fga")
+ (set_attr "fptype" "double")])
+
+(define_insn "subv4hi3"
+ [(set (match_operand:V4HI 0 "register_operand" "=e")
+ (minus:V4HI (match_operand:V4HI 1 "register_operand" "e")
+ (match_operand:V4HI 2 "register_operand" "e")))]
+ "TARGET_VIS"
+ "fpsub16\t%1, %2, %0"
+ [(set_attr "type" "fga")
+ (set_attr "fptype" "double")])
+
+;; fpsub32s is emitted by the subsi3 pattern.
+
+(define_insn "subv2hi3"
+ [(set (match_operand:V2HI 0 "register_operand" "=f")
+ (minus:V2HI (match_operand:V2HI 1 "register_operand" "f")
+ (match_operand:V2HI 2 "register_operand" "f")))]
+ "TARGET_VIS"
+ "fpsub16s\t%1, %2, %0"
+ [(set_attr "type" "fga")
+ (set_attr "fptype" "single")])