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[RFC] PowerPC scheduling multi-instruction patterns
- From: David Edelsohn <dje at watson dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Tue, 09 Nov 2004 18:58:50 -0500
- Subject: [RFC] PowerPC scheduling multi-instruction patterns
This patch improves the accuracy of the scheduling information for
multi-instruction patterns. While I model the function unit occupancy, I
am recording the latency as a single instruction. The multiple
instructions are dependent and will not execute in parallel, so the latter
instructions will occupy clock ticks and should not be modeled by the
scheduler. The next RTL instruction that the scheduler can issue only
should consider the latency of the last instruction. Comments?
Thanks, David
Index: 40x.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/40x.md,v
retrieving revision 1.10
diff -c -p -r1.10 40x.md
*** 40x.md 17 Oct 2004 18:09:43 -0000 1.10
--- 40x.md 9 Nov 2004 23:50:30 -0000
***************
*** 41,46 ****
--- 41,56 ----
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
+ (define_insn_reservation "ppc403-two" 1
+ (and (eq_attr "type" "two")
+ (eq_attr "cpu" "ppc403,ppc405"))
+ "iu_40x,iu_40x")
+
+ (define_insn_reservation "ppc403-three" 1
+ (and (eq_attr "type" "three")
+ (eq_attr "cpu" "ppc403,ppc405"))
+ "iu_40x,iu_40x,iu_40x")
+
(define_insn_reservation "ppc403-compare" 3
(and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare")
(eq_attr "cpu" "ppc403,ppc405"))
Index: 440.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/440.md,v
retrieving revision 1.3
diff -c -p -r1.3 440.md
*** 440.md 9 Jun 2003 17:16:14 -0000 1.3
--- 440.md 9 Nov 2004 23:50:30 -0000
***************
*** 58,63 ****
--- 58,77 ----
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe|ppc440_j_pipe")
+ (define_insn_reservation "ppc440-two" 1
+ (and (eq_attr "type" "two")
+ (eq_attr "cpu" "ppc440"))
+ "ppc440_issue_0+ppc440_issue_1,\
+ ppc440_i_pipe|ppc440_j_pipe,ppc440_i_pipe|ppc440_j_pipe")
+
+ (define_insn_reservation "ppc440-three" 1
+ (and (eq_attr "type" "three")
+ (eq_attr "cpu" "ppc440"))
+ "ppc440_issue_0+ppc440_issue_1,\
+ ppc440_i_pipe|ppc440_j_pipe,\
+ ppc440_i_pipe|ppc440_j_pipe,\
+ ppc440_i_pipe|ppc440_j_pipe")
+
(define_insn_reservation "ppc440-imul" 3
(and (eq_attr "type" "imul,imul_compare")
(eq_attr "cpu" "ppc440"))
Index: 603.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/603.md,v
retrieving revision 1.10
diff -c -p -r1.10 603.md
*** 603.md 5 Jul 2003 00:08:10 -0000 1.10
--- 603.md 9 Nov 2004 23:50:30 -0000
***************
*** 58,63 ****
--- 58,73 ----
(eq_attr "cpu" "ppc603"))
"iu_603")
+ (define_insn_reservation "ppc603-two" 1
+ (and (eq_attr "type" "two")
+ (eq_attr "cpu" "ppc603"))
+ "iu_603,iu_603")
+
+ (define_insn_reservation "ppc603-three" 1
+ (and (eq_attr "type" "three")
+ (eq_attr "cpu" "ppc603"))
+ "iu_603,iu_603,iu_603")
+
; This takes 2 or 3 cycles
(define_insn_reservation "ppc603-imul" 3
(and (eq_attr "type" "imul,imul_compare")
Index: 6xx.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/6xx.md,v
retrieving revision 1.9
diff -c -p -r1.9 6xx.md
*** 6xx.md 9 Jun 2003 17:16:14 -0000 1.9
--- 6xx.md 9 Nov 2004 23:50:30 -0000
***************
*** 68,73 ****
--- 68,83 ----
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"iu1_6xx|iu2_6xx")
+ (define_insn_reservation "ppc604-two" 1
+ (and (eq_attr "type" "two")
+ (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
+ "iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx")
+
+ (define_insn_reservation "ppc604-three" 1
+ (and (eq_attr "type" "three")
+ (eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
+ "iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx")
+
(define_insn_reservation "ppc604-imul" 4
(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
(eq_attr "cpu" "ppc604"))
Index: 7450.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/7450.md,v
retrieving revision 1.11
diff -c -p -r1.11 7450.md
*** 7450.md 17 Oct 2004 18:09:43 -0000 1.11
--- 7450.md 9 Nov 2004 23:50:30 -0000
***************
*** 67,73 ****
(define_insn_reservation "ppc7450-integer" 1
(and (eq_attr "type" "integer,insert_word")
(eq_attr "cpu" "ppc7450"))
! "ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)")
(define_insn_reservation "ppc7450-imul" 4
(and (eq_attr "type" "imul,imul_compare")
--- 67,84 ----
(define_insn_reservation "ppc7450-integer" 1
(and (eq_attr "type" "integer,insert_word")
(eq_attr "cpu" "ppc7450"))
! "ppc7450_du,iu1_7450|iu2_7450|iu3_7450")
!
! (define_insn_reservation "ppc7450-two" 1
! (and (eq_attr "type" "two")
! (eq_attr "cpu" "ppc7450"))
! "ppc7450_du,iu1_7450|iu2_7450|iu3_7450,iu1_7450|iu2_7450|iu3_7450")
!
! (define_insn_reservation "ppc7450-three" 1
! (and (eq_attr "type" "three")
! (eq_attr "cpu" "ppc7450"))
! "ppc7450_du,iu1_7450|iu2_7450|iu3_7450,\
! iu1_7450|iu2_7450|iu3_7450,iu1_7450|iu2_7450|iu3_7450")
(define_insn_reservation "ppc7450-imul" 4
(and (eq_attr "type" "imul,imul_compare")
Index: 7xx.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/7xx.md,v
retrieving revision 1.10
diff -c -p -r1.10 7xx.md
*** 7xx.md 5 Jul 2003 00:08:10 -0000 1.10
--- 7xx.md 9 Nov 2004 23:50:30 -0000
***************
*** 61,67 ****
(define_insn_reservation "ppc750-integer" 1
(and (eq_attr "type" "integer,insert_word")
(eq_attr "cpu" "ppc750,ppc7400"))
! "ppc750_du,(iu1_7xx|iu2_7xx)")
(define_insn_reservation "ppc750-imul" 4
(and (eq_attr "type" "imul,imul_compare")
--- 61,77 ----
(define_insn_reservation "ppc750-integer" 1
(and (eq_attr "type" "integer,insert_word")
(eq_attr "cpu" "ppc750,ppc7400"))
! "ppc750_du,iu1_7xx|iu2_7xx")
!
! (define_insn_reservation "ppc750-two" 1
! (and (eq_attr "type" "two")
! (eq_attr "cpu" "ppc750,ppc7400"))
! "ppc750_du,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx")
!
! (define_insn_reservation "ppc750-three" 1
! (and (eq_attr "type" "three")
! (eq_attr "cpu" "ppc750,ppc7400"))
! "ppc750_du,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx")
(define_insn_reservation "ppc750-imul" 4
(and (eq_attr "type" "imul,imul_compare")
Index: 8540.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/8540.md,v
retrieving revision 1.9
diff -c -p -r1.9 8540.md
*** 8540.md 17 Oct 2004 18:09:43 -0000 1.9
--- 8540.md 9 Nov 2004 23:50:30 -0000
***************
*** 89,94 ****
--- 89,107 ----
(eq_attr "cpu" "ppc8540"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
+ (define_insn_reservation "ppc8540_two" 1
+ (and (eq_attr "type" "two")
+ (eq_attr "cpu" "ppc8540"))
+ "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
+ ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
+
+ (define_insn_reservation "ppc8540_three" 1
+ (and (eq_attr "type" "three")
+ (eq_attr "cpu" "ppc8540"))
+ "ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
+ ppc8540_issue+ppc8540_su_stage0+ppc8540_retire,\
+ ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
+
;; Branch. Actually this latency time is not used by the scheduler.
(define_insn_reservation "ppc8540_branch" 1
(and (eq_attr "type" "jmpreg,branch")
Index: mpc.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/mpc.md,v
retrieving revision 1.8
diff -c -p -r1.8 mpc.md
*** mpc.md 9 Jun 2003 17:16:14 -0000 1.8
--- mpc.md 9 Nov 2004 23:50:30 -0000
***************
*** 46,51 ****
--- 46,61 ----
(eq_attr "cpu" "mpccore"))
"iu_mpc")
+ (define_insn_reservation "mpccore-two" 1
+ (and (eq_attr "type" "two")
+ (eq_attr "cpu" "mpccore"))
+ "iu_mpc,iu_mpc")
+
+ (define_insn_reservation "mpccore-three" 1
+ (and (eq_attr "type" "three")
+ (eq_attr "cpu" "mpccore"))
+ "iu_mpc,iu_mpc,iu_mpc")
+
(define_insn_reservation "mpccore-imul" 2
(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
(eq_attr "cpu" "mpccore"))
Index: power4.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/power4.md,v
retrieving revision 1.18
diff -c -p -r1.18 power4.md
*** power4.md 17 Oct 2004 18:09:44 -0000 1.18
--- power4.md 9 Nov 2004 23:50:30 -0000
***************
*** 183,188 ****
--- 183,208 ----
(eq_attr "cpu" "power4"))
"iq_power4")
+ (define_insn_reservation "power4-two" 2
+ (and (eq_attr "type" "two")
+ (eq_attr "cpu" "power4"))
+ "(du1_power4+du2_power4,iu1_power4,nothing,iu2_power4)\
+ |(du2_power4+du3_power4,iu2_power4,nothing,iu2_power4)\
+ |(du3_power4+du4_power4,iu2_power4,nothing,iu1_power4)\
+ |(du4_power4+du1_power4,iu1_power4,nothing,iu1_power4)")
+
+ (define_insn_reservation "power4-three" 2
+ (and (eq_attr "type" "three")
+ (eq_attr "cpu" "power4"))
+ "(du1_power4+du2_power4+du3_power4,\
+ iu1_power4,nothing,iu2_power4,nothing,iu2_power4)\
+ |(du2_power4+du3_power4+du4_power4,\
+ iu2_power4,nothing,iu2_power4,nothing,iu1_power4)\
+ |(du3_power4+du4_power4+du1_power4,\
+ iu2_power4,nothing,iu1_power4,nothing,iu1_power4)\
+ |(du4_power4+du1_power4+du2_power4,\
+ iu1_power4,nothing,iu2_power4,nothing,iu2_power4)")
+
(define_insn_reservation "power4-insert" 4
(and (eq_attr "type" "insert_word")
(eq_attr "cpu" "power4"))
Index: power5.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/power5.md,v
retrieving revision 1.3
diff -c -p -r1.3 power5.md
*** power5.md 8 Sep 2004 19:55:26 -0000 1.3
--- power5.md 9 Nov 2004 23:50:30 -0000
***************
*** 142,147 ****
--- 142,167 ----
(eq_attr "cpu" "power5"))
"iq_power5")
+ (define_insn_reservation "power5-two" 2
+ (and (eq_attr "type" "two")
+ (eq_attr "cpu" "power5"))
+ "(du1_power5+du2_power5,iu1_power5,nothing,iu2_power5)\
+ |(du2_power5+du3_power5,iu2_power5,nothing,iu2_power5)\
+ |(du3_power5+du4_power5,iu2_power5,nothing,iu1_power5)\
+ |(du4_power5+du1_power5,iu1_power5,nothing,iu1_power5)")
+
+ (define_insn_reservation "power5-three" 2
+ (and (eq_attr "type" "three")
+ (eq_attr "cpu" "power5"))
+ "(du1_power5+du2_power5+du3_power5,\
+ iu1_power5,nothing,iu2_power5,nothing,iu2_power5)\
+ |(du2_power5+du3_power5+du4_power5,\
+ iu2_power5,nothing,iu2_power5,nothing,iu1_power5)\
+ |(du3_power5+du4_power5+du1_power5,\
+ iu2_power5,nothing,iu1_power5,nothing,iu1_power5)\
+ |(du4_power5+du1_power5+du2_power5,\
+ iu1_power5,nothing,iu2_power5,nothing,iu2_power5)")
+
(define_insn_reservation "power5-insert" 4
(and (eq_attr "type" "insert_word")
(eq_attr "cpu" "power5"))
Index: rios1.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rios1.md,v
retrieving revision 1.8
diff -c -p -r1.8 rios1.md
*** rios1.md 9 Jun 2003 17:16:14 -0000 1.8
--- rios1.md 9 Nov 2004 23:50:30 -0000
***************
*** 55,60 ****
--- 55,70 ----
(eq_attr "cpu" "rios1,ppc601"))
"iu_rios1")
+ (define_insn_reservation "rios1-two" 1
+ (and (eq_attr "type" "two")
+ (eq_attr "cpu" "rios1,ppc601"))
+ "iu_rios1,iu_rios1")
+
+ (define_insn_reservation "rios1-three" 1
+ (and (eq_attr "type" "three")
+ (eq_attr "cpu" "rios1,ppc601"))
+ "iu_rios1,iu_rios1,iu_rios1")
+
(define_insn_reservation "rios1-imul" 5
(and (eq_attr "type" "imul,imul_compare")
(eq_attr "cpu" "rios1"))
Index: rios2.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rios2.md,v
retrieving revision 1.8
diff -c -p -r1.8 rios2.md
*** rios2.md 9 Jun 2003 17:16:14 -0000 1.8
--- rios2.md 9 Nov 2004 23:50:30 -0000
***************
*** 43,48 ****
--- 43,58 ----
(eq_attr "cpu" "rios2"))
"iu1_rios2|iu2_rios2")
+ (define_insn_reservation "rios2-two" 1
+ (and (eq_attr "type" "two")
+ (eq_attr "cpu" "rios2"))
+ "iu1_rios2|iu2_rios2,iu1_rios2|iu2_rios2")
+
+ (define_insn_reservation "rios2-three" 1
+ (and (eq_attr "type" "three")
+ (eq_attr "cpu" "rios2"))
+ "iu1_rios2|iu2_rios2,iu1_rios2|iu2_rios2,iu1_rios2|iu2_rios2")
+
(define_insn_reservation "rios2-imul" 2
(and (eq_attr "type" "imul,imul2,imul3,imul_compare")
(eq_attr "cpu" "rios2"))
Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.330
diff -c -p -r1.330 rs6000.md
*** rs6000.md 9 Nov 2004 15:27:23 -0000 1.330
--- rs6000.md 9 Nov 2004 23:50:31 -0000
***************
*** 64,70 ****
;; Define an insn type attribute. This is used in function unit delay
;; computations.
! (define_attr "type" "integer,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
(const_string "integer"))
;; Length (in bytes).
--- 64,70 ----
;; Define an insn type attribute. This is used in function unit delay
;; computations.
! (define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv"
(const_string "integer"))
;; Length (in bytes).
***************
*** 11536,11542 ****
{xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
{xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
{sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
! [(set_attr "length" "12,8,12,12,12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
--- 11536,11543 ----
{xoril|xori} %0,%1,%b2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
{xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0
{sfi|subfic} %0,%1,%2\;{sfi|subfic} %3,%0,0\;{ae|adde} %0,%3,%0"
! [(set_attr "type" "three,two,three,three,three")
! (set_attr "length" "12,8,12,12,12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r")
***************
*** 11550,11556 ****
xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
! [(set_attr "length" "12,8,12,12,12")])
(define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
--- 11551,11558 ----
xori %0,%1,%b2\;subfic %3,%0,0\;adde %0,%3,%0
xoris %0,%1,%u2\;subfic %3,%0,0\;adde %0,%3,%0
subfic %0,%1,%2\;subfic %3,%0,0\;adde %0,%3,%0"
! [(set_attr "type" "three,two,three,three,three")
! (set_attr "length" "12,8,12,12,12")])
(define_insn ""
[(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
***************
*** 11663,11669 ****
{xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
{xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
{sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
! [(set_attr "length" "12,8,12,12,12")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
--- 11665,11672 ----
{xoril|xori} %0,%1,%b2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
{xoriu|xoris} %0,%1,%u2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3
{sfi|subfic} %0,%1,%2\;{sfi|subfic} %0,%0,0\;{aze|addze} %0,%3"
! [(set_attr "type" "three,two,three,three,three")
! (set_attr "length" "12,8,12,12,12")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y")
***************
*** 11762,11768 ****
{xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
{xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
{sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
! [(set_attr "length" "12,8,12,12,12")])
;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
;; since it nabs/sr is just as fast.
--- 11765,11772 ----
{xoril|xori} %0,%1,%b2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
{xoriu|xoris} %0,%1,%u2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0
{sfi|subfic} %0,%1,%2\;{ai|addic} %0,%0,-1\;{sfe|subfe} %0,%0,%0"
! [(set_attr "type" "three,two,three,three,three")
! (set_attr "length" "12,8,12,12,12")])
;; Simplify (ne X (const_int 0)) on the PowerPC. No need to on the Power,
;; since it nabs/sr is just as fast.
***************
*** 11773,11779 ****
(clobber (match_scratch:SI 2 "=&r"))]
"! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
"{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
! [(set_attr "length" "8")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
--- 11777,11784 ----
(clobber (match_scratch:SI 2 "=&r"))]
"! TARGET_POWER && TARGET_32BIT && !TARGET_ISEL"
"{ai|addic} %2,%1,-1\;{sfe|subfe} %0,%2,%1"
! [(set_attr "type" "two")
! (set_attr "length" "8")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
***************
*** 11782,11788 ****
(clobber (match_scratch:DI 2 "=&r"))]
"TARGET_64BIT"
"addic %2,%1,-1\;subfe %0,%2,%1"
! [(set_attr "length" "8")])
;; This is what (plus (ne X (const_int 0)) Y) looks like.
(define_insn ""
--- 11787,11794 ----
(clobber (match_scratch:DI 2 "=&r"))]
"TARGET_64BIT"
"addic %2,%1,-1\;subfe %0,%2,%1"
! [(set_attr "type" "two")
! (set_attr "length" "8")])
;; This is what (plus (ne X (const_int 0)) Y) looks like.
(define_insn ""
***************
*** 11794,11800 ****
(clobber (match_scratch:SI 3 "=&r"))]
"TARGET_32BIT"
"{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
! [(set_attr "length" "8")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
--- 11800,11807 ----
(clobber (match_scratch:SI 3 "=&r"))]
"TARGET_32BIT"
"{ai|addic} %3,%1,-1\;{aze|addze} %0,%2"
! [(set_attr "type" "two")
! (set_attr "length" "8")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
***************
*** 11805,11811 ****
(clobber (match_scratch:DI 3 "=&r"))]
"TARGET_64BIT"
"addic %3,%1,-1\;addze %0,%2"
! [(set_attr "length" "8")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
--- 11812,11819 ----
(clobber (match_scratch:DI 3 "=&r"))]
"TARGET_64BIT"
"addic %3,%1,-1\;addze %0,%2"
! [(set_attr "type" "two")
! (set_attr "length" "8")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
***************
*** 12105,12111 ****
(match_operand:SI 2 "reg_or_short_operand" "rI")))]
"TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
! [(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
--- 12113,12120 ----
(match_operand:SI 2 "reg_or_short_operand" "rI")))]
"TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
! [(set_attr "type" "three")
! (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
***************
*** 12113,12119 ****
(match_operand:DI 2 "reg_or_short_operand" "rI")))]
"TARGET_64BIT"
"subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
! [(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
--- 12122,12129 ----
(match_operand:DI 2 "reg_or_short_operand" "rI")))]
"TARGET_64BIT"
"subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0"
! [(set_attr "type" "three")
! (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
***************
*** 12184,12190 ****
(match_operand:SI 3 "gpc_reg_operand" "r")))]
"TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
! [(set_attr "length" "8")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
--- 12194,12201 ----
(match_operand:SI 3 "gpc_reg_operand" "r")))]
"TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{aze|addze} %0,%3"
! [(set_attr "type" "two")
! (set_attr "length" "8")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
***************
*** 12257,12263 ****
(match_operand:SI 2 "reg_or_short_operand" "rI"))))]
"TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
! [(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
--- 12268,12275 ----
(match_operand:SI 2 "reg_or_short_operand" "rI"))))]
"TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0"
! [(set_attr "type" "three")
! (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=&r")
***************
*** 12267,12273 ****
(match_operand:SI 3 "gpc_reg_operand" "r")))]
"TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
! [(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
--- 12279,12286 ----
(match_operand:SI 3 "gpc_reg_operand" "r")))]
"TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
! [(set_attr "type" "three")
! (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
***************
*** 12616,12622 ****
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
! [(set_attr "type" "insert_word")
(set_attr "length" "8")])
(define_insn ""
--- 12629,12635 ----
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
! [(set_attr "type" "two")
(set_attr "length" "8")])
(define_insn ""
***************
*** 12627,12633 ****
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
! [(set_attr "type" "insert_word")
(set_attr "length" "8")])
(define_insn ""
--- 12640,12646 ----
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
! [(set_attr "type" "two")
(set_attr "length" "8")])
(define_insn ""
***************
*** 12763,12769 ****
"@
{sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
{ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
! [(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
--- 12776,12783 ----
"@
{sf|subfc} %0,%2,%1\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0
{ai|addic} %0,%1,%n2\;{cal %0,0(0)|li %0,0}\;{ae|adde} %0,%0,%0"
! [(set_attr "type" "three")
! (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
***************
*** 12773,12779 ****
"@
subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
! [(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
--- 12787,12794 ----
"@
subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0
addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0"
! [(set_attr "type" "three")
! (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
***************
*** 12850,12856 ****
"@
{sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
{ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
! [(set_attr "length" "8")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
--- 12865,12872 ----
"@
{sf|subfc} %0,%2,%1\;{aze|addze} %0,%3
{ai|addic} %0,%1,%n2\;{aze|addze} %0,%3"
! [(set_attr "type" "two")
! (set_attr "length" "8")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
***************
*** 12929,12935 ****
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
{sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
! [(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
--- 12945,12952 ----
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;nand %0,%0,%0
{sfi|subfic} %0,%1,-1\;{a%I2|add%I2c} %0,%0,%2\;{sfe|subfe} %0,%0,%0"
! [(set_attr "type" "three")
! (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r")
***************
*** 12941,12947 ****
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
! [(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
--- 12958,12965 ----
"@
{sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0
{ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;andc %0,%3,%0"
! [(set_attr "type" "three")
! (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
***************
*** 13022,13028 ****
(const_int 0)))]
"TARGET_32BIT"
"{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
! [(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
--- 13040,13047 ----
(const_int 0)))]
"TARGET_32BIT"
"{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{sri|srwi} %0,%0,31"
! [(set_attr "type" "three")
! (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
***************
*** 13030,13036 ****
(const_int 0)))]
"TARGET_64BIT"
"subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
! [(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
--- 13049,13056 ----
(const_int 0)))]
"TARGET_64BIT"
"subfic %0,%1,0\;addme %0,%0\;srdi %0,%0,63"
! [(set_attr "type" "three")
! (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 2 "cc_reg_operand" "=x,?y")
***************
*** 13140,13146 ****
(match_operand:SI 2 "gpc_reg_operand" "r")))]
"TARGET_32BIT"
"{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
! [(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
--- 13160,13167 ----
(match_operand:SI 2 "gpc_reg_operand" "r")))]
"TARGET_32BIT"
"{a|addc} %0,%1,%1\;{sfe|subfe} %0,%1,%0\;{aze|addze} %0,%2"
! [(set_attr "type" "three")
! (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=&r")
***************
*** 13149,13155 ****
(match_operand:DI 2 "gpc_reg_operand" "r")))]
"TARGET_64BIT"
"addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
! [(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
--- 13170,13177 ----
(match_operand:DI 2 "gpc_reg_operand" "r")))]
"TARGET_64BIT"
"addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2"
! [(set_attr "type" "three")
! (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
***************
*** 13360,13366 ****
(const_int 0))))]
"TARGET_32BIT"
"{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
! [(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
--- 13382,13389 ----
(const_int 0))))]
"TARGET_32BIT"
"{sfi|subfic} %0,%1,0\;{ame|addme} %0,%0\;{srai|srawi} %0,%0,31"
! [(set_attr "type" "three")
! (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
***************
*** 13368,13374 ****
(const_int 0))))]
"TARGET_64BIT"
"subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
! [(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
--- 13391,13398 ----
(const_int 0))))]
"TARGET_64BIT"
"subfic %0,%1,0\;addme %0,%0\;sradi %0,%0,63"
! [(set_attr "type" "three")
! (set_attr "length" "12")])
(define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
***************
*** 13630,13636 ****
(match_operand:SI 2 "reg_or_short_operand" "rI"))))]
"TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
! [(set_attr "type" "insert_word")
(set_attr "length" "8")])
(define_insn ""
--- 13654,13660 ----
(match_operand:SI 2 "reg_or_short_operand" "rI"))))]
"TARGET_32BIT"
"{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0"
! [(set_attr "type" "two")
(set_attr "length" "8")])
(define_insn ""
***************
*** 13639,13645 ****
(match_operand:DI 2 "reg_or_short_operand" "rI"))))]
"TARGET_64BIT"
"subf%I2c %0,%1,%2\;subfe %0,%0,%0"
! [(set_attr "type" "insert_word")
(set_attr "length" "8")])
;; Define both directions of branch and return. If we need a reload
--- 13663,13669 ----
(match_operand:DI 2 "reg_or_short_operand" "rI"))))]
"TARGET_64BIT"
"subf%I2c %0,%1,%2\;subfe %0,%0,%0"
! [(set_attr "type" "two")
(set_attr "length" "8")])
;; Define both directions of branch and return. If we need a reload
Index: rs64.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs64.md,v
retrieving revision 1.9
diff -c -p -r1.9 rs64.md
*** rs64.md 9 Jun 2003 17:16:15 -0000 1.9
--- rs64.md 9 Nov 2004 23:50:31 -0000
***************
*** 46,51 ****
--- 46,61 ----
(eq_attr "cpu" "rs64a"))
"iu_rs64")
+ (define_insn_reservation "rs64a-two" 1
+ (and (eq_attr "type" "two")
+ (eq_attr "cpu" "rs64a"))
+ "iu_rs64,iu_rs64")
+
+ (define_insn_reservation "rs64a-three" 1
+ (and (eq_attr "type" "three")
+ (eq_attr "cpu" "rs64a"))
+ "iu_rs64,iu_rs64,iu_rs64")
+
(define_insn_reservation "rs64a-imul" 20
(and (eq_attr "type" "imul,imul_compare")
(eq_attr "cpu" "rs64a"))