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[RFC] PowerPC sCC patterns
- From: David Edelsohn <dje at watson dot ibm dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Mon, 08 Nov 2004 18:04:08 -0500
- Subject: [RFC] PowerPC sCC patterns
This patch creates splitters for sCC patterns whose final step
does not use the carry bit, namely GTU and LTU. This gives the scheduler
a little more information and a little more freedom.
While testing, I discovered that combine did not choose the best
patterns because rtx_costs did not model those instruction, so this patch
improves the cost model as well.
If anyone notices any mistakes, let me know.
David
* config/rs6000/rs6000.c (rs6000_rtx_costs): Add EQ, GTU, and LTU.
* config/rs6000/rs6000.md (sCC): Split GTU and LTU patterns.
Index: rs6000.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.737
diff -c -p -r1.737 rs6000.c
*** rs6000.c 8 Nov 2004 04:42:35 -0000 1.737
--- rs6000.c 8 Nov 2004 22:54:52 -0000
*************** rs6000_rtx_costs (rtx x, int code, int o
*** 17984,17992 ****
*total = rs6000_cost->fp;
return false;
}
-
break;
default:
break;
}
--- 17984,18015 ----
*total = rs6000_cost->fp;
return false;
}
break;
+ case EQ:
+ case GTU:
+ case LTU:
+ if (mode == Pmode)
+ {
+ switch (outer_code)
+ {
+ case PLUS:
+ case NEG:
+ /* PLUS or NEG already counted so only add one more. */
+ *total = COSTS_N_INSNS (1);
+ break;
+ case SET:
+ *total = COSTS_N_INSNS (3);
+ break;
+ case COMPARE:
+ *total = 0;
+ return true;
+ default:
+ break;
+ }
+ return false;
+ }
+
default:
break;
}
Index: rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.329
diff -c -p -r1.329 rs6000.md
*** rs6000.md 8 Nov 2004 04:42:36 -0000 1.329
--- rs6000.md 8 Nov 2004 22:54:53 -0000
***************
*** 12460,12474 ****
"doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
[(set_attr "length" "12")])
! (define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
"TARGET_32BIT"
! "@
! {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;neg %0,%0
! {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
! [(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
--- 12460,12486 ----
"doz%I2 %0,%1,%2\;nabs %0,%0\;{srai|srawi} %0,%0,31"
[(set_attr "length" "12")])
! (define_insn_and_split ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
(ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
(match_operand:SI 2 "reg_or_neg_short_operand" "r,P")))]
"TARGET_32BIT"
! "#"
! "TARGET_32BIT"
! [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
! (set (match_dup 0) (neg:SI (match_dup 0)))]
! "")
!
! (define_insn_and_split ""
! [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
! (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
! (match_operand:DI 2 "reg_or_neg_short_operand" "r,P")))]
! "TARGET_64BIT"
! "#"
! "TARGET_64BIT"
! [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
! (set (match_dup 0) (neg:DI (match_dup 0)))]
! "")
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
***************
*** 12503,12520 ****
(const_int 0)))]
"")
! (define_insn ""
! [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r")
! (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
! (match_operand:SI 2 "reg_or_neg_short_operand" "r,r,P,P"))
! (match_operand:SI 3 "reg_or_short_operand" "r,I,r,I")))]
"TARGET_32BIT"
! "@
! {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sf|subf} %0,%0,%3
! {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0\;{sfi|subfic} %0,%0,%3
! {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sf|subf} %0,%0,%3
! {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0\;{sfi|subfic} %0,%0,%3"
! [(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
--- 12515,12543 ----
(const_int 0)))]
"")
! (define_insn_and_split ""
! [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
! (plus:SI (ltu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
! (match_operand:SI 2 "reg_or_neg_short_operand" "r,P"))
! (match_operand:SI 3 "reg_or_short_operand" "rI,rI")))]
"TARGET_32BIT"
! "#"
! "TARGET_32BIT"
! [(set (match_dup 0) (neg:SI (ltu:SI (match_dup 1) (match_dup 2))))
! (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
! "")
!
! (define_insn_and_split ""
! [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
! (plus:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
! (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))
! (match_operand:DI 3 "reg_or_short_operand" "rI,rI")))]
! "TARGET_64BIT"
! "#"
! "TARGET_64BIT"
! [(set (match_dup 0) (neg:DI (ltu:DI (match_dup 1) (match_dup 2))))
! (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
! "")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
***************
*** 12596,12601 ****
--- 12619,12634 ----
[(set_attr "length" "8")])
(define_insn ""
+ [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
+ (neg:DI (ltu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")
+ (match_operand:DI 2 "reg_or_neg_short_operand" "r,P"))))]
+ "TARGET_64BIT"
+ "@
+ {sf|subfc} %0,%2,%1\;{sfe|subfe} %0,%0,%0
+ {ai|addic} %0,%1,%n2\;{sfe|subfe} %0,%0,%0"
+ [(set_attr "length" "8")])
+
+ (define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(ge:SI (match_operand:SI 1 "gpc_reg_operand" "r")
(match_operand:SI 2 "reg_or_short_operand" "rI")))
***************
*** 13343,13363 ****
"doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
[(set_attr "length" "12")])
! (define_insn ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
! (match_operand:SI 2 "reg_or_short_operand" "rI")))]
"TARGET_32BIT"
! "{sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;neg %0,%0"
! [(set_attr "length" "12")])
! (define_insn ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
! (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
! (match_operand:DI 2 "reg_or_short_operand" "rI")))]
"TARGET_64BIT"
! "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;neg %0,%0"
! [(set_attr "length" "12")])
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
--- 13376,13402 ----
"doz %0,%2,%1\;nabs %0,%0\;{srai|srawi} %0,%0,31"
[(set_attr "length" "12")])
! (define_insn_and_split ""
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
! (match_operand:SI 2 "reg_or_short_operand" "rI")))]
"TARGET_32BIT"
! "#"
! "TARGET_32BIT"
! [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
! (set (match_dup 0) (neg:SI (match_dup 0)))]
! "")
! (define_insn_and_split ""
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
! (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
! (match_operand:DI 2 "reg_or_short_operand" "rI")))]
"TARGET_64BIT"
! "#"
! "TARGET_64BIT"
! [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
! (set (match_dup 0) (neg:DI (match_dup 0)))]
! "")
(define_insn ""
[(set (match_operand:CC 3 "cc_reg_operand" "=x,?y")
***************
*** 13421,13449 ****
(const_int 0)))]
"")
! (define_insn ""
! [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r")
! (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
! (match_operand:SI 2 "reg_or_short_operand" "I,rI,rI"))
! (match_operand:SI 3 "reg_or_short_operand" "r,r,I")))]
"TARGET_32BIT"
! "@
! {ai|addic} %0,%1,%k2\;{aze|addze} %0,%3
! {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sf|subf} %0,%0,%3
! {sf%I2|subf%I2c} %0,%1,%2\;{sfe|subfe} %0,%0,%0\;{sfi|subfic} %0,%0,%3"
! [(set_attr "length" "8,12,12")])
! (define_insn ""
! [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,&r")
! (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r")
! (match_operand:DI 2 "reg_or_short_operand" "I,rI,rI"))
! (match_operand:DI 3 "reg_or_short_operand" "r,r,I")))]
"TARGET_64BIT"
! "@
! addic %0,%1,%k2\;addze %0,%3
! subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subf %0,%0,%3
! subf%I2c %0,%1,%2\;subfe %0,%0,%0\;subfic %0,%0,%3"
! [(set_attr "length" "8,12,12")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
--- 13460,13488 ----
(const_int 0)))]
"")
! (define_insn_and_split ""
! [(set (match_operand:SI 0 "gpc_reg_operand" "=r")
! (plus:SI (gtu:SI (match_operand:SI 1 "gpc_reg_operand" "r")
! (match_operand:SI 2 "reg_or_short_operand" "rI"))
! (match_operand:SI 3 "reg_or_short_operand" "rI")))]
"TARGET_32BIT"
! "#"
! "TARGET_32BIT"
! [(set (match_dup 0) (neg:SI (gtu:SI (match_dup 1) (match_dup 2))))
! (set (match_dup 0) (minus:SI (match_dup 3) (match_dup 0)))]
! "")
! (define_insn_and_split ""
! [(set (match_operand:DI 0 "gpc_reg_operand" "=r")
! (plus:DI (gtu:DI (match_operand:DI 1 "gpc_reg_operand" "r")
! (match_operand:DI 2 "reg_or_short_operand" "rI"))
! (match_operand:DI 3 "reg_or_short_operand" "rI")))]
"TARGET_64BIT"
! "#"
! "TARGET_64BIT"
! [(set (match_dup 0) (neg:DI (gtu:DI (match_dup 1) (match_dup 2))))
! (set (match_dup 0) (minus:DI (match_dup 3) (match_dup 0)))]
! "")
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")