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Re: PR target/16482: first scheduling pass on SH4

> Alexandre Oliva <> wrote:
>>> 	* config/sh/sh.c (implicit_r0_use_block): New variable.
>>> 	(may_use_r0_in_reload, find_implicit_r0_use): New.
>>> 	(sh_md_init_global): Initialize and set implicit_r0_use_block.
>>> 	(sh_md_finish_global): Cleanup implicit_r0_use_block if needed.
>>> 	(implicit_r0_pressure): New.
>>> 	(sh_reorder): Use implicit_r0_pressure.
>>> 	(sh_reorder2): Likewise.
>> I'm a bit concerned with this approach.  Consider, for example, a (mem
>> (reg)), in which reload finds this reg to be equivalent to a (plus
>> (reg) (reg)), or a (plus (reg) (const_int BIG)).  Both might end up
>> needing r0, and I don't quite see how you could prevent reload from
>> trying such a substitution.
> Agreed.

BTW, I've seen many spill failures in compiling glibc with 4.0.0
for sh4 without -fno-schedule-insns.  Some of them can't be fixed
with my experimental patch.  For example,

strtod_l.c: In function 'round_and_return':
strtod_l.c:275: error: unable to find a register to spill in class 'R0_REGS'
strtod_l.c:275: error: this is the insn:
(insn:HI 39 32 34 2 strtod_l.c:198 (parallel [
            (set (reg:SF 64 fr0 [orig:160 D.8163 ] [160])
                (const_double:SF 0.0 [0x0.0p+0]))
            (use (reg/v:PSI 151 ))
            (clobber (scratch:SI))
        ]) 157 {movsf_ie} (nil)
    (expr_list:REG_UNUSED (scratch:SI)

initgroups.c: In function 'initgroups':
initgroups.c:220: error: unable to find a register to spill in class 'R0_REGS'
initgroups.c:220: error: this is the insn:
(insn:HI 86 85 92 7 initgroups.c:214 (set (reg:SI 147 t)
        (eq:SI (reg/v:SI 10 r10 [orig:161 result ] [161])
            (const_int -1 [0xffffffffffffffff]))) 1 {cmpeqsi_t} (insn_list:REG_DEP_ANTI 81 (insn_list:REG_DEP_ANTI 82 (insn_list:REG_DEP_ANTI 83 (insn_list:REG_DEP_TRUE 84 (nil)))))

So your are quite right.  My approach wouldn't work at all for (b).
I hope that those failures also come from the lcm.c problem suggested
by Joern.


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