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RFC: modify ppc expanders to support e500
- From: Aldy Hernandez <aldyh at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org, geoffk at geoffk dot org, dje at watson dot ibm dot com
- Date: Fri, 22 Oct 2004 16:50:15 -0400
- Subject: RFC: modify ppc expanders to support e500
Hi guys.
Here are some changes to the expanders, adding support for e500 v2.
I'd like some feedback on the patch, specifically the "extendsfdf2"
change. I've visually inspected the generated code triggering the
pattern, and it seems to work ok (for both e500 and classic), but I'm
uncomfortable with changes to insn/splitter's because I don't understand
them well.
I'd like to make sure there's no weird interaction I'm missing.
Does this look ok?
* config/rs6000/rs6000.md (fix_truncdffsi2): Handle e500
doubles.
(floatunssidf2): Same.
(floatsidf2): Same.
* config/rs6000/spe.md ("spe_extendsfdf2"): Remove FIXME comment.
("spe_fix_truncdfsi2"): Same.
(spe_floatunssidf2): Same.
(spe_floatsidf2): Same.
* config/rs6000/rs6000.md ("extendsfdf2"): New expander.
("fpr_extendsfdf2"): Rename.
Index: config/rs6000/rs6000.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.325
diff -c -p -r1.325 rs6000.md
*** config/rs6000/rs6000.md 22 Oct 2004 19:41:58 -0000 1.325
--- config/rs6000/rs6000.md 22 Oct 2004 20:34:49 -0000
***************
*** 4459,4465 ****
;; this case, we just lose precision that we would have otherwise gotten but
;; is not guaranteed. Perhaps this should be tightened up at some point.
! (define_insn_and_split "extendsfdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "0,f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
--- 4459,4471 ----
;; this case, we just lose precision that we would have otherwise gotten but
;; is not guaranteed. Perhaps this should be tightened up at some point.
! (define_expand "extendsfdf2"
! [(set (match_operand:DF 0 "gpc_reg_operand" "")
! (float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "")))]
! "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
! "")
!
! (define_insn_and_split "fpr_extendsfdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=f,?f")
(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "0,f")))]
"TARGET_HARD_FLOAT && TARGET_FPRS"
***************
*** 5126,5131 ****
--- 5132,5142 ----
"TARGET_HARD_FLOAT && TARGET_FPRS"
"
{
+ if (TARGET_E500_DOUBLE)
+ {
+ emit_insn (gen_spe_floatsidf2 (operands[0], operands[1]));
+ DONE;
+ }
if (TARGET_POWERPC64)
{
rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
***************
*** 5205,5213 ****
(use (match_dup 3))
(clobber (match_dup 4))
(clobber (match_dup 5))])]
! "TARGET_HARD_FLOAT && TARGET_FPRS"
"
{
if (TARGET_POWERPC64)
{
rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
--- 5216,5229 ----
(use (match_dup 3))
(clobber (match_dup 4))
(clobber (match_dup 5))])]
! "TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"
{
+ if (TARGET_E500_DOUBLE)
+ {
+ emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1]));
+ DONE;
+ }
if (TARGET_POWERPC64)
{
rtx mem = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
***************
*** 5274,5282 ****
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
(clobber (match_dup 2))
(clobber (match_dup 3))])]
! "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && TARGET_FPRS"
"
{
operands[2] = gen_reg_rtx (DImode);
operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
}")
--- 5290,5303 ----
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "")))
(clobber (match_dup 2))
(clobber (match_dup 3))])]
! "(TARGET_POWER2 || TARGET_POWERPC) && TARGET_HARD_FLOAT && (TARGET_FPRS || TARGET_E500_DOUBLE)"
"
{
+ if (TARGET_E500_DOUBLE)
+ {
+ emit_insn (gen_spe_fix_truncdfsi2 (operands[0], operands[1]));
+ DONE;
+ }
operands[2] = gen_reg_rtx (DImode);
operands[3] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode), 0);
}")
Index: config/rs6000/spe.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/rs6000/spe.md,v
retrieving revision 1.28
diff -c -p -r1.28 spe.md
*** config/rs6000/spe.md 22 Oct 2004 19:41:58 -0000 1.28
--- config/rs6000/spe.md 22 Oct 2004 20:34:49 -0000
***************
*** 93,99 ****
"efdctuiz %0,%1"
[(set_attr "type" "fp")])
- ;; FIXME: fix expander.
(define_insn "spe_extendsfdf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
(float_extend:DF (match_operand:SF 1 "gpc_reg_operand" "r")))]
--- 93,98 ----
***************
*** 115,121 ****
"efsctsiz %0,%1"
[(set_attr "type" "fp")])
- ;; FIXME: fix expander.
(define_insn "spe_fix_truncdfsi2"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
(fix:SI (match_operand:DF 1 "gpc_reg_operand" "r")))]
--- 114,119 ----
***************
*** 130,136 ****
"efscfui %0,%1"
[(set_attr "type" "fp")])
- ;; FIXME: fix expander.
(define_insn "spe_floatunssidf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
(unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
--- 128,133 ----
***************
*** 145,151 ****
"efscfsi %0,%1"
[(set_attr "type" "fp")])
- ;; FIXME: fix expander.
(define_insn "spe_floatsidf2"
[(set (match_operand:DF 0 "gpc_reg_operand" "=r")
(float:DF (match_operand:SI 1 "gpc_reg_operand" "r")))]
--- 142,147 ----