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Committed, CRIS: Fix target/17984, another goof in peephole2:s.
- From: Hans-Peter Nilsson <hp at bitrange dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Wed, 13 Oct 2004 19:36:31 -0400 (EDT)
- Subject: Committed, CRIS: Fix target/17984, another goof in peephole2:s.
See the PR for a few more details.
Tested cross to cris-axis-linux-gnu.
gcc:
PR target/17984
* config/cris/cris.md (asrandb, asrandw, lsrandb, lsrandw): Apply
trunc_int_for_mode for constants used in shortened mode.
gcc/testsuite:
PR target/17984
* gcc.dg/cris-peep2-xsrand2.c: New test.
--- /dev/null Tue Jan 1 05:00:00 1980
+++ cris-peep2-xsrand2.c Thu Oct 14 01:12:38 2004
@@ -0,0 +1,34 @@
+/* { dg-do compile { target cris-*-* } } */
+/* { dg-final { scan-assembler "and.w -137," } } */
+/* { dg-final { scan-assembler "and.b -64," } } */
+/* { dg-final { scan-assembler "and.w -139," } } */
+/* { dg-final { scan-assembler "and.b -63," } } */
+/* { dg-final { scan-assembler-not "and.d" } } */
+/* { dg-options "-O2" } */
+
+/* PR target/17984. Test-case based on
+ testsuite/gcc.dg/cris-peep2-xsrand.c. */
+
+unsigned int
+andwlsr (unsigned int x)
+{
+ return (x >> 16) & 0xff77;
+}
+
+unsigned int
+andblsr (unsigned int x)
+{
+ return (x >> 24) & 0xc0;
+}
+
+int
+andwasr (int x)
+{
+ return (x >> 16) & 0xff75;
+}
+
+int
+andbasr (int x)
+{
+ return (x >> 24) & 0xc1;
+}
Index: cris.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/cris/cris.md,v
retrieving revision 1.20
diff -p -c -r1.20 cris.md
*** cris.md 29 Sep 2004 19:46:18 -0000 1.20
--- cris.md 13 Oct 2004 23:16:36 -0000
***************
*** 4717,4725 ****
&& (INTVAL (operands[2])
& ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0"
[(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
! (set (match_dup 3) (and:QI (match_dup 3) (match_dup 2)))]
;; FIXME: CC0 is valid except for the M bit.
! "operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));")
(define_peephole2 ; asrandw (peephole casesi+32)
[(set (match_operand:SI 0 "register_operand" "")
--- 4717,4728 ----
&& (INTVAL (operands[2])
& ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0"
[(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
! (set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))]
;; FIXME: CC0 is valid except for the M bit.
! {
! operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));
! operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));
! })
(define_peephole2 ; asrandw (peephole casesi+32)
[(set (match_operand:SI 0 "register_operand" "")
***************
*** 4735,4743 ****
&& (INTVAL (operands[2])
& ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0"
[(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
! (set (match_dup 3) (and:HI (match_dup 3) (match_dup 2)))]
;; FIXME: CC0 is valid except for the M bit.
! "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
(define_peephole2 ; lsrandb (peephole casesi+33)
[(set (match_operand:SI 0 "register_operand" "")
--- 4738,4749 ----
&& (INTVAL (operands[2])
& ((HOST_WIDE_INT) -1 << (32 - INTVAL (operands[1])))) == 0"
[(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
! (set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))]
;; FIXME: CC0 is valid except for the M bit.
! {
! operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
! operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode));
! })
(define_peephole2 ; lsrandb (peephole casesi+33)
[(set (match_operand:SI 0 "register_operand" "")
***************
*** 4749,4757 ****
&& INTVAL (operands[2]) < 255
&& INTVAL (operands[1]) > 23"
[(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
! (set (match_dup 3) (and:QI (match_dup 3) (match_dup 2)))]
;; FIXME: CC0 is valid except for the M bit.
! "operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));")
(define_peephole2 ; lsrandw (peephole casesi+34)
[(set (match_operand:SI 0 "register_operand" "")
--- 4755,4766 ----
&& INTVAL (operands[2]) < 255
&& INTVAL (operands[1]) > 23"
[(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
! (set (match_dup 3) (and:QI (match_dup 3) (match_dup 4)))]
;; FIXME: CC0 is valid except for the M bit.
! {
! operands[3] = gen_rtx_REG (QImode, REGNO (operands[0]));
! operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), QImode));
! })
(define_peephole2 ; lsrandw (peephole casesi+34)
[(set (match_operand:SI 0 "register_operand" "")
***************
*** 4763,4771 ****
&& INTVAL (operands[2]) != 255
&& INTVAL (operands[1]) > 15"
[(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
! (set (match_dup 3) (and:HI (match_dup 3) (match_dup 2)))]
;; FIXME: CC0 is valid except for the M bit.
! "operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));")
;; Change
--- 4772,4783 ----
&& INTVAL (operands[2]) != 255
&& INTVAL (operands[1]) > 15"
[(set (match_dup 0) (lshiftrt:SI (match_dup 0) (match_dup 1)))
! (set (match_dup 3) (and:HI (match_dup 3) (match_dup 4)))]
;; FIXME: CC0 is valid except for the M bit.
! {
! operands[3] = gen_rtx_REG (HImode, REGNO (operands[0]));
! operands[4] = GEN_INT (trunc_int_for_mode (INTVAL (operands[2]), HImode));
! })
;; Change
brgds, H-P