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Re: [PATCH] Add vcond_gen_code optab and expand VEC_COND_EXPR

From: Devang Patel <dpatel at apple dot com>
To: Richard Henderson <rth at redhat dot com>
Cc: GCC Patches <gcc-patches at gcc dot gnu dot org>
Date: Tue, 21 Sep 2004 15:08:22 -0700
Subject: Re: [PATCH] Add vcond_gen_code optab and expand VEC_COND_EXPR
References: <5C534A82-0800-11D9-A562-000393A91CAA@apple.com> <20040921214859.GC32068@redhat.com>

On Sep 21, 2004, at 2:48 PM, Richard Henderson wrote:

On Thu, Sep 16, 2004 at 09:49:22AM -0700, Devang Patel wrote:

+   /* Force operands into register.  */
+   rtx_op0 = force_reg (TYPE_MODE (TREE_TYPE (t_op0)), rtx_op0);
+   rtx_op1 = force_reg (TYPE_MODE (TREE_TYPE (t_op1)), rtx_op1);

Why?

because I did not consider cases like below..

Certainly it's the case that the zero vector often exists
as a register in hardware.  You need to be looking at predicates
for the appropriate optab.

OK

-
Devang

References:
- [PATCH] Add vcond_gen_code optab and expand VEC_COND_EXPR
  - From: Devang Patel
- Re: [PATCH] Add vcond_gen_code optab and expand VEC_COND_EXPR
  - From: Richard Henderson

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