This is the mail archive of the
gcc-patches@gcc.gnu.org
mailing list for the GCC project.
Re: [m68k] Add 'R' constraint for ColdFire V4 mov3q.l instruction
- From: Peter Barada <peter at the-baradas dot com>
- To: hp at bitrange dot com
- Cc: gcc-patches at gcc dot gnu dot org, peter at the-baradas dot com
- Date: Mon, 20 Sep 2004 23:50:23 -0400 (EDT)
- Subject: Re: [m68k] Add 'R' constraint for ColdFire V4 mov3q.l instruction
- References: <20040729154225.545E1990F4@baradas.org> <Pine.BSF.4.58.0409162224200.59402@dair.pair.com>
>> 2004-07-29 Peter Barada <peter@the-baradas.com>
>>
>> * config/m68k/m68k.h: (EXTRA_CONSTRAINT): Add 'R' for mov3q
>> constants
>
>Looks like nobody reviewed this?
Not that I know of :)
>> #define EXTRA_CONSTRAINT(OP,CODE) \
>> + ((((CODE) == 'R') && TARGET_CFV4) \
>> + ? (GET_CODE (OP) == CONST_INT \
>> + && (INTVAL (OP) == -1 \
>> + || (INTVAL (OP) >= 1 && INTVAL (OP) <= 7))) \
>> + : \
>
>Since this is a CONST_INT, and you're out of
>CONST_OK_FOR_LETTER_P letters, I'd recommend defining
>CONST_OK_FOR_CONSTRAINT_P instead (and making one of the
>existing CONST_OK_FOR_LETTER_P letters multi-letter).
>Benefit: GCC will know that only a CONST_INT can match.
>Caveat: editing...
>Beware: you can't have both CONST_OK_FOR_LETTER_P and
>CONST_OK_FOR_CONSTRAINT_P and there's no check for that; the
>CONST_OK_FOR_LETTER_P definition will be unused.
>
>(You might have considered this, but you didn't mention that.)
Well, its a mess since the integer constants are so diverse that no
naming convention jumps out at me as a decent starting point. As a
first cut, I converted from CONST_OK_FOR_LETTER_P to
CONST_OK_FOR_CONSTRAINT_P, and using sh.h as an example, started by
converting ober only 'I' into multichar constraints, using a two
character moniker:
'Im' for mov3q constants -1,1..7
'Is' for shift constants 0..8
'Ir' for rotate constants 0..8
'It' for trap constants 0..8
Of course I can slap back together all of the 0..8 constants into a
single multichar constraint, but what should its name be? As another
point, should we split up the constraints base don how they are used,
or what their ranges are? This isn't great, but it *does* immediately
solve the current problem of using 'R' as a constant constraint.
I can submit patches to convert the rest of the single char CONST_INT
constraints into multichar ones, but we have to come to a consensus on
what those multichar constraints should be called. I'm sure there are
a few people(like myself) that have ingrained single-char constraints,
*especially* for m68k since it was one of the original ports...
Comments are *wanted*, especially those that suggest what the
multichar constraint names for CONST_INT *should* be.
Since I'm not subscribed to gcc-patches, please CC: me any comments.
I've built uberbaum with this change....
--
Peter Barada
peter@the-baradas.com
Index: m68k.h
===================================================================
RCS file: /cvs/uberbaum/gcc/config/m68k/m68k.h,v
retrieving revision 1.120
diff -c -3 -p -r1.120 m68k.h
*** m68k.h 6 Aug 2004 07:14:56 -0000 1.120
--- m68k.h 21 Sep 2004 03:47:44 -0000
*************** extern enum reg_class regno_reg_class[];
*** 569,576 ****
NO_REGS) : \
NO_REGS)))
! /* For the m68k, `I' is used for the range 1 to 8
! allowed as immediate shift counts and in addq.
`J' is used for the range of signed numbers that fit in 16 bits.
`K' is for numbers that moveq can't handle.
`L' is for range -8 to -1, range of values that can be added with subq.
--- 569,599 ----
NO_REGS) : \
NO_REGS)))
! /* Constraints for integers...
! Ia 0 < VALUE <= 8 Allowed as immediate shift counts.
! Im VALUE == -1 || 0 < VALUE <= 7 Immediate constants mov3q can store.
! Ir 0 < VALUE <= 8 Allowed as immediate rotate counts.
! Is 0 < VALUE <= 8 Allowed as immediate shift counts.
! It 0 < VALUE <= 8 Allowed as immediate trap values. */
! #define CONST_OK_FOR_Ia(VALUE) \
! ((VALUE) > 0 && (VALUE) <= 8)
! #define CONST_OK_FOR_Im(VALUE) \
! ((VALUE) == -1 || ((VALUE) >= 1 && (VALUE) <= 7))
! #define CONST_OK_FOR_Ir(VALUE) \
! ((VALUE) > 0 && (VALUE) <= 8)
! #define CONST_OK_FOR_Is(VALUE) \
! ((VALUE) > 0 && (VALUE) <= 8)
! #define CONST_OK_FOR_It(VALUE) \
! ((VALUE) > 0 && (VALUE) <= 8)
! #define CONST_OK_FOR_I(VALUE, STR) \
! ((STR)[1] == 'a' ? CONST_OK_FOR_Ia (VALUE) \
! : (STR)[1] == 'm' ? CONST_OK_FOR_Im (VALUE) \
! : (STR)[1] == 'r' ? CONST_OK_FOR_Ir (VALUE) \
! : (STR)[1] == 's' ? CONST_OK_FOR_Is (VALUE) \
! : (STR)[1] == 't' ? CONST_OK_FOR_It (VALUE) \
! : 0)
!
! /* For the m68k, `I' is a prefix used for integer constants of 3 bits
`J' is used for the range of signed numbers that fit in 16 bits.
`K' is for numbers that moveq can't handle.
`L' is for range -8 to -1, range of values that can be added with subq.
*************** extern enum reg_class regno_reg_class[];
*** 578,585 ****
'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
'O' is for 16 (for rotate using swap).
'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */
! #define CONST_OK_FOR_LETTER_P(VALUE, C) \
! ((C) == 'I' ? (VALUE) > 0 && (VALUE) <= 8 : \
(C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
(C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
(C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
--- 601,608 ----
'N' is for range 24 to 31, rotatert:SI 8 to 1 expressed as rotate.
'O' is for 16 (for rotate using swap).
'P' is for range 8 to 15, rotatert:HI 8 to 1 expressed as rotate. */
! #define CONST_OK_FOR_CONSTRAINT_P(VALUE, C, STR) \
! ((C) == 'I' ? CONST_OK_FOR_I ((VALUE), (STR)) : \
(C) == 'J' ? (VALUE) >= -0x8000 && (VALUE) <= 0x7FFF : \
(C) == 'K' ? (VALUE) < -0x80 || (VALUE) >= 0x80 : \
(C) == 'L' ? (VALUE) < 0 && (VALUE) >= -8 : \
*************** extern enum reg_class regno_reg_class[];
*** 588,593 ****
--- 611,620 ----
(C) == 'O' ? (VALUE) == 16 : \
(C) == 'P' ? (VALUE) >= 8 && (VALUE) <= 15 : 0)
+ #define CONSTRAINT_LEN(C, STR) \
+ ((C) == 'I') ? 2 \
+ : DEFAULT_CONSTRAINT_LEN ((C), (STR))
+
/* "G" defines all of the floating constants that are *NOT* 68881
constants. This is so 68881 constants get reloaded and the
fpmovecr is used. */
Index: m68k.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/m68k/m68k.md,v
retrieving revision 1.80
diff -c -3 -p -r1.80 m68k.md
*** m68k.md 6 Aug 2004 07:14:56 -0000 1.80
--- m68k.md 21 Sep 2004 03:47:45 -0000
***************
*** 58,64 ****
;; info.
;;- Immediate integer operand constraints:
! ;;- 'I' 1 .. 8
;;- 'J' -32768 .. 32767
;;- 'K' all integers EXCEPT -128 .. 127
;;- 'L' -8 .. -1
--- 58,67 ----
;; info.
;;- Immediate integer operand constraints:
! ;;- 'Ia' 1 .. 8
! ;;- 'Ir' 1 .. 8
! ;;- 'It' 1 .. 8
! ;;- 'Im' -1, 1 .. 7
;;- 'J' -32768 .. 32767
;;- 'K' all integers EXCEPT -128 .. 127
;;- 'L' -8 .. -1
***************
*** 685,691 ****
(define_insn "*movsi_cfv4"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g,U")
! (match_operand:SI 1 "general_operand" "Rg,Rr<Q>,U"))]
"TARGET_CFV4"
"* return output_move_simode (operands);")
--- 688,694 ----
(define_insn "*movsi_cfv4"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g,U")
! (match_operand:SI 1 "general_operand" "Img,Imr<Q>,U"))]
"TARGET_CFV4"
"* return output_move_simode (operands);")
***************
*** 1841,1847 ****
(define_insn "*addsi3_internal"
[(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,d,a")
(plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0,0")
! (match_operand:SI 2 "general_src_operand" "dIKLT,rJK,a,mSrIKLT,mSrIKLs")))]
"! TARGET_COLDFIRE"
--- 1844,1850 ----
(define_insn "*addsi3_internal"
[(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,d,a")
(plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0,0")
! (match_operand:SI 2 "general_src_operand" "dIaKLT,rJK,a,mSrIaKLT,mSrIaKLs")))]
"! TARGET_COLDFIRE"
***************
*** 1850,1856 ****
(define_insn "*addsi3_5200"
[(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,r")
(plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
! (match_operand:SI 2 "general_src_operand" "d,rJK,a,mrIKLs")))]
"TARGET_COLDFIRE"
"* return output_addsi3 (operands);")
--- 1853,1859 ----
(define_insn "*addsi3_5200"
[(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,r")
(plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
! (match_operand:SI 2 "general_src_operand" "d,rJK,a,mrIaKLs")))]
"TARGET_COLDFIRE"
"* return output_addsi3 (operands);")
***************
*** 3977,3983 ****
(define_insn "ashlsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
(ashift:SI (match_operand:SI 1 "register_operand" "0")
! (match_operand:SI 2 "general_operand" "dI")))]
""
{
if (operands[2] == const1_rtx)
--- 3980,3986 ----
(define_insn "ashlsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
(ashift:SI (match_operand:SI 1 "register_operand" "0")
! (match_operand:SI 2 "general_operand" "dIs")))]
""
{
if (operands[2] == const1_rtx)
***************
*** 3991,4018 ****
(define_insn "ashlhi3"
[(set (match_operand:HI 0 "register_operand" "=d")
(ashift:HI (match_operand:HI 1 "register_operand" "0")
! (match_operand:HI 2 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"lsl%.w %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
(ashift:HI (match_dup 0)
! (match_operand:HI 1 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"lsl%.w %1,%0")
(define_insn "ashlqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
(ashift:QI (match_operand:QI 1 "register_operand" "0")
! (match_operand:QI 2 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"lsl%.b %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
(ashift:QI (match_dup 0)
! (match_operand:QI 1 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"lsl%.b %1,%0")
--- 3994,4021 ----
(define_insn "ashlhi3"
[(set (match_operand:HI 0 "register_operand" "=d")
(ashift:HI (match_operand:HI 1 "register_operand" "0")
! (match_operand:HI 2 "general_operand" "dIs")))]
"!TARGET_COLDFIRE"
"lsl%.w %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
(ashift:HI (match_dup 0)
! (match_operand:HI 1 "general_operand" "dIs")))]
"!TARGET_COLDFIRE"
"lsl%.w %1,%0")
(define_insn "ashlqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
(ashift:QI (match_operand:QI 1 "register_operand" "0")
! (match_operand:QI 2 "general_operand" "dIs")))]
"!TARGET_COLDFIRE"
"lsl%.b %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
(ashift:QI (match_dup 0)
! (match_operand:QI 1 "general_operand" "dIs")))]
"!TARGET_COLDFIRE"
"lsl%.b %1,%0")
***************
*** 4160,4194 ****
(define_insn "ashrsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
! (match_operand:SI 2 "general_operand" "dI")))]
""
"asr%.l %2,%0")
(define_insn "ashrhi3"
[(set (match_operand:HI 0 "register_operand" "=d")
(ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
! (match_operand:HI 2 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"asr%.w %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
(ashiftrt:HI (match_dup 0)
! (match_operand:HI 1 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"asr%.w %1,%0")
(define_insn "ashrqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
(ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
! (match_operand:QI 2 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"asr%.b %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
(ashiftrt:QI (match_dup 0)
! (match_operand:QI 1 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"asr%.b %1,%0")
--- 4163,4197 ----
(define_insn "ashrsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
(ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
! (match_operand:SI 2 "general_operand" "dIs")))]
""
"asr%.l %2,%0")
(define_insn "ashrhi3"
[(set (match_operand:HI 0 "register_operand" "=d")
(ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
! (match_operand:HI 2 "general_operand" "dIs")))]
"!TARGET_COLDFIRE"
"asr%.w %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
(ashiftrt:HI (match_dup 0)
! (match_operand:HI 1 "general_operand" "dIs")))]
"!TARGET_COLDFIRE"
"asr%.w %1,%0")
(define_insn "ashrqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
(ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
! (match_operand:QI 2 "general_operand" "dIs")))]
"!TARGET_COLDFIRE"
"asr%.b %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
(ashiftrt:QI (match_dup 0)
! (match_operand:QI 1 "general_operand" "dIs")))]
"!TARGET_COLDFIRE"
"asr%.b %1,%0")
***************
*** 4347,4381 ****
(define_insn "lshrsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
! (match_operand:SI 2 "general_operand" "dI")))]
""
"lsr%.l %2,%0")
(define_insn "lshrhi3"
[(set (match_operand:HI 0 "register_operand" "=d")
(lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
! (match_operand:HI 2 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"lsr%.w %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
(lshiftrt:HI (match_dup 0)
! (match_operand:HI 1 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"lsr%.w %1,%0")
(define_insn "lshrqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
(lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
! (match_operand:QI 2 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"lsr%.b %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
(lshiftrt:QI (match_dup 0)
! (match_operand:QI 1 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"lsr%.b %1,%0")
--- 4350,4384 ----
(define_insn "lshrsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
(lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
! (match_operand:SI 2 "general_operand" "dIs")))]
""
"lsr%.l %2,%0")
(define_insn "lshrhi3"
[(set (match_operand:HI 0 "register_operand" "=d")
(lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
! (match_operand:HI 2 "general_operand" "dIs")))]
"!TARGET_COLDFIRE"
"lsr%.w %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
(lshiftrt:HI (match_dup 0)
! (match_operand:HI 1 "general_operand" "dIs")))]
"!TARGET_COLDFIRE"
"lsr%.w %1,%0")
(define_insn "lshrqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
(lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
! (match_operand:QI 2 "general_operand" "dIs")))]
"!TARGET_COLDFIRE"
"lsr%.b %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
(lshiftrt:QI (match_dup 0)
! (match_operand:QI 1 "general_operand" "dIs")))]
"!TARGET_COLDFIRE"
"lsr%.b %1,%0")
***************
*** 4384,4390 ****
(define_insn "rotlsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
(rotate:SI (match_operand:SI 1 "register_operand" "0")
! (match_operand:SI 2 "general_operand" "dINO")))]
"!TARGET_COLDFIRE"
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
--- 4387,4393 ----
(define_insn "rotlsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
(rotate:SI (match_operand:SI 1 "register_operand" "0")
! (match_operand:SI 2 "general_operand" "dIrNO")))]
"!TARGET_COLDFIRE"
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
***************
*** 4401,4407 ****
(define_insn "rotlhi3"
[(set (match_operand:HI 0 "register_operand" "=d")
(rotate:HI (match_operand:HI 1 "register_operand" "0")
! (match_operand:HI 2 "general_operand" "dIP")))]
"!TARGET_COLDFIRE"
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
--- 4404,4410 ----
(define_insn "rotlhi3"
[(set (match_operand:HI 0 "register_operand" "=d")
(rotate:HI (match_operand:HI 1 "register_operand" "0")
! (match_operand:HI 2 "general_operand" "dIrP")))]
"!TARGET_COLDFIRE"
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
***************
*** 4416,4422 ****
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
(rotate:HI (match_dup 0)
! (match_operand:HI 1 "general_operand" "dIP")))]
"!TARGET_COLDFIRE"
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
--- 4419,4425 ----
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
(rotate:HI (match_dup 0)
! (match_operand:HI 1 "general_operand" "dIrP")))]
"!TARGET_COLDFIRE"
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
***************
*** 4431,4437 ****
(define_insn "rotlqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
(rotate:QI (match_operand:QI 1 "register_operand" "0")
! (match_operand:QI 2 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
--- 4434,4440 ----
(define_insn "rotlqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
(rotate:QI (match_operand:QI 1 "register_operand" "0")
! (match_operand:QI 2 "general_operand" "dIr")))]
"!TARGET_COLDFIRE"
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
***************
*** 4446,4452 ****
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
(rotate:QI (match_dup 0)
! (match_operand:QI 1 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
--- 4449,4455 ----
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
(rotate:QI (match_dup 0)
! (match_operand:QI 1 "general_operand" "dIr")))]
"!TARGET_COLDFIRE"
{
if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
***************
*** 4461,4495 ****
(define_insn "rotrsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
(rotatert:SI (match_operand:SI 1 "register_operand" "0")
! (match_operand:SI 2 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"ror%.l %2,%0")
(define_insn "rotrhi3"
[(set (match_operand:HI 0 "register_operand" "=d")
(rotatert:HI (match_operand:HI 1 "register_operand" "0")
! (match_operand:HI 2 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"ror%.w %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
(rotatert:HI (match_dup 0)
! (match_operand:HI 1 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"ror%.w %1,%0")
(define_insn "rotrqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
(rotatert:QI (match_operand:QI 1 "register_operand" "0")
! (match_operand:QI 2 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"ror%.b %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
(rotatert:QI (match_dup 0)
! (match_operand:QI 1 "general_operand" "dI")))]
"!TARGET_COLDFIRE"
"ror%.b %1,%0")
--- 4464,4498 ----
(define_insn "rotrsi3"
[(set (match_operand:SI 0 "register_operand" "=d")
(rotatert:SI (match_operand:SI 1 "register_operand" "0")
! (match_operand:SI 2 "general_operand" "dIr")))]
"!TARGET_COLDFIRE"
"ror%.l %2,%0")
(define_insn "rotrhi3"
[(set (match_operand:HI 0 "register_operand" "=d")
(rotatert:HI (match_operand:HI 1 "register_operand" "0")
! (match_operand:HI 2 "general_operand" "dIr")))]
"!TARGET_COLDFIRE"
"ror%.w %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
(rotatert:HI (match_dup 0)
! (match_operand:HI 1 "general_operand" "dIr")))]
"!TARGET_COLDFIRE"
"ror%.w %1,%0")
(define_insn "rotrqi3"
[(set (match_operand:QI 0 "register_operand" "=d")
(rotatert:QI (match_operand:QI 1 "register_operand" "0")
! (match_operand:QI 2 "general_operand" "dIr")))]
"!TARGET_COLDFIRE"
"ror%.b %2,%0")
(define_insn ""
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
(rotatert:QI (match_dup 0)
! (match_operand:QI 1 "general_operand" "dIr")))]
"!TARGET_COLDFIRE"
"ror%.b %1,%0")
***************
*** 7089,7095 ****
(define_insn "conditional_trap"
[(trap_if (match_operator 0 "valid_dbcc_comparison_p"
[(cc0) (const_int 0)])
! (match_operand:SI 1 "const_int_operand" "I"))]
"TARGET_68020 && ! flags_in_68881 ()"
{
switch (GET_CODE (operands[0]))
--- 7092,7098 ----
(define_insn "conditional_trap"
[(trap_if (match_operator 0 "valid_dbcc_comparison_p"
[(cc0) (const_int 0)])
! (match_operand:SI 1 "const_int_operand" "It"))]
"TARGET_68020 && ! flags_in_68881 ()"
{
switch (GET_CODE (operands[0]))