Re: [PATCH] x86 peephole2s to optimize "1LL << x"

[Richard Henderson <rth at redhat dot com>]

On Sat, Sep 11, 2004 at 09:14:08PM -0600, Roger Sayle wrote:
> But the real bottom line (in my mind) is that implementating your method
> (A), 2*setcc + 2*shift in the x86 backend results in an "1LL << x"
> implementation an astounding seven times faster than current mainline.

Thanks.  I've come up with a final sequence,

        movl    %ecx, %edi
        shrl    $5, %edi
        andl    $1, %edi
        movl    %edi, %esi
        sall    %cl, %edi
        xorl    $1, %esi
        sall    %cl, %esi

that I will use when the registers chosen aren't appropriate for setcc.
It does use one more shift, but given the disparity between 

> a	26.98s	 2.98s		 13.1%		2*setcc+2*shift
> b	30.03s	 6.03s		 26.6%		push+shift+2*cmov

I'm betting it's still a win.  You could run it through your
test harness if you like (using eax/edx, not esi/edi).

I'm doing one more bootstrap and test before checking this in.


r~