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PATCH [FSF mainline] - ppc-darwin mixed mode does not clobber TFmode regs
- From: Fariborz Jahanian <fjahanian at apple dot com>
- To: "gcc-patches at gcc dot gnu dot org Patches" <gcc-patches at gcc dot gnu dot org>
- Date: Wed, 25 Aug 2004 08:40:36 -0700
- Subject: PATCH [FSF mainline] - ppc-darwin mixed mode does not clobber TFmode regs
Following test case is part of gcc.c-torture/execute/conversion.c test
of dejagnu-test suite. It fails with
-mcpu=G5 (mixed mode) on ppc-darwin where 'long double' is 128 bits.
TFmode registers must be
marked as 'call clobbered'. Patch has been bootstrapped and dejagnu
tested on apple-ppc-darwin
(with and without -mcpu=G5).
OK for mainline?
- Thanks, fariborz (fjahanian@apple.com)
Test case:
/* { dg-do run { target powerpc*-*-darwin* } } */
/* { dg-options "-O2 -mcpu=G5 " } */
/* 128 bit long double */
long double sll2ld(s)
long long int s;
{
return s;
}
main()
{
if (sll2ld((long long int)((~0ULL) >> 1)) != (long double)(long long
int)((~0ULL) >> 1))
abort();
exit(0);
}
ChangeLog:
2004-08-25 Fariborz Jahanian <fjahanian@apple.com>
* config/rs6000/rs6000.h (HARD_REGNO_CALL_PART_CLOBBERED): Added
TFmode as additional register mode cloberred by call.
Patch:
Index: rs6000.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.h,v
retrieving revision 1.336
diff -c -p -r1.336 rs6000.h
*** rs6000.h 21 Aug 2004 01:40:00 -0000 1.336
--- rs6000.h 24 Aug 2004 22:12:20 -0000
*************** extern const char *rs6000_warn_altivec_l
*** 1016,1022 ****
#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
((TARGET_32BIT && TARGET_POWERPC64 \
! && (MODE == DImode || MODE == DFmode) \
&& INT_REGNO_P (REGNO)) ? 1 : 0)
#define ALTIVEC_VECTOR_MODE(MODE) \
--- 1016,1022 ----
#define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \
((TARGET_32BIT && TARGET_POWERPC64 \
! && (MODE == DImode || MODE == DFmode || MODE == TFmode) \
&& INT_REGNO_P (REGNO)) ? 1 : 0)
#define ALTIVEC_VECTOR_MODE(MODE) \