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[committed] mips.md macroisation (1/n)
- From: Richard Sandiford <rsandifo at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Date: Mon, 23 Aug 2004 08:00:26 +0100
- Subject: [committed] mips.md macroisation (1/n)
Part 1 of the mips.md macroisation process. This patch handles the
integer mulM3 multiplication patterns. The only non-mechanical change
is to add TARGET_MAD to GENERATE_MULT3_SI rather than check for it
separately each time.
Bootstrapped & regression tested on mips-sgi-irix6.5. Applied to head.
Richard
* config/mips/mips.h (GENERATE_MULT3_SI): Check TARGET_MAD.
* config/mips/mips.md (mul[sd]i3, mul[sd]i3_internal)
(mul[sd]i3_r4000): Redefine using :GPR.
(mulsi3_mult3): Don't check TARGET_MAD separately.
(muldi3_mult3): Moved after mulsi_mult3.
Index: config/mips/mips.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.h,v
retrieving revision 1.359
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.359 mips.h
--- config/mips/mips.h 23 Aug 2004 06:53:46 -0000 1.359
+++ config/mips/mips.h 23 Aug 2004 06:55:38 -0000
@@ -779,6 +779,7 @@ #define GENERATE_MULT3_SI ((TARGET
|| TARGET_MIPS5500 \
|| TARGET_MIPS7000 \
|| TARGET_MIPS9000 \
+ || TARGET_MAD \
|| ISA_MIPS32 \
|| ISA_MIPS32R2 \
|| ISA_MIPS64) \
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.271
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.271 mips.md
--- config/mips/mips.md 23 Aug 2004 06:53:46 -0000 1.271
+++ config/mips/mips.md 23 Aug 2004 06:55:45 -0000
@@ -822,18 +822,19 @@ (define_insn "mulsf3_r4300"
;; These processors have PRId values of 0x00004220 and 0x00004300,
;; respectively.
-(define_expand "mulsi3"
- [(set (match_operand:SI 0 "register_operand")
- (mult:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "register_operand")))]
+(define_expand "mul<mode>3"
+ [(set (match_operand:GPR 0 "register_operand")
+ (mult:GPR (match_operand:GPR 1 "register_operand")
+ (match_operand:GPR 2 "register_operand")))]
""
{
- if (GENERATE_MULT3_SI || TARGET_MAD)
- emit_insn (gen_mulsi3_mult3 (operands[0], operands[1], operands[2]));
+ if (GENERATE_MULT3_<MODE>)
+ emit_insn (gen_mul<mode>3_mult3 (operands[0], operands[1], operands[2]));
else if (!TARGET_FIX_R4000)
- emit_insn (gen_mulsi3_internal (operands[0], operands[1], operands[2]));
+ emit_insn (gen_mul<mode>3_internal (operands[0], operands[1],
+ operands[2]));
else
- emit_insn (gen_mulsi3_r4000 (operands[0], operands[1], operands[2]));
+ emit_insn (gen_mul<mode>3_r4000 (operands[0], operands[1], operands[2]));
DONE;
})
@@ -843,8 +844,7 @@ (define_insn "mulsi3_mult3"
(match_operand:SI 2 "register_operand" "d,d")))
(clobber (match_scratch:SI 3 "=h,h"))
(clobber (match_scratch:SI 4 "=l,X"))]
- "GENERATE_MULT3_SI
- || TARGET_MAD"
+ "GENERATE_MULT3_SI"
{
if (which_alternative == 1)
return "mult\t%1,%2";
@@ -859,8 +859,19 @@ (define_insn "mulsi3_mult3"
return "mul\t%0,%1,%2";
return "mult\t%0,%1,%2";
}
- [(set_attr "type" "imul")
- (set_attr "mode" "SI")])
+ [(set_attr "type" "imul")
+ (set_attr "mode" "SI")])
+
+(define_insn "muldi3_mult3"
+ [(set (match_operand:DI 0 "register_operand" "=d")
+ (mult:DI (match_operand:DI 1 "register_operand" "d")
+ (match_operand:DI 2 "register_operand" "d")))
+ (clobber (match_scratch:DI 3 "=h"))
+ (clobber (match_scratch:DI 4 "=l"))]
+ "TARGET_64BIT && GENERATE_MULT3_DI"
+ "dmult\t%0,%1,%2"
+ [(set_attr "type" "imul")
+ (set_attr "mode" "DI")])
;; If a register gets allocated to LO, and we spill to memory, the reload
;; will include a move from LO to a GPR. Merge it into the multiplication
@@ -888,27 +899,27 @@ (define_peephole2
(clobber (match_dup 3))
(clobber (match_dup 0))])])
-(define_insn "mulsi3_internal"
- [(set (match_operand:SI 0 "register_operand" "=l")
- (mult:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (clobber (match_scratch:SI 3 "=h"))]
+(define_insn "mul<mode>3_internal"
+ [(set (match_operand:GPR 0 "register_operand" "=l")
+ (mult:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "register_operand" "d")))
+ (clobber (match_scratch:GPR 3 "=h"))]
"!TARGET_FIX_R4000"
- "mult\t%1,%2"
- [(set_attr "type" "imul")
- (set_attr "mode" "SI")])
+ "<d>mult\t%1,%2"
+ [(set_attr "type" "imul")
+ (set_attr "mode" "<MODE>")])
-(define_insn "mulsi3_r4000"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (mult:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))
- (clobber (match_scratch:SI 3 "=h"))
- (clobber (match_scratch:SI 4 "=l"))]
+(define_insn "mul<mode>3_r4000"
+ [(set (match_operand:GPR 0 "register_operand" "=d")
+ (mult:GPR (match_operand:GPR 1 "register_operand" "d")
+ (match_operand:GPR 2 "register_operand" "d")))
+ (clobber (match_scratch:GPR 3 "=h"))
+ (clobber (match_scratch:GPR 4 "=l"))]
"TARGET_FIX_R4000"
- "mult\t%1,%2\;mflo\t%0"
- [(set_attr "type" "imul")
- (set_attr "mode" "SI")
- (set_attr "length" "8")])
+ "<d>mult\t%1,%2\;mflo\t%0"
+ [(set_attr "type" "imul")
+ (set_attr "mode" "<MODE>")
+ (set_attr "length" "8")])
;; On the VR4120 and VR4130, it is better to use "mtlo $0; macc" instead
;; of "mult; mflo". They have the same latency, but the first form gives
@@ -1284,54 +1295,6 @@ (define_insn "*muls"
[(set_attr "type" "imul")
(set_attr "mode" "SI")])
-(define_expand "muldi3"
- [(set (match_operand:DI 0 "register_operand")
- (mult:DI (match_operand:DI 1 "register_operand")
- (match_operand:DI 2 "register_operand")))]
- "TARGET_64BIT"
-{
- if (GENERATE_MULT3_DI)
- emit_insn (gen_muldi3_mult3 (operands[0], operands[1], operands[2]));
- else if (!TARGET_FIX_R4000)
- emit_insn (gen_muldi3_internal (operands[0], operands[1], operands[2]));
- else
- emit_insn (gen_muldi3_r4000 (operands[0], operands[1], operands[2]));
- DONE;
-})
-
-(define_insn "muldi3_mult3"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (mult:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:DI 2 "register_operand" "d")))
- (clobber (match_scratch:DI 3 "=h"))
- (clobber (match_scratch:DI 4 "=l"))]
- "TARGET_64BIT && GENERATE_MULT3_DI"
- "dmult\t%0,%1,%2"
- [(set_attr "type" "imul")
- (set_attr "mode" "DI")])
-
-(define_insn "muldi3_internal"
- [(set (match_operand:DI 0 "register_operand" "=l")
- (mult:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:DI 2 "register_operand" "d")))
- (clobber (match_scratch:DI 3 "=h"))]
- "TARGET_64BIT && !TARGET_FIX_R4000"
- "dmult\t%1,%2"
- [(set_attr "type" "imul")
- (set_attr "mode" "DI")])
-
-(define_insn "muldi3_r4000"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (mult:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:DI 2 "register_operand" "d")))
- (clobber (match_scratch:DI 3 "=h"))
- (clobber (match_scratch:DI 4 "=l"))]
- "TARGET_64BIT && TARGET_FIX_R4000"
- "dmult\t%1,%2\;mflo\t%0"
- [(set_attr "type" "imul")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
-
;; ??? We could define a mulditi3 pattern when TARGET_64BIT.
(define_expand "mulsidi3"