Re: PATCH: First part of 64-bit Darwin support

[Stan Shebs <shebs at apple dot com>]

Andrew Pinski wrote:

> Some comments by quickly looking into your patch (late at night too).
>
> Shouldn't these be in altivec.md if not already right?
Theoretically, but as I recall, the generic patterns weren't kicking
in, probably because Darwin addressing patterns are different. What
I'd like to do is leave these in darwin.md for now, since that's
what's tested, and revisit as part of general reorg for Darwin
specific patterns.

Stan

> > + (define_split
> > +   [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" "")
> > +              (match_operand:DI 1 "short_cint_operand" "")))
> > +     (match_operand:V4SI 2 "register_operand" ""))
> > +    (clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
> > +   ""
> > +   [(set (match_dup 3) (plus:DI (match_dup 0) (match_dup 1)))
> > +    (set (mem:V4SI (match_dup 3))
> > +     (match_dup 2))]
> > +   "")
> > +
> > + (define_insn ""
> > +   [(set (mem:V4SI (plus:DI (match_operand:DI 0 "gpc_reg_operand" 
> > "b,r")
> > +              (match_operand:DI 1 "gpc_reg_operand" "r,b")))
> > +     (match_operand:V4SI 2 "register_operand" "v,v"))]
> > +   ""
> > +   "@
> > +    stvx %2,%0,%1
> > +    stvx %2,%1,%0"
> > +   [(set_attr "type" "vecstore")])
> > +
> > + (define_insn ""
> > +   [(set (mem:V4SI (match_operand:DI 0 "gpc_reg_operand" "r"))
> > +     (match_operand:V4SI 1 "register_operand" "v"))]
> > +   ""
> > +   "stvx %1,0,%0"
> > +   [(set_attr "type" "vecstore")])
> > +
> > + (define_split
> > +   [(set (match_operand:V4SI 0 "register_operand" "")
> > +     (mem:V4SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "")
> > +              (match_operand:DI 2 "short_cint_operand" ""))))
> > +    (clobber (match_operand:DI 3 "gpc_reg_operand" ""))]
> > +   ""
> > +   [(set (match_dup 3) (plus:DI (match_dup 1) (match_dup 2)))
> > +    (set (match_dup 0)
> > +     (mem:V4SI (match_dup 3)))]
> > +   "")
> > +
> > + (define_insn ""
> > +   [(set (match_operand:V4SI 0 "register_operand" "=v,v")
> > +     (mem:V4SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "b,r")
> > +              (match_operand:DI 2 "gpc_reg_operand" "r,b"))))]
> > +   ""
> > +   "@
> > +    lvx %0,%1,%2
> > +    lvx %0,%2,%1"
> > +   [(set_attr "type" "vecload")])
> > +
> > + (define_insn ""
> > +   [(set (match_operand:V4SI 0 "register_operand" "=v")
> > +         (mem:V4SI (match_operand:DI 1 "gpc_reg_operand" "r")))]
> > +   ""
> > +   "lvx %0,0,%1"
> > +   [(set_attr "type" "vecload")])
>
>
>
> Aren't these part of saveworld support which has not made it into 
> FSF's gcc or
> at least maybe done differently in the FSF's GCC:
>
> > + (define_insn "*save_fpregs_with_label_di"
> > +  [(match_parallel 0 "any_operand"
> > +                   [(clobber (match_operand:DI 1 "register_operand" 
> > "=l"))
> > +            (use (match_operand:DI 2 "call_operand" "s"))
> > +            (use (match_operand:DI 3 "" ""))
> > +            (set (match_operand:DF 4 "memory_operand" "=m")
> > +             (match_operand:DF 5 "gpc_reg_operand" "f"))])]
> > +  "TARGET_64BIT"
> > +  "*
> > + #if TARGET_MACHO
> > +   const char *picbase = machopic_function_base_name ();
> > +   operands[3] = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string 
> > (picbase, -1));
> > + #endif
> > +   return \"bl %z2\\n%3:\";
> > + "
> > +   [(set_attr "type" "branch")
> > +    (set_attr "length" "4")])
> > +
> > + (define_insn "*save_vregs_di"
> > +  [(match_parallel 0 "any_operand"
> > +                   [(clobber (match_operand:DI 1 "register_operand" 
> > "=l"))
> > +            (use (match_operand:DI 2 "call_operand" "s"))
> > +            (set (match_operand:V4SI 3 "any_operand" "=m")
> > +             (match_operand:V4SI 4 "register_operand" "v"))])]
> > +  "TARGET_64BIT"
> > +  "bl %z2"
> > +   [(set_attr "type" "branch")
> > +    (set_attr "length" "4")])
> > +
> > + (define_insn "*restore_vregs_di"
> > +  [(match_parallel 0 "any_operand"
> > +                   [(clobber (match_operand:DI 1 "register_operand" 
> > "=l"))
> > +            (use (match_operand:DI 2 "call_operand" "s"))
> > +            (clobber (match_operand:DI 3 "gpc_reg_operand" "=r"))
> > +            (set (match_operand:V4SI 4 "register_operand" "=v")
> > +             (match_operand:V4SI 5 "any_operand" "m"))])]
> > +  "TARGET_64BIT"
> > +  "bl %z2")
> > +
> > + (define_insn "*save_vregs_with_label_di"
> > +  [(match_parallel 0 "any_operand"
> > +                   [(clobber (match_operand:DI 1 "register_operand" 
> > "=l"))
> > +            (use (match_operand:DI 2 "call_operand" "s"))
> > +            (use (match_operand:DI 3 "" ""))
> > +            (set (match_operand:V4SI 4 "any_operand" "=m")
> > +             (match_operand:V4SI 5 "register_operand" "v"))])]
> > +  "TARGET_64BIT"
> > +  "*
> > + #if TARGET_MACHO
> > +   const char *picbase = machopic_function_base_name ();
> > +   operands[3] = gen_rtx_SYMBOL_REF (Pmode, ggc_alloc_string 
> > (picbase, -1));
> > + #endif
> > +   return \"bl %z2\\n%3:\";
> > + "
> > +   [(set_attr "type" "branch")
> > +    (set_attr "length" "4")])
>
> -- Pinski