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Re: [patch] MIPS/gcc: Revert removal of DImode shifts for 32-bittargets
- From: Nigel Stephens <nigel at mips dot com>
- To: "Maciej W. Rozycki" <macro at linux-mips dot org>
- Cc: Richard Sandiford <rsandifo at redhat dot com>, Ralf Baechle <ralf at linux-mips dot org>,Richard Henderson <rth at redhat dot com>, gcc-patches at gcc dot gnu dot org, linux-mips at linux-mips dot org
- Date: Wed, 04 Aug 2004 21:37:04 +0100
- Subject: Re: [patch] MIPS/gcc: Revert removal of DImode shifts for 32-bittargets
- Organization: MIPS Technologies
- References: <Pine.LNX.4.55.0407191648451.3667@jurand.ds.pg.gda.pl> <87hds49bmo.fsf@redhat.com> <Pine.LNX.4.55.0407191907300.3667@jurand.ds.pg.gda.pl> <20040719213801.GD14931@redhat.com> <Pine.LNX.4.55.0407201505330.14824@jurand.ds.pg.gda.pl> <20040723202703.GB30931@redhat.com> <20040723211232.GB5138@linux-mips.org> <Pine.LNX.4.58L.0407261325470.3873@blysk.ds.pg.gda.pl> <410E9E25.7080104@mips.com> <87acxcbxfl.fsf@redhat.com> <410F5964.3010109@mips.com> <876580bm2e.fsf@redhat.com> <410F60DF.9020400@mips.com> <Pine.LNX.4.58L.0408042123030.31930@blysk.ds.pg.gda.pl>
Maciej W. Rozycki wrote:
Here are my proposals I've referred to previously. Instruction counts
are 9, 9 and 10, respectively, as I've missed an additional instruction
required to handle shifts by 0 (or actually any multiples of 64).
IMHO handling a shift by zero correctly is important.
"not %1, %3\n\t"
"srlv %1, %L2, %1\n\t"
"srl %1, %1, 1\n\t"
Why not the shorter:
"neg %1, %3\n\t"
"srlv %1, %L2, %1\n\t"
And then in __ashrdi3:
"andi %1, %3, 0x20\n\t"
".set push\n\t"
".set noat\n\t"
"sra $1, %M2, 31\n\t"
"movn %L0, %M0, %1\n\t"
"movn %M0, $1, %1\n\t"
".set pop"
Cute, but I think that should be
"sra $1, %M0, 31\n\t"
(i.e %M0 not %M2)
Nigel