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Re: [patch] MIPS/gcc: Revert removal of DImode shifts for 32-bittargets
- From: Nigel Stephens <nigel at mips dot com>
- To: Richard Sandiford <rsandifo at redhat dot com>
- Cc: "Maciej W. Rozycki" <macro at linux-mips dot org>, Ralf Baechle <ralf at linux-mips dot org>,Richard Henderson <rth at redhat dot com>, gcc-patches at gcc dot gnu dot org, linux-mips at linux-mips dot org
- Date: Tue, 03 Aug 2004 10:54:39 +0100
- Subject: Re: [patch] MIPS/gcc: Revert removal of DImode shifts for 32-bittargets
- Organization: MIPS Technologies
- References: <Pine.LNX.4.55.0407191648451.3667@jurand.ds.pg.gda.pl> <87hds49bmo.fsf@redhat.com> <Pine.LNX.4.55.0407191907300.3667@jurand.ds.pg.gda.pl> <20040719213801.GD14931@redhat.com> <Pine.LNX.4.55.0407201505330.14824@jurand.ds.pg.gda.pl> <20040723202703.GB30931@redhat.com> <20040723211232.GB5138@linux-mips.org> <Pine.LNX.4.58L.0407261325470.3873@blysk.ds.pg.gda.pl> <410E9E25.7080104@mips.com> <87acxcbxfl.fsf@redhat.com> <410F5964.3010109@mips.com> <876580bm2e.fsf@redhat.com>
Richard Sandiford wrote:
I think we should only use define_expands if there's a truly
MIPS-specific feature in the expansion (as there is in the block
move stuff, for example, where we use left/right loads and stores).
Fair enough.
Now obviously I'm only guessing what insn sequence you're using,
OK, the simplest thing is for me to attach the define_insns. See below.
Note that there is one slightly controversial aspect of these sequences,
which is that they don't truncate the shift count, so a shift outside of
the range 0 to 63 will generate an "unusual" result. This didn't cause
any regression failures, and I believe that this is strictly speaking
acceptable for C, since a shift is undefined outside of this range - but
it could cause some "buggy" code to break. It wouldn't be hard to add an
extra mask with 0x3f if people were nervous about this - it's just that
I didn't have enough spare temp registers within the constraints of the
existing DImode patterns.
---- cut here ---
;; XXX Would be better done using define_expand, so it can be scheduled
;; XXX Note won't handle a shift count outside the range 0 - 63
(define_insn "ashldi3_internal_movc"
[(set (match_operand:DI 0 "register_operand" "=&d")
(ashift:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d")))
(clobber (match_operand:SI 3 "register_operand" "=&d"))]
"!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
&& ISA_HAS_CONDMOVE"
"subu\t%3,%.,%2\;\
sll\t%M0,%M1,%2\;\
srl\t%3,%L1,%3\;\
sll\t%L0,%L1,%2\;\
movz\t%3,%.,%2\;\
or\t%M0,%M0,%3\;\
and\t%3,%2,32\;\
movn\t%M0,%L0,%3\;\
movn\t%L0,%.,%3"
[(set_attr "type" "darith")
(set_attr "mode" "DI")
(set_attr "length" "36")])
;; Same length as before, but avoids branches
;; XXX Note won't handle a shift count outside the range 0 - 63
(define_insn "ashrdi3_internal_movc"
[(set (match_operand:DI 0 "register_operand" "=&d")
(ashiftrt:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d")))
(clobber (match_operand:SI 3 "register_operand" "=&d"))]
"!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
&& ISA_HAS_CONDMOVE"
"subu\t%3,%.,%2\;\
srl\t%L0,%L1,%2\;\
sll\t%3,%M1,%3\;\
sra\t%M0,%M1,%2\;\
movz\t%3,%.,%2\;\
or\t%L0,%L0,%3\;\
and\t%3,%2,32\;\
movn\t%L0,%M0,%3\;\
movn\t%M0,%.,%3\;\
movn\t%3,%L0,%3\;\
sra\t%3,%3,31\;\
or\t%M0,%M0,%3"
[(set_attr "type" "darith")
(set_attr "mode" "DI")
(set_attr "length" "48")])
;;; XXX Note won't handle a shift count outside the range 0 - 63
(define_insn "lshrdi3_internal_movc"
[(set (match_operand:DI 0 "register_operand" "=&d")
(lshiftrt:DI (match_operand:DI 1 "register_operand" "d")
(match_operand:SI 2 "register_operand" "d")))
(clobber (match_operand:SI 3 "register_operand" "=&d"))]
"!TARGET_64BIT && !TARGET_DEBUG_G_MODE && !TARGET_MIPS16
&& ISA_HAS_CONDMOVE"
"subu\t%3,%.,%2\;\
srl\t%L0,%L1,%2\;\
sll\t%3,%M1,%3\;\
srl\t%M0,%M1,%2\;\
movz\t%3,%.,%2\;\
or\t%L0,%L0,%3\;\
and\t%3,%2,32\;\
movn\t%L0,%M0,%3\;\
movn\t%M0,%.,%3"
[(set_attr "type" "darith")
(set_attr "mode" "DI")
(set_attr "length" "36")])