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Remove MIPS define_function_units
- From: Richard Sandiford <rsandifo at redhat dot com>
- To: Paolo Bonzini <bonzini at gnu dot org>, echristo at redhat dot com
- Cc: "gcc-patches at gcc dot gnu dot org" <gcc-patches at gcc dot gnu dot org>
- Date: Sat, 10 Jul 2004 13:52:59 +0100
- Subject: Remove MIPS define_function_units
- References: <40EF973A.2050008@gnu.org> <87zn68cnai.fsf@redhat.com>
Richard Sandiford <rsandifo@redhat.com> writes:
> BTW, as a general comment: I'm a bit worried that after a full transition
> to DFA, we're going to have lots of automata in the MIPS port. More than
> 30, at a guess. Each call to state_transition() will have to step every
> automata, even though only a handful of states are actually of any use.
...and I'd therefore like to take a different approach.
The old scheduler had just one set of units (alu, memory, adder, etc.)
and these units were used for all processors. For the reasons given
above, I don't think it's worth going away from that and creating
different cpu units and automata for each processor.
Also, there was a great deal of commonality between the schedulers.
I therefore don't think it's worth making every processor's .md file
specify something for every insn type. Instead, I'd like to use a
"generic" scheduler, placed at the end of the include list, and override
bits of it on a target-by-target basis.
So... the patch below extracts the old "default" scheduler: i.e. the
bits that were selected with (eq_attr "cpu" "!...."), or that had no
(eq_attr "cpu" ...) clause at all. This is the scheduler was used for
untuned processors like the 4kc, 5kc, etc. It goes in generic.md and
is included after all the other schedulers.
The patch then adds a new file for each processor that had been tuned.
These files override the parts of generic.md that don't apply.
This approach does mean that you have to look in two places if you want
to know how a particular processor is scheduled. I don't see that as
any great hardship, though, since its obvious at a glance which bits
have been overridden and which haven't.
IMO, the downside of having to look in two places is far outweighed by
the reduction in code duplication. Anyone who's actually interested in
the performance of these processors would probably be better off
starting from scratch anyway...
There were (at least) two major problems with the old description:
- fmadd instructions weren't handled, and were therefore treated like
single-cycle ALU operations. The patch treats them like fmul insns
instead.
I can't guarantee that the new behaviour is accurate for all processors,
but it's surely going to be an improvement over the single-cycle
assumption.
- The 4300.md description had:
(define_function_unit "imuldiv" 1 0
(and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt,frsqrt"))
^^^^
(and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
29 29)
(define_function_unit "imuldiv" 1 0
(and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt,frsqrt"))
^^^^
(and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
58 58)
which would clearly never be used. fdiv, fsqrt and frsqrt were therefore
treated as single-cycle ALU operations, just like fmadd. I'm assuming
the "and" should have been an "ior".
Tested by compiling C-torture at -O2 for each of the following processors:
4kc r3000 r3900 r4000 r4100 r4111 r4120 r4300 r4600
r4650 r5000 r6000 r8000
and comparing the assembly output before and after the patch. Because of
the problems mentioned above, there were differences in the output for
r4300, r5000 and r8000, the last two of which allow fmadd-type insns.
The output for the other processors didn't change.
As a sanity check, I tried treating fmadd and r4300 fdiv, fsqrt and
frsqrt insns as single-cycle ALU operations. There were then no changes
at all with the new description.
I'll run this through the usual bootstrap tests once the varargs stuff
has finished. Eric, is the patch OK with you?
Richard
* config/mips/mips.c (mips_use_dfa_pipeline_interface): Delete.
(TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE): Define to hook_int_void_1.
* config/mips/3000.md: Add copyright notice. Remove automota and
function units; use generic ones instead. Only define reservations
for things that are different from generic.md. Extend each clause
to include r3900.
* config/mips/{4000,4100,4300,4600,5000,6000,generic}.md: New files.
* config/mips/mips.md: Include them. Remove define_function_units.
(alu, imuldiv): New automata and units.
Index: config/mips/mips.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.c,v
retrieving revision 1.426
diff -c -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.426 mips.c
*** config/mips/mips.c 7 Jul 2004 19:24:28 -0000 1.426
--- config/mips/mips.c 10 Jul 2004 12:47:34 -0000
*************** static int mips_sched_reorder (FILE *, i
*** 283,289 ****
static int mips_variable_issue (FILE *, int, rtx, int);
static int mips_adjust_cost (rtx, rtx, rtx, int);
static int mips_issue_rate (void);
- static int mips_use_dfa_pipeline_interface (void);
static int mips_multipass_dfa_lookahead (void);
static void mips_init_libfuncs (void);
static void mips_setup_incoming_varargs (CUMULATIVE_ARGS *, enum machine_mode,
--- 283,288 ----
*************** #define TARGET_SCHED_ADJUST_COST mips_ad
*** 732,738 ****
#undef TARGET_SCHED_ISSUE_RATE
#define TARGET_SCHED_ISSUE_RATE mips_issue_rate
#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
! #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE mips_use_dfa_pipeline_interface
#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
mips_multipass_dfa_lookahead
--- 731,737 ----
#undef TARGET_SCHED_ISSUE_RATE
#define TARGET_SCHED_ISSUE_RATE mips_issue_rate
#undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
! #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1
#undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD
#define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \
mips_multipass_dfa_lookahead
*************** mips_issue_rate (void)
*** 9924,9952 ****
}
- /* Implements TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE. Return true for
- processors that have a DFA pipeline description. */
-
- static int
- mips_use_dfa_pipeline_interface (void)
- {
- switch (mips_tune)
- {
- case PROCESSOR_R3000:
- case PROCESSOR_R4130:
- case PROCESSOR_R5400:
- case PROCESSOR_R5500:
- case PROCESSOR_R7000:
- case PROCESSOR_R9000:
- case PROCESSOR_SB1:
- case PROCESSOR_SR71000:
- return true;
-
- default:
- return false;
- }
- }
-
/* Implements TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD. This should
be as wide as the scheduling freedom in the DFA. */
--- 9923,9928 ----
Index: config/mips/3000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/3000.md,v
retrieving revision 1.2
diff -c -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.2 3000.md
*** config/mips/3000.md 30 Jun 2004 17:27:54 -0000 1.2
--- config/mips/3000.md 10 Jul 2004 12:47:34 -0000
***************
*** 1,78 ****
! ;; DFA based pipeline description for the r3000
! ;; This is a special pipeline - this is also the default schedule and
! ;; so we need to schedule instructions that may not exist on the r2k/r3k.
!
! (define_automaton "r3k_alu,r3k_imuldiv")
!
! (define_cpu_unit "r3k_alu" "r3k_alu")
! (define_cpu_unit "r3k_imuldiv" "r3k_imuldiv")
!
! (define_insn_reservation "r3k_generic" 1
! (and (eq_attr "cpu" "r3000")
! (eq_attr "type" "unknown,prefetch,prefetchx,condmove,const,arith,
! shift,slt,clz,trap,multi,nop"))
! "r3k_alu")
(define_insn_reservation "r3k_load" 2
! (and (eq_attr "cpu" "r3000")
! (eq_attr "type" "load,fpload,fpidxload,xfer"))
! "r3k_alu")
!
! (define_insn_reservation "r3k_store" 1
! (and (eq_attr "cpu" "r3000")
! (eq_attr "type" "store,fpstore,fpidxstore"))
! "r3k_alu")
!
! (define_insn_reservation "r3k_branch" 1
! (and (eq_attr "cpu" "r3000")
! (eq_attr "type" "branch,jump,call"))
! "r3k_alu")
!
! (define_insn_reservation "r3k_hilo" 1
! (and (eq_attr "cpu" "r3000")
! (eq_attr "type" "mfhilo,mthilo"))
! "r3k_imuldiv*3")
(define_insn_reservation "r3k_imul" 12
! (and (eq_attr "cpu" "r3000")
(eq_attr "type" "imul,imadd"))
! "r3k_imuldiv*12")
(define_insn_reservation "r3k_idiv" 35
! (and (eq_attr "cpu" "r3000")
(eq_attr "type" "idiv"))
! "r3k_imuldiv*35")
(define_insn_reservation "r3k_fmove" 1
! (and (eq_attr "cpu" "r3000")
! (eq_attr "type" "fabs,fneg,fmove,fcvt"))
! "r3k_alu")
(define_insn_reservation "r3k_fadd" 2
! (and (eq_attr "cpu" "r3000")
(eq_attr "type" "fcmp,fadd"))
! "r3k_alu")
(define_insn_reservation "r3k_fmul_single" 4
! (and (eq_attr "cpu" "r3000")
(and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "SF")))
! "r3k_alu")
(define_insn_reservation "r3k_fmul_double" 5
! (and (eq_attr "cpu" "r3000")
(and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "DF")))
! "r3k_alu")
(define_insn_reservation "r3k_fdiv_single" 12
! (and (eq_attr "cpu" "r3000")
! (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
(eq_attr "mode" "SF")))
! "r3k_alu")
(define_insn_reservation "r3k_fdiv_double" 19
! (and (eq_attr "cpu" "r3000")
! (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
(eq_attr "mode" "DF")))
! "r3k_alu")
--- 1,72 ----
! ;; R3000 and TX39 pipeline description.
! ;; Copyright (C) 2004 Free Software Foundation, Inc.
! ;;
! ;; This file is part of GCC.
!
! ;; GCC is free software; you can redistribute it and/or modify it
! ;; under the terms of the GNU General Public License as published
! ;; by the Free Software Foundation; either version 2, or (at your
! ;; option) any later version.
!
! ;; GCC is distributed in the hope that it will be useful, but WITHOUT
! ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
! ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
! ;; License for more details.
!
! ;; You should have received a copy of the GNU General Public License
! ;; along with GCC; see the file COPYING. If not, write to the
! ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
! ;; MA 02111-1307, USA.
!
!
! ;; This file overrides parts of generic.md. It is derived from the
! ;; old define_function_unit description.
(define_insn_reservation "r3k_load" 2
! (and (eq_attr "cpu" "r3000,r3900")
! (eq_attr "type" "load,fpload,fpidxload"))
! "alu")
(define_insn_reservation "r3k_imul" 12
! (and (eq_attr "cpu" "r3000,r3900")
(eq_attr "type" "imul,imadd"))
! "imuldiv*12")
(define_insn_reservation "r3k_idiv" 35
! (and (eq_attr "cpu" "r3000,r3900")
(eq_attr "type" "idiv"))
! "imuldiv*35")
(define_insn_reservation "r3k_fmove" 1
! (and (eq_attr "cpu" "r3000,r3900")
! (eq_attr "type" "fabs,fneg,fmove"))
! "alu")
(define_insn_reservation "r3k_fadd" 2
! (and (eq_attr "cpu" "r3000,r3900")
(eq_attr "type" "fcmp,fadd"))
! "alu")
(define_insn_reservation "r3k_fmul_single" 4
! (and (eq_attr "cpu" "r3000,r3900")
(and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "SF")))
! "alu")
(define_insn_reservation "r3k_fmul_double" 5
! (and (eq_attr "cpu" "r3000,r3900")
(and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "DF")))
! "alu")
(define_insn_reservation "r3k_fdiv_single" 12
! (and (eq_attr "cpu" "r3000,r3900")
! (and (eq_attr "type" "fdiv")
(eq_attr "mode" "SF")))
! "alu")
(define_insn_reservation "r3k_fdiv_double" 19
! (and (eq_attr "cpu" "r3000,r3900")
! (and (eq_attr "type" "fdiv")
(eq_attr "mode" "DF")))
! "alu")
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.250
diff -c -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.250 mips.md
*** config/mips/mips.md 7 Jul 2004 19:24:31 -0000 1.250
--- config/mips/mips.md 10 Jul 2004 12:47:35 -0000
*************** (define_delay (and (eq_attr "type" "call
*** 313,644 ****
(nil)
(nil)])
! ;; .........................
! ;;
! ;; Functional units
! ;;
! ;; .........................
! ; (define_function_unit NAME MULTIPLICITY SIMULTANEITY
! ; TEST READY-DELAY ISSUE-DELAY [CONFLICT-LIST])
- ;; Make the default case (PROCESSOR_DEFAULT) handle the worst case
-
- (define_function_unit "memory" 1 0
- (and (eq_attr "type" "load,fpload,fpidxload")
- (eq_attr "cpu" "!r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
- 3 0)
-
- (define_function_unit "memory" 1 0
- (and (eq_attr "type" "load,fpload,fpidxload")
- (eq_attr "cpu" "r3900,r4600,r4650,r4100,r4120,r4300,r5000"))
- 2 0)
-
- (define_function_unit "memory" 1 0
- (eq_attr "type" "store,fpstore,fpidxstore")
- 1 0)
-
- (define_function_unit "memory" 1 0 (eq_attr "type" "xfer") 2 0)
-
- (define_function_unit "imuldiv" 1 0
- (eq_attr "type" "mthilo,mfhilo")
- 1 3)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd")
- (eq_attr "cpu" "!r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000"))
- 17 17)
-
- ;; On them mips16, we want to stronly discourage a mult from appearing
- ;; after an mflo, since that requires explicit nop instructions. We
- ;; do this by pretending that mflo ties up the function unit for long
- ;; enough that the scheduler will ignore load stalls and the like when
- ;; selecting instructions to between the two instructions.
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "mfhilo") (ne (symbol_ref "TARGET_MIPS16") (const_int 0)))
- 1 5)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd") (eq_attr "cpu" "r3900"))
- 12 12)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd") (eq_attr "cpu" "r4000,r4600"))
- 10 10)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd") (eq_attr "cpu" "r4650"))
- 4 4)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd")
- (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100,r4120")))
- 1 1)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100,r4120")))
- 4 4)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd")
- (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300,r5000")))
- 5 5)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300")))
- 8 8)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "imul,imadd")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000")))
- 9 9)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (eq_attr "cpu" "!r3900,r4000,r4600,r4650,r4100,r4120,r4300,r5000"))
- 38 38)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv") (eq_attr "cpu" "r3900"))
- 35 35)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4600"))
- 42 42)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4650"))
- 36 36)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv") (eq_attr "cpu" "r4000"))
- 69 69)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4100,r4120")))
- 35 35)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4100,r4120")))
- 67 67)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "SI") (eq_attr "cpu" "r4300")))
- 37 37)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r4300")))
- 69 69)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "SI") (eq_attr "cpu" "r5000")))
- 36 36)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "idiv")
- (and (eq_attr "mode" "DI") (eq_attr "cpu" "r5000")))
- 68 68)
-
- ;; The R4300 does *NOT* have a separate Floating Point Unit, instead
- ;; the FP hardware is part of the normal ALU circuitry. This means FP
- ;; instructions affect the pipe-line, and no functional unit
- ;; parallelism can occur on R4300 processors. To force GCC into coding
- ;; for only a single functional unit, we force the R4300 FP
- ;; instructions to be processed in the "imuldiv" unit.
-
- (define_function_unit "adder" 1 1
- (and (eq_attr "type" "fcmp") (eq_attr "cpu" "!r3900,r6000,r4300,r5000"))
- 3 0)
-
- (define_function_unit "adder" 1 1
- (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r3900,r6000"))
- 2 0)
-
- (define_function_unit "adder" 1 1
- (and (eq_attr "type" "fcmp") (eq_attr "cpu" "r5000"))
- 1 0)
-
- (define_function_unit "adder" 1 1
- (and (eq_attr "type" "fadd") (eq_attr "cpu" "!r3900,r6000,r4300"))
- 4 0)
-
- (define_function_unit "adder" 1 1
- (and (eq_attr "type" "fadd") (eq_attr "cpu" "r3900"))
- 2 0)
-
- (define_function_unit "adder" 1 1
- (and (eq_attr "type" "fadd") (eq_attr "cpu" "r6000"))
- 3 0)
-
- (define_function_unit "adder" 1 1
- (and (eq_attr "type" "fabs,fneg,fmove")
- (eq_attr "cpu" "!r3900,r4600,r4650,r4300,r5000"))
- 2 0)
-
- (define_function_unit "adder" 1 1
- (and (eq_attr "type" "fabs,fneg,fmove") (eq_attr "cpu" "r3900,r4600,r4650,r5000"))
- 1 0)
-
- (define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "SF")
- (eq_attr "cpu" "!r3900,r6000,r4600,r4650,r4300,r5000")))
- 7 0)
-
- (define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3900,r5000")))
- 4 0)
-
- (define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
- 5 0)
-
- (define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
- 8 0)
-
- (define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r3900,r6000,r4300,r5000")))
- 8 0)
-
- (define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3900,r5000")))
- 5 0)
-
- (define_function_unit "mult" 1 1
- (and (eq_attr "type" "fmul")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
- 6 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "SF")
- (eq_attr "cpu" "!r3900,r6000,r4600,r4650,r4300,r5000")))
- 23 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r3900")))
- 12 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r6000")))
- 15 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
- 32 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
- 21 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "DF")
- (eq_attr "cpu" "!r3900,r6000,r4600,r4650,r4300")))
- 36 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r3900")))
- 19 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r6000")))
- 16 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fdiv")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650")))
- 61 0)
-
- ;;; ??? Is this number right?
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt,frsqrt")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000")))
- 54 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt,frsqrt")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4600,r4650")))
- 31 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt,frsqrt")
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r5000")))
- 21 0)
-
- ;;; ??? Is this number right?
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt,frsqrt")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "!r4600,r4650,r4300,r5000")))
- 112 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt,frsqrt")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4600,r4650")))
- 60 0)
-
- (define_function_unit "divide" 1 1
- (and (eq_attr "type" "fsqrt,frsqrt")
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r5000")))
- 36 0)
-
- ;; R4300 FP instruction classes treated as part of the "imuldiv"
- ;; functional unit:
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "fadd") (eq_attr "cpu" "r4300"))
- 3 3)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "fcmp,fabs,fneg,fmove") (eq_attr "cpu" "r4300"))
- 1 1)
-
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "fmul") (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
- 5 5)
- (define_function_unit "imuldiv" 1 0
- (and (eq_attr "type" "fmul") (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
- 8 8)
-
- (define_function_unit "imuldiv" 1 0
- (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt,frsqrt"))
- (and (eq_attr "mode" "SF") (eq_attr "cpu" "r4300")))
- 29 29)
- (define_function_unit "imuldiv" 1 0
- (and (and (eq_attr "type" "fdiv") (eq_attr "type" "fsqrt,frsqrt"))
- (and (eq_attr "mode" "DF") (eq_attr "cpu" "r4300")))
- 58 58)
-
;; Include scheduling descriptions.
(include "3000.md")
(include "4130.md")
(include "5400.md")
(include "5500.md")
(include "7000.md")
(include "9000.md")
(include "sb1.md")
(include "sr71k.md")
;;
;; ....................
--- 313,342 ----
(nil)
(nil)])
! ;; These automota are used by generic.md and the processor-specific files
! ;; that override it.
! (define_automaton "alu,imuldiv")
! (define_cpu_unit "alu" "alu")
! (define_cpu_unit "imuldiv" "imuldiv")
;; Include scheduling descriptions.
(include "3000.md")
+ (include "4000.md")
+ (include "4100.md")
(include "4130.md")
+ (include "4300.md")
+ (include "4600.md")
+ (include "5000.md")
(include "5400.md")
(include "5500.md")
+ (include "6000.md")
(include "7000.md")
(include "9000.md")
(include "sb1.md")
(include "sr71k.md")
+ (include "generic.md")
;;
;; ....................
*** /dev/null Fri Apr 23 00:21:55 2004
--- config/mips/4000.md Sat Jul 10 13:03:29 2004
***************
*** 0 ****
--- 1,33 ----
+ ;; R4000 pipeline description.
+ ;; Copyright (C) 2004 Free Software Foundation, Inc.
+ ;;
+ ;; This file is part of GCC.
+
+ ;; GCC is free software; you can redistribute it and/or modify it
+ ;; under the terms of the GNU General Public License as published
+ ;; by the Free Software Foundation; either version 2, or (at your
+ ;; option) any later version.
+
+ ;; GCC is distributed in the hope that it will be useful, but WITHOUT
+ ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ ;; License for more details.
+
+ ;; You should have received a copy of the GNU General Public License
+ ;; along with GCC; see the file COPYING. If not, write to the
+ ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
+ ;; MA 02111-1307, USA.
+
+
+ ;; This file overrides parts of generic.md. It is derived from the
+ ;; old define_function_unit description.
+
+ (define_insn_reservation "r4k_imul" 10
+ (and (eq_attr "cpu" "r4000")
+ (eq_attr "type" "imul,imadd"))
+ "imuldiv*10")
+
+ (define_insn_reservation "r4k_idiv" 69
+ (and (eq_attr "cpu" "r4000")
+ (eq_attr "type" "idiv"))
+ "imuldiv*69")
*** /dev/null Fri Apr 23 00:21:55 2004
--- config/mips/4100.md Sat Jul 10 13:03:52 2004
***************
*** 0 ****
--- 1,52 ----
+ ;; VR4100 and VR4120 pipeline description.
+ ;; Copyright (C) 2004 Free Software Foundation, Inc.
+ ;;
+ ;; This file is part of GCC.
+
+ ;; GCC is free software; you can redistribute it and/or modify it
+ ;; under the terms of the GNU General Public License as published
+ ;; by the Free Software Foundation; either version 2, or (at your
+ ;; option) any later version.
+
+ ;; GCC is distributed in the hope that it will be useful, but WITHOUT
+ ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ ;; License for more details.
+
+ ;; You should have received a copy of the GNU General Public License
+ ;; along with GCC; see the file COPYING. If not, write to the
+ ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
+ ;; MA 02111-1307, USA.
+
+
+ ;; This file overrides parts of generic.md. It is derived from the
+ ;; old define_function_unit description.
+
+ (define_insn_reservation "r4100_load" 2
+ (and (eq_attr "cpu" "r4100,r4120")
+ (eq_attr "type" "load,fpload,fpidxload,xfer"))
+ "alu")
+
+ (define_insn_reservation "r4100_imul_si" 1
+ (and (eq_attr "cpu" "r4100,r4120")
+ (and (eq_attr "type" "imul,imadd")
+ (eq_attr "mode" "SI")))
+ "imuldiv")
+
+ (define_insn_reservation "r4100_imul_di" 4
+ (and (eq_attr "cpu" "r4100,r4120")
+ (and (eq_attr "type" "imul,imadd")
+ (eq_attr "mode" "DI")))
+ "imuldiv*4")
+
+ (define_insn_reservation "r4100_idiv_si" 35
+ (and (eq_attr "cpu" "r4100,r4120")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "SI")))
+ "imuldiv*35")
+
+ (define_insn_reservation "r4100_idiv_di" 67
+ (and (eq_attr "cpu" "r4100,r4120")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "DI")))
+ "imuldiv*67")
*** /dev/null Fri Apr 23 00:21:55 2004
--- config/mips/4300.md Sat Jul 10 13:04:08 2004
***************
*** 0 ****
--- 1,86 ----
+ ;; VR4300 pipeline description.
+ ;; Copyright (C) 2004 Free Software Foundation, Inc.
+ ;;
+ ;; This file is part of GCC.
+
+ ;; GCC is free software; you can redistribute it and/or modify it
+ ;; under the terms of the GNU General Public License as published
+ ;; by the Free Software Foundation; either version 2, or (at your
+ ;; option) any later version.
+
+ ;; GCC is distributed in the hope that it will be useful, but WITHOUT
+ ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ ;; License for more details.
+
+ ;; You should have received a copy of the GNU General Public License
+ ;; along with GCC; see the file COPYING. If not, write to the
+ ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
+ ;; MA 02111-1307, USA.
+
+
+ ;; This file overrides parts of generic.md. It is derived from the
+ ;; old define_function_unit description.
+
+ (define_insn_reservation "r4300_load" 2
+ (and (eq_attr "cpu" "r4300")
+ (eq_attr "type" "load,fpload,fpidxload,xfer"))
+ "alu")
+
+ (define_insn_reservation "r4300_imul_si" 5
+ (and (eq_attr "cpu" "r4300")
+ (and (eq_attr "type" "imul,imadd")
+ (eq_attr "mode" "SI")))
+ "imuldiv*5")
+
+ (define_insn_reservation "r4300_imul_di" 8
+ (and (eq_attr "cpu" "r4300")
+ (and (eq_attr "type" "imul,imadd")
+ (eq_attr "mode" "DI")))
+ "imuldiv*8")
+
+ (define_insn_reservation "r4300_idiv_si" 37
+ (and (eq_attr "cpu" "r4300")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "SI")))
+ "imuldiv*37")
+
+ (define_insn_reservation "r4300_idiv_di" 69
+ (and (eq_attr "cpu" "r4300")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "DI")))
+ "imuldiv*69")
+
+ (define_insn_reservation "r4300_fmove" 1
+ (and (eq_attr "cpu" "r4300")
+ (eq_attr "type" "fcmp,fabs,fneg,fmove"))
+ "imuldiv")
+
+ (define_insn_reservation "r4300_fadd" 3
+ (and (eq_attr "cpu" "r4300")
+ (eq_attr "type" "fadd"))
+ "imuldiv*3")
+
+ (define_insn_reservation "r4300_fmul_single" 5
+ (and (eq_attr "cpu" "r4300")
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "SF")))
+ "imuldiv*5")
+
+ (define_insn_reservation "r4300_fmul_double" 8
+ (and (eq_attr "cpu" "r4300")
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "DF")))
+ "imuldiv*8")
+
+ (define_insn_reservation "r4300_fdiv_single" 29
+ (and (eq_attr "cpu" "r4300")
+ (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
+ (eq_attr "mode" "SF")))
+ "imuldiv*29")
+
+ (define_insn_reservation "r4300_fdiv_double" 58
+ (and (eq_attr "cpu" "r4300")
+ (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
+ (eq_attr "mode" "DF")))
+ "imuldiv*58")
*** /dev/null Fri Apr 23 00:21:55 2004
--- config/mips/4600.md Sat Jul 10 13:05:32 2004
***************
*** 0 ****
--- 1,88 ----
+ ;; R4600 and R4650 pipeline description.
+ ;; Copyright (C) 2004 Free Software Foundation, Inc.
+ ;;
+ ;; This file is part of GCC.
+
+ ;; GCC is free software; you can redistribute it and/or modify it
+ ;; under the terms of the GNU General Public License as published
+ ;; by the Free Software Foundation; either version 2, or (at your
+ ;; option) any later version.
+
+ ;; GCC is distributed in the hope that it will be useful, but WITHOUT
+ ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ ;; License for more details.
+
+ ;; You should have received a copy of the GNU General Public License
+ ;; along with GCC; see the file COPYING. If not, write to the
+ ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
+ ;; MA 02111-1307, USA.
+
+
+ ;; This file overrides parts of generic.md. It is derived from the
+ ;; old define_function_unit description.
+ ;;
+ ;; We handle the R4600 and R4650 in much the same way. The only difference
+ ;; is in the integer multiplication and division costs.
+
+ (define_insn_reservation "r4600_imul" 10
+ (and (eq_attr "cpu" "r4600")
+ (eq_attr "type" "imul,imadd"))
+ "imuldiv*10")
+
+ (define_insn_reservation "r4600_idiv" 42
+ (and (eq_attr "cpu" "r4600")
+ (eq_attr "type" "idiv"))
+ "imuldiv*42")
+
+
+ (define_insn_reservation "r4650_imul" 4
+ (and (eq_attr "cpu" "r4650")
+ (eq_attr "type" "imul,imadd"))
+ "imuldiv*4")
+
+ (define_insn_reservation "r4650_idiv" 36
+ (and (eq_attr "cpu" "r4650")
+ (eq_attr "type" "idiv"))
+ "imuldiv*36")
+
+
+ (define_insn_reservation "r4600_load" 2
+ (and (eq_attr "cpu" "r4600,r4650")
+ (eq_attr "type" "load,fpload,fpidxload"))
+ "alu")
+
+ (define_insn_reservation "r4600_fmove" 1
+ (and (eq_attr "cpu" "r4600,r4650")
+ (eq_attr "type" "fabs,fneg,fmove"))
+ "alu")
+
+ (define_insn_reservation "r4600_fmul_single" 8
+ (and (eq_attr "cpu" "r4600,r4650")
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "SF")))
+ "alu")
+
+ (define_insn_reservation "r4600_fdiv_single" 32
+ (and (eq_attr "cpu" "r4600,r4650")
+ (and (eq_attr "type" "fdiv")
+ (eq_attr "mode" "SF")))
+ "alu")
+
+ (define_insn_reservation "r4600_fdiv_double" 61
+ (and (eq_attr "cpu" "r4600,r4650")
+ (and (eq_attr "type" "fdiv")
+ (eq_attr "mode" "DF")))
+ "alu")
+
+ (define_insn_reservation "r4600_fsqrt_single" 31
+ (and (eq_attr "cpu" "r4600,r4650")
+ (and (eq_attr "type" "fsqrt,frsqrt")
+ (eq_attr "mode" "SF")))
+ "alu")
+
+ (define_insn_reservation "r4600_fsqrt_double" 60
+ (and (eq_attr "cpu" "r4600,r4650")
+ (and (eq_attr "type" "fsqrt,frsqrt")
+ (eq_attr "mode" "DF")))
+ "alu")
*** /dev/null Fri Apr 23 00:21:55 2004
--- config/mips/5000.md Sat Jul 10 13:14:39 2004
***************
*** 0 ****
--- 1,81 ----
+ ;; VR5000 pipeline description.
+ ;; Copyright (C) 2004 Free Software Foundation, Inc.
+ ;;
+ ;; This file is part of GCC.
+
+ ;; GCC is free software; you can redistribute it and/or modify it
+ ;; under the terms of the GNU General Public License as published
+ ;; by the Free Software Foundation; either version 2, or (at your
+ ;; option) any later version.
+
+ ;; GCC is distributed in the hope that it will be useful, but WITHOUT
+ ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ ;; License for more details.
+
+ ;; You should have received a copy of the GNU General Public License
+ ;; along with GCC; see the file COPYING. If not, write to the
+ ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
+ ;; MA 02111-1307, USA.
+
+
+ ;; This file overrides parts of generic.md. It is derived from the
+ ;; old define_function_unit description.
+
+ (define_insn_reservation "r5k_load" 2
+ (and (eq_attr "cpu" "r5000")
+ (eq_attr "type" "load,fpload,fpidxload,xfer"))
+ "alu")
+
+ (define_insn_reservation "r5k_imul_si" 5
+ (and (eq_attr "cpu" "r5000")
+ (and (eq_attr "type" "imul,imadd")
+ (eq_attr "mode" "SI")))
+ "imuldiv*5")
+
+ (define_insn_reservation "r5k_imul_di" 9
+ (and (eq_attr "cpu" "r5000")
+ (and (eq_attr "type" "imul,imadd")
+ (eq_attr "mode" "DI")))
+ "imuldiv*9")
+
+ (define_insn_reservation "r5k_idiv_si" 36
+ (and (eq_attr "cpu" "r5000")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "SI")))
+ "imuldiv*36")
+
+ (define_insn_reservation "r5k_idiv_di" 68
+ (and (eq_attr "cpu" "r5000")
+ (and (eq_attr "type" "idiv")
+ (eq_attr "mode" "DI")))
+ "imuldiv*68")
+
+ (define_insn_reservation "r5k_fmove" 1
+ (and (eq_attr "cpu" "r5000")
+ (eq_attr "type" "fcmp,fabs,fneg,fmove"))
+ "alu")
+
+ (define_insn_reservation "r5k_fmul_single" 4
+ (and (eq_attr "cpu" "r5000")
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "SF")))
+ "alu")
+
+ (define_insn_reservation "r5k_fmul_double" 5
+ (and (eq_attr "cpu" "r5000")
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "DF")))
+ "alu")
+
+ (define_insn_reservation "r5k_fdiv_single" 21
+ (and (eq_attr "cpu" "r5000")
+ (and (eq_attr "type" "fdiv,fsqrt,frsqrt")
+ (eq_attr "mode" "SF")))
+ "alu")
+
+ (define_insn_reservation "r5k_fsqrt_double" 36
+ (and (eq_attr "cpu" "r5000")
+ (and (eq_attr "type" "fsqrt,frsqrt")
+ (eq_attr "mode" "DF")))
+ "alu")
*** /dev/null Fri Apr 23 00:21:55 2004
--- config/mips/6000.md Sat Jul 10 13:06:05 2004
***************
*** 0 ****
--- 1,57 ----
+ ;; R6000 pipeline description.
+ ;; Copyright (C) 2004 Free Software Foundation, Inc.
+ ;;
+ ;; This file is part of GCC.
+
+ ;; GCC is free software; you can redistribute it and/or modify it
+ ;; under the terms of the GNU General Public License as published
+ ;; by the Free Software Foundation; either version 2, or (at your
+ ;; option) any later version.
+
+ ;; GCC is distributed in the hope that it will be useful, but WITHOUT
+ ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ ;; License for more details.
+
+ ;; You should have received a copy of the GNU General Public License
+ ;; along with GCC; see the file COPYING. If not, write to the
+ ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
+ ;; MA 02111-1307, USA.
+
+
+ ;; This file overrides parts of generic.md. It is derived from the
+ ;; old define_function_unit description.
+
+ (define_insn_reservation "r6k_fcmp" 2
+ (and (eq_attr "cpu" "r6000")
+ (eq_attr "type" "fcmp"))
+ "alu")
+
+ (define_insn_reservation "r6k_fadd" 3
+ (and (eq_attr "cpu" "r6000")
+ (eq_attr "type" "fadd"))
+ "alu")
+
+ (define_insn_reservation "r6k_fmul_single" 5
+ (and (eq_attr "cpu" "r6000")
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "SF")))
+ "alu")
+
+ (define_insn_reservation "r6k_fmul_double" 6
+ (and (eq_attr "cpu" "r6000")
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "DF")))
+ "alu")
+
+ (define_insn_reservation "r6k_fdiv_single" 15
+ (and (eq_attr "cpu" "r6000")
+ (and (eq_attr "type" "fdiv")
+ (eq_attr "mode" "SF")))
+ "alu")
+
+ (define_insn_reservation "r6k_fdiv_double" 16
+ (and (eq_attr "cpu" "r6000")
+ (and (eq_attr "type" "fdiv")
+ (eq_attr "mode" "DF")))
+ "alu")
*** /dev/null Fri Apr 23 00:21:55 2004
--- config/mips/generic.md Sat Jul 10 12:55:06 2004
***************
*** 0 ****
--- 1,102 ----
+ ;; Generic DFA-based pipeline description for MIPS targets
+ ;; Copyright (C) 2004 Free Software Foundation, Inc.
+ ;;
+ ;; This file is part of GCC.
+
+ ;; GCC is free software; you can redistribute it and/or modify it
+ ;; under the terms of the GNU General Public License as published
+ ;; by the Free Software Foundation; either version 2, or (at your
+ ;; option) any later version.
+
+ ;; GCC is distributed in the hope that it will be useful, but WITHOUT
+ ;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ ;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
+ ;; License for more details.
+
+ ;; You should have received a copy of the GNU General Public License
+ ;; along with GCC; see the file COPYING. If not, write to the
+ ;; Free Software Foundation, 59 Temple Place - Suite 330, Boston,
+ ;; MA 02111-1307, USA.
+
+
+ ;; This file is derived from the old define_function_unit description.
+ ;; Each reservation can be overridden on a processor-by-processor basis.
+
+ (define_insn_reservation "generic_alu" 1
+ (eq_attr "type" "unknown,prefetch,prefetchx,condmove,const,arith,
+ shift,slt,clz,trap,multi,nop")
+ "alu")
+
+ (define_insn_reservation "generic_load" 3
+ (eq_attr "type" "load,fpload,fpidxload")
+ "alu")
+
+ (define_insn_reservation "generic_store" 1
+ (eq_attr "type" "store,fpstore,fpidxstore")
+ "alu")
+
+ (define_insn_reservation "generic_xfer" 2
+ (eq_attr "type" "xfer")
+ "alu")
+
+ (define_insn_reservation "generic_branch" 1
+ (eq_attr "type" "branch,jump,call")
+ "alu")
+
+ (define_insn_reservation "generic_hilo" 1
+ (eq_attr "type" "mfhilo,mthilo")
+ "imuldiv*3")
+
+ (define_insn_reservation "generic_imul" 17
+ (eq_attr "type" "imul,imadd")
+ "imuldiv*17")
+
+ (define_insn_reservation "generic_idiv" 38
+ (eq_attr "type" "idiv")
+ "imuldiv*38")
+
+ (define_insn_reservation "generic_fcvt" 1
+ (eq_attr "type" "fcvt")
+ "alu")
+
+ (define_insn_reservation "generic_fmove" 2
+ (eq_attr "type" "fabs,fneg,fmove")
+ "alu")
+
+ (define_insn_reservation "generic_fcmp" 3
+ (eq_attr "type" "fcmp")
+ "alu")
+
+ (define_insn_reservation "generic_fadd" 4
+ (eq_attr "type" "fadd")
+ "alu")
+
+ (define_insn_reservation "generic_fmul_single" 7
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "SF"))
+ "alu")
+
+ (define_insn_reservation "generic_fmul_double" 8
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "DF"))
+ "alu")
+
+ (define_insn_reservation "generic_fdiv_single" 23
+ (and (eq_attr "type" "fdiv")
+ (eq_attr "mode" "SF"))
+ "alu")
+
+ (define_insn_reservation "generic_fdiv_double" 36
+ (and (eq_attr "type" "fdiv")
+ (eq_attr "mode" "DF"))
+ "alu")
+
+ (define_insn_reservation "generic_fsqrt_single" 54
+ (and (eq_attr "type" "fsqrt,frsqrt")
+ (eq_attr "mode" "SF"))
+ "alu")
+
+ (define_insn_reservation "generic_fsqrt_double" 112
+ (and (eq_attr "type" "fsqrt,frsqrt")
+ (eq_attr "mode" "DF"))
+ "alu")