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It is not obvious why __float128 support, requiring XMM registers, was designated for x86-64 only (but still partly enabled for x86). This patch brings it to the same (incomplete) level of support for both 32 and 64 bits. bootstrapped and tested on i686-pc-linux-gnu. Jan 2004-07-08 Jan Beulich <jbeulich@novell.com> * config/i386/i386.c (ix86_function_regparm): Don't call cgraph_local_info for libcalls, which dont provide a FUNCTION_DECL. (function_arg): Also pass TFmode through XMM registers. (ix86_return_in_memory): Don't return TFmode in memory when SSE is enabled. (ix86_value_regno): Consolidate check for returning in xmm0, and move it ahead of the check for floating point modes. (ix86_init_mmx_sse_builtins): Set up __float128 only when SSE is enabled. * config/i386/i386.md (movtf): Also allow in 32-bit mode when SSE is enabled. (*movtf_internal): New. --- /home/jbeulich/src/gcc/mainline/2004-07-05.10.09/gcc/config/i386/i386.c 2004-07-02 15:20:42.000000000 +0200 +++ 2004-07-05.10.09/gcc/config/i386/i386.c 2004-07-07 15:39:12.884303648 +0200 @@ -1777,7 +1777,8 @@ } /* Use register calling convention for local functions when possible. */ - if (!TARGET_64BIT && !user_convention && decl + if (!TARGET_64BIT && !user_convention + && decl && TREE_CODE (decl) == FUNCTION_DECL && flag_unit_at_a_time && !profile_flag) { struct cgraph_local_info *i = cgraph_local_info (decl); @@ -2663,6 +2664,7 @@ } break; case TImode: + case TFmode: case V16QImode: case V8HImode: case V4SImode: @@ -2891,7 +2893,7 @@ if (MS_AGGREGATE_RETURN && AGGREGATE_TYPE_P (type) && size <= 8) return 0; - if (VECTOR_MODE_P (mode) || mode == TImode) + if (VECTOR_MODE_P (mode) || mode == TImode || mode == TFmode) { /* User-created vectors small enough to fit in EAX. */ if (size < 8) @@ -2980,13 +2982,13 @@ static int ix86_value_regno (enum machine_mode mode) { - /* Floating point return values in %st(0). */ - if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_FLOAT_RETURNS_IN_80387) - return FIRST_FLOAT_REG; /* 16-byte vector modes in %xmm0. See ix86_return_in_memory for where we prevent this case when sse is not available. */ - if (mode == TImode || (VECTOR_MODE_P (mode) && GET_MODE_SIZE (mode) == 16)) + if (SSE_REG_MODE_P (mode)) return FIRST_SSE_REG; + /* Floating point return values in %st(0). */ + if (GET_MODE_CLASS (mode) == MODE_FLOAT && TARGET_FLOAT_RETURNS_IN_80387) + return FIRST_FLOAT_REG; /* Everything else in %eax. */ return 0; } @@ -13317,9 +13319,6 @@ tree v2di_ftype_v2di = build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE); - tree float80_type; - tree float128_type; - /* The __float80 type. */ if (TYPE_MODE (long_double_type_node) == XFmode) (*lang_hooks.types.register_builtin_type) (long_double_type_node, @@ -13327,16 +13326,21 @@ else { /* The __float80 type. */ - float80_type = make_node (REAL_TYPE); + tree float80_type = make_node (REAL_TYPE); + TYPE_PRECISION (float80_type) = 96; layout_type (float80_type); (*lang_hooks.types.register_builtin_type) (float80_type, "__float80"); } - float128_type = make_node (REAL_TYPE); - TYPE_PRECISION (float128_type) = 128; - layout_type (float128_type); - (*lang_hooks.types.register_builtin_type) (float128_type, "__float128"); + if (TARGET_SSE) + { + tree float128_type = make_node (REAL_TYPE); + + TYPE_PRECISION (float128_type) = 128; + layout_type (float128_type); + (*lang_hooks.types.register_builtin_type) (float128_type, "__float128"); + } /* Add all builtins that are more or less simple operations on two operands. */ --- /home/jbeulich/src/gcc/mainline/2004-07-05.10.09/gcc/config/i386/i386.md 2004-07-02 15:20:47.000000000 +0200 +++ 2004-07-05.10.09/gcc/config/i386/i386.md 2004-07-07 15:39:12.932296352 +0200 @@ -19763,7 +19763,7 @@ (define_expand "movtf" [(set (match_operand:TF 0 "nonimmediate_operand" "") (match_operand:TF 1 "nonimmediate_operand" ""))] - "TARGET_64BIT" + "TARGET_SSE || TARGET_64BIT" { if (TARGET_64BIT) ix86_expand_move (TFmode, operands); @@ -20157,6 +20157,37 @@ (const_string "TI"))] (const_string "DI")))]) +(define_insn "*movtf_internal" + [(set (match_operand:TF 0 "nonimmediate_operand" "=x,x,m") + (match_operand:TF 1 "vector_move_operand" "C,xm,x"))] + "TARGET_SSE && !TARGET_64BIT + && (GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM)" +{ + switch (which_alternative) + { + case 0: + if (get_attr_mode (insn) == MODE_V4SF) + return "xorps\t%0, %0"; + else + return "pxor\t%0, %0"; + case 1: + case 2: + if (get_attr_mode (insn) == MODE_V4SF) + return "movaps\t{%1, %0|%0, %1}"; + else + return "movdqa\t{%1, %0|%0, %1}"; + default: + abort (); + } +} + [(set_attr "type" "ssemov,ssemov,ssemov") + (set (attr "mode") + (if_then_else + (ior (ne (symbol_ref "optimize_size") (const_int 0)) + (eq (symbol_ref "TARGET_SSE2") (const_int 0))) + (const_string "V4SF") + (const_string "TI")))]) + (define_insn "*movtf_rex64" [(set (match_operand:TF 0 "nonimmediate_operand" "=r,o,x,x,xm") (match_operand:TF 1 "general_operand" "riFo,riF,C,xm,x"))]
Attachment:
gcc-mainline-x86-TFmode.patch
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