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Re: DFA "pipeline" description for mcore
- From: Jeffrey A Law <law at redhat dot com>
- To: Steven Bosscher <stevenb at suse dot de>
- Cc: gcc-patches at gcc dot gnu dot org, nickc at redhat dot com
- Date: Mon, 05 Jul 2004 17:24:53 -0600
- Subject: Re: DFA "pipeline" description for mcore
- Organization: Red Hat, Inc
- References: <200407031727.17504.stevenb@suse.de>
- Reply-to: law at redhat dot com
On Sat, 2004-07-03 at 09:27, Steven Bosscher wrote:
> Hi,
>
> There's really no "pipeline model" here, only a load latency of
> 2 cycles instead of 1 is modelled. But in the DFA model, an insn
> that doesn't match a define_insn_reservation has latency 0, hence
> the extra lines.
>
> Tested by building an amd64 x mcore cross and comparing assembly.
> OK?
>
> Gr.
> Steven
>
> * config/mcore/mcore.c (TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE):
> Define.
> * config/mcore/mcore.md: Model memory latency with a simple DFA
> pipeline description instead of a define_function_unit.
This is fine.
jeff