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Removing -mdebugc from the MIPS port
- From: Richard Sandiford <rsandifo at redhat dot com>
- To: gcc-patches at gcc dot gnu dot org
- Cc: echristo at redhat dot com
- Date: Sun, 04 Jul 2004 15:40:33 +0100
- Subject: Removing -mdebugc from the MIPS port
The MIPS port has two ways of expanding scc-type operations: the default
one, and the one selected by TARGET_DEBUG_C_MODE. The latter can only
be activated by editing the source.
The default behaviour is to lower non-native scc operations at
rtl expansion time. Much of the code to do this is shared with
branches and conditional moves.
On the other hand, the TARGET_DEBUG_C_MODE version uses gradual
lowering. It provides define_insns for non-native scc instructions
and uses define_splits to break them up later.
I suspect the idea was that gradual lowering would help the higher-level
rtl optimisers understand what was happening. On the other hand,
immediate lowering gives more the optimisers more chance to remove
or simplify the individual MIPS instructions.
Naively, I'd have expected gradual lowering to be less of a win in the
tree-ssa world, and that the current approach (immediate lowering)
would be slightly better. And this does seem to be borne out by
a comparison of c-torture assembly output. Most of the files that
changed are better with the current approach.
For the record, a summary of -O2 -march=mips2 -mabi=32 output gives:
55 files changed, 1157 insertions(+), 1148 deletions(-)
where the "before" side is the current behaviour and the "after"
side is the TARGET_DEBUG_C_MODE version. The comparison for
-O2 -march=mips4 -mabi=eabi is:
17 files changed, 901 insertions(+), 892 deletions(-)
As a specific example:
int foo (int x) { return x == -1; }
is currently implemented as:
nor $2,$0,$4
j $31
sltu $2,$2,1
but the TARGET_DEBUG_C_MODE version gives:
li $2,-1
xor $2,$4,$2
j $31
sltu $2,$2,1
...the point being that the xor is exposed too late to be converted
to a nor. TARGET_DEBUG_C_MODE also has the problem of not supporting
64-bit or mips16 code properly. The expanders all have:
if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
{
gen_int_relational (...);
DONE;
}
So... I'd like to remove the TARGET_DEBUG_C_MODE. Patch tested on
mips64el-linux-gnu. Eric, is this OK with you?
I've got other changes planned for the gen_int_relational code,
but this is the first step...
Richard
* config/mips/mips.h (MASK_DEBUG_C, TARGET_DEBUG_C_MODE): Delete.
(TARGET_SWITCHES): Remove -mdebugc.
* config/mips/mips.md (seq, sne, sgt, sge, slt, sle, sgtu, sgeu)
(sltu, sleu): Remove TARGET_DEBUG_C_MODE handling.
(seq_[sd]i, sne_[sd]i, sge_[sd]i, sle_[sd]i_reg, sgeu_[sd]i)
(sle_[sd]i_reg): Delete.
Index: config/mips/mips.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.h,v
retrieving revision 1.343
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.343 mips.h
--- config/mips/mips.h 21 May 2004 01:03:19 -0000 1.343
+++ config/mips/mips.h 1 Jul 2004 08:34:56 -0000
@@ -176,7 +176,6 @@ #define MASK_FP_EXCEPTIONS 0x10000000
/* Debug switches, not documented */
#define MASK_DEBUG 0 /* unused */
-#define MASK_DEBUG_C 0 /* don't expand seq, etc. */
#define MASK_DEBUG_D 0 /* don't do define_split's */
/* Dummy switches used only in specs */
@@ -197,7 +196,6 @@ #define TARGET_MIPS_AS (!TARGET_GAS)
/* Debug Modes */
#define TARGET_DEBUG_MODE (target_flags & MASK_DEBUG)
-#define TARGET_DEBUG_C_MODE (target_flags & MASK_DEBUG_C)
#define TARGET_DEBUG_D_MODE (target_flags & MASK_DEBUG_D)
/* Reg. Naming in .s ($21 vs. $a0) */
@@ -672,8 +670,6 @@ #define TARGET_SWITCHES \
N_("FP exceptions are not enabled") }, \
{"debug", MASK_DEBUG, \
NULL}, \
- {"debugc", MASK_DEBUG_C, \
- NULL}, \
{"debugd", MASK_DEBUG_D, \
NULL}, \
{"", (TARGET_DEFAULT \
Index: config/mips/mips.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/mips/mips.md,v
retrieving revision 1.248
diff -u -p -F^\([(a-zA-Z0-9_]\|#define\) -r1.248 mips.md
--- config/mips/mips.md 26 Jun 2004 03:51:29 -0000 1.248
+++ config/mips/mips.md 1 Jul 2004 08:34:58 -0000
@@ -6318,20 +6318,8 @@ (define_expand "seq"
if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
FAIL;
- /* Set up operands from compare. */
- operands[1] = branch_cmp[0];
- operands[2] = branch_cmp[1];
-
- if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
- {
- gen_int_relational (EQ, operands[0], operands[1], operands[2], (int *)0);
- DONE;
- }
-
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
- operands[2] = force_reg (SImode, operands[2]);
-
- /* Fall through and generate default code. */
+ gen_int_relational (EQ, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+ DONE;
})
@@ -6371,59 +6359,6 @@ (define_insn ""
[(set_attr "type" "slt")
(set_attr "mode" "DI")])
-(define_insn "seq_si"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (eq:SI (match_operand:SI 1 "register_operand" "%d,d")
- (match_operand:SI 2 "uns_arith_operand" "d,K")))]
- "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "@
- xor\t%0,%1,%2\;sltu\t%0,%0,1
- xori\t%0,%1,%2\;sltu\t%0,%0,1"
- [(set_attr "type" "multi")
- (set_attr "mode" "SI")
- (set_attr "length" "8")])
-
-(define_split
- [(set (match_operand:SI 0 "register_operand")
- (eq:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "uns_arith_operand")))]
- "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
- && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
- [(set (match_dup 0)
- (xor:SI (match_dup 1)
- (match_dup 2)))
- (set (match_dup 0)
- (ltu:SI (match_dup 0)
- (const_int 1)))]
- "")
-
-(define_insn "seq_di"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (eq:DI (match_operand:DI 1 "register_operand" "%d,d")
- (match_operand:DI 2 "uns_arith_operand" "d,K")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "@
- xor\t%0,%1,%2\;sltu\t%0,%0,1
- xori\t%0,%1,%2\;sltu\t%0,%0,1"
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (eq:DI (match_operand:DI 1 "register_operand")
- (match_operand:DI 2 "uns_arith_operand")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
- && !TARGET_MIPS16
- && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
- [(set (match_dup 0)
- (xor:DI (match_dup 1)
- (match_dup 2)))
- (set (match_dup 0)
- (ltu:DI (match_dup 0)
- (const_int 1)))]
- "")
-
;; On the mips16 the default code is better than using sltu.
(define_expand "sne"
@@ -6435,20 +6370,8 @@ (define_expand "sne"
if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
FAIL;
- /* Set up operands from compare. */
- operands[1] = branch_cmp[0];
- operands[2] = branch_cmp[1];
-
- if (TARGET_64BIT || !TARGET_DEBUG_C_MODE)
- {
- gen_int_relational (NE, operands[0], operands[1], operands[2], (int *)0);
- DONE;
- }
-
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0)
- operands[2] = force_reg (SImode, operands[2]);
-
- /* Fall through and generate default code. */
+ gen_int_relational (NE, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+ DONE;
})
(define_insn "sne_si_zero"
@@ -6469,59 +6392,6 @@ (define_insn "sne_di_zero"
[(set_attr "type" "slt")
(set_attr "mode" "DI")])
-(define_insn "sne_si"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
- (ne:SI (match_operand:SI 1 "register_operand" "%d,d")
- (match_operand:SI 2 "uns_arith_operand" "d,K")))]
- "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "@
- xor\t%0,%1,%2\;sltu\t%0,%.,%0
- xori\t%0,%1,%x2\;sltu\t%0,%.,%0"
- [(set_attr "type" "multi")
- (set_attr "mode" "SI")
- (set_attr "length" "8")])
-
-(define_split
- [(set (match_operand:SI 0 "register_operand")
- (ne:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "uns_arith_operand")))]
- "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16
- && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
- [(set (match_dup 0)
- (xor:SI (match_dup 1)
- (match_dup 2)))
- (set (match_dup 0)
- (gtu:SI (match_dup 0)
- (const_int 0)))]
- "")
-
-(define_insn "sne_di"
- [(set (match_operand:DI 0 "register_operand" "=d,d")
- (ne:DI (match_operand:DI 1 "register_operand" "%d,d")
- (match_operand:DI 2 "uns_arith_operand" "d,K")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "@
- xor\t%0,%1,%2\;sltu\t%0,%.,%0
- xori\t%0,%1,%x2\;sltu\t%0,%.,%0"
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (ne:DI (match_operand:DI 1 "register_operand")
- (match_operand:DI 2 "uns_arith_operand")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
- && !TARGET_MIPS16
- && (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0)"
- [(set (match_dup 0)
- (xor:DI (match_dup 1)
- (match_dup 2)))
- (set (match_dup 0)
- (gtu:DI (match_dup 0)
- (const_int 0)))]
- "")
-
(define_expand "sgt"
[(set (match_operand:SI 0 "register_operand")
(gt:SI (match_dup 1)
@@ -6531,20 +6401,8 @@ (define_expand "sgt"
if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
FAIL;
- /* Set up operands from compare. */
- operands[1] = branch_cmp[0];
- operands[2] = branch_cmp[1];
-
- if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
- {
- gen_int_relational (GT, operands[0], operands[1], operands[2], (int *)0);
- DONE;
- }
-
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
- operands[2] = force_reg (SImode, operands[2]);
-
- /* Fall through and generate default code. */
+ gen_int_relational (GT, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+ DONE;
})
(define_insn "sgt_si"
@@ -6592,66 +6450,10 @@ (define_expand "sge"
if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
FAIL;
- /* Set up operands from compare. */
- operands[1] = branch_cmp[0];
- operands[2] = branch_cmp[1];
-
- if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
- {
- gen_int_relational (GE, operands[0], operands[1], operands[2], (int *)0);
- DONE;
- }
-
- /* Fall through and generate default code. */
+ gen_int_relational (GE, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+ DONE;
})
-(define_insn "sge_si"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (ge:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "slt\t%0,%1,%2\;xori\t%0,%0,0x0001"
- [(set_attr "type" "multi")
- (set_attr "mode" "SI")
- (set_attr "length" "8")])
-
-(define_split
- [(set (match_operand:SI 0 "register_operand")
- (ge:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "arith_operand")))]
- "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
- [(set (match_dup 0)
- (lt:SI (match_dup 1)
- (match_dup 2)))
- (set (match_dup 0)
- (xor:SI (match_dup 0)
- (const_int 1)))]
- "")
-
-(define_insn "sge_di"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (ge:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:DI 2 "arith_operand" "dI")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "slt\t%0,%1,%2\;xori\t%0,%0,0x0001"
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (ge:DI (match_operand:DI 1 "register_operand")
- (match_operand:DI 2 "arith_operand")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
- && !TARGET_MIPS16"
- [(set (match_dup 0)
- (lt:DI (match_dup 1)
- (match_dup 2)))
- (set (match_dup 0)
- (xor:DI (match_dup 0)
- (const_int 1)))]
- "")
-
(define_expand "slt"
[(set (match_operand:SI 0 "register_operand")
(lt:SI (match_dup 1)
@@ -6661,17 +6463,8 @@ (define_expand "slt"
if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
FAIL;
- /* Set up operands from compare. */
- operands[1] = branch_cmp[0];
- operands[2] = branch_cmp[1];
-
- if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
- {
- gen_int_relational (LT, operands[0], operands[1], operands[2], (int *)0);
- DONE;
- }
-
- /* Fall through and generate default code. */
+ gen_int_relational (LT, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+ DONE;
})
(define_insn "slt_si"
@@ -6729,20 +6522,8 @@ (define_expand "sle"
if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
FAIL;
- /* Set up operands from compare. */
- operands[1] = branch_cmp[0];
- operands[2] = branch_cmp[1];
-
- if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
- {
- gen_int_relational (LE, operands[0], operands[1], operands[2], (int *)0);
- DONE;
- }
-
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
- operands[2] = force_reg (SImode, operands[2]);
-
- /* Fall through and generate default code. */
+ gen_int_relational (LE, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+ DONE;
})
(define_insn "sle_si_const"
@@ -6799,53 +6580,6 @@ (define_insn ""
(const_int 4)
(const_int 8)))])
-(define_insn "sle_si_reg"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (le:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))]
- "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "slt\t%0,%z2,%1\;xori\t%0,%0,0x0001"
- [(set_attr "type" "multi")
- (set_attr "mode" "SI")
- (set_attr "length" "8")])
-
-(define_split
- [(set (match_operand:SI 0 "register_operand")
- (le:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "register_operand")))]
- "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
- [(set (match_dup 0)
- (lt:SI (match_dup 2)
- (match_dup 1)))
- (set (match_dup 0)
- (xor:SI (match_dup 0)
- (const_int 1)))]
- "")
-
-(define_insn "sle_di_reg"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (le:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:DI 2 "register_operand" "d")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "slt\t%0,%z2,%1\;xori\t%0,%0,0x0001"
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (le:DI (match_operand:DI 1 "register_operand")
- (match_operand:DI 2 "register_operand")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
- && !TARGET_MIPS16"
- [(set (match_dup 0)
- (lt:DI (match_dup 2)
- (match_dup 1)))
- (set (match_dup 0)
- (xor:DI (match_dup 0)
- (const_int 1)))]
- "")
-
(define_expand "sgtu"
[(set (match_operand:SI 0 "register_operand")
(gtu:SI (match_dup 1)
@@ -6855,20 +6589,8 @@ (define_expand "sgtu"
if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
FAIL;
- /* Set up operands from compare. */
- operands[1] = branch_cmp[0];
- operands[2] = branch_cmp[1];
-
- if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
- {
- gen_int_relational (GTU, operands[0], operands[1], operands[2], (int *)0);
- DONE;
- }
-
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) != 0)
- operands[2] = force_reg (SImode, operands[2]);
-
- /* Fall through and generate default code. */
+ gen_int_relational (GTU, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+ DONE;
})
(define_insn "sgtu_si"
@@ -6916,66 +6638,10 @@ (define_expand "sgeu"
if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
FAIL;
- /* Set up operands from compare. */
- operands[1] = branch_cmp[0];
- operands[2] = branch_cmp[1];
-
- if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
- {
- gen_int_relational (GEU, operands[0], operands[1], operands[2], (int *)0);
- DONE;
- }
-
- /* Fall through and generate default code. */
+ gen_int_relational (GEU, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+ DONE;
})
-(define_insn "sgeu_si"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (geu:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "arith_operand" "dI")))]
- "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "sltu\t%0,%1,%2\;xori\t%0,%0,0x0001"
- [(set_attr "type" "multi")
- (set_attr "mode" "SI")
- (set_attr "length" "8")])
-
-(define_split
- [(set (match_operand:SI 0 "register_operand")
- (geu:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "arith_operand")))]
- "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
- [(set (match_dup 0)
- (ltu:SI (match_dup 1)
- (match_dup 2)))
- (set (match_dup 0)
- (xor:SI (match_dup 0)
- (const_int 1)))]
- "")
-
-(define_insn "sgeu_di"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (geu:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:DI 2 "arith_operand" "dI")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "sltu\t%0,%1,%2\;xori\t%0,%0,0x0001"
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (geu:DI (match_operand:DI 1 "register_operand")
- (match_operand:DI 2 "arith_operand")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
- && !TARGET_MIPS16"
- [(set (match_dup 0)
- (ltu:DI (match_dup 1)
- (match_dup 2)))
- (set (match_dup 0)
- (xor:DI (match_dup 0)
- (const_int 1)))]
- "")
-
(define_expand "sltu"
[(set (match_operand:SI 0 "register_operand")
(ltu:SI (match_dup 1)
@@ -6985,17 +6651,8 @@ (define_expand "sltu"
if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
FAIL;
- /* Set up operands from compare. */
- operands[1] = branch_cmp[0];
- operands[2] = branch_cmp[1];
-
- if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
- {
- gen_int_relational (LTU, operands[0], operands[1], operands[2], (int *)0);
- DONE;
- }
-
- /* Fall through and generate default code. */
+ gen_int_relational (LTU, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+ DONE;
})
(define_insn "sltu_si"
@@ -7053,20 +6710,8 @@ (define_expand "sleu"
if (branch_type != CMP_SI && (!TARGET_64BIT || branch_type != CMP_DI))
FAIL;
- /* Set up operands from compare. */
- operands[1] = branch_cmp[0];
- operands[2] = branch_cmp[1];
-
- if (TARGET_64BIT || !TARGET_DEBUG_C_MODE || TARGET_MIPS16)
- {
- gen_int_relational (LEU, operands[0], operands[1], operands[2], (int *)0);
- DONE;
- }
-
- if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 32767)
- operands[2] = force_reg (SImode, operands[2]);
-
- /* Fall through and generate default code. */
+ gen_int_relational (LEU, operands[0], branch_cmp[0], branch_cmp[1], NULL);
+ DONE;
})
(define_insn "sleu_si_const"
@@ -7122,53 +6767,6 @@ (define_insn ""
(set (attr "length") (if_then_else (match_operand:VOID 2 "m16_uimm8_m1_1")
(const_int 4)
(const_int 8)))])
-
-(define_insn "sleu_si_reg"
- [(set (match_operand:SI 0 "register_operand" "=d")
- (leu:SI (match_operand:SI 1 "register_operand" "d")
- (match_operand:SI 2 "register_operand" "d")))]
- "TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "sltu\t%0,%z2,%1\;xori\t%0,%0,0x0001"
- [(set_attr "type" "multi")
- (set_attr "mode" "SI")
- (set_attr "length" "8")])
-
-(define_split
- [(set (match_operand:SI 0 "register_operand")
- (leu:SI (match_operand:SI 1 "register_operand")
- (match_operand:SI 2 "register_operand")))]
- "TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE && !TARGET_MIPS16"
- [(set (match_dup 0)
- (ltu:SI (match_dup 2)
- (match_dup 1)))
- (set (match_dup 0)
- (xor:SI (match_dup 0)
- (const_int 1)))]
- "")
-
-(define_insn "sleu_di_reg"
- [(set (match_operand:DI 0 "register_operand" "=d")
- (leu:DI (match_operand:DI 1 "register_operand" "d")
- (match_operand:DI 2 "register_operand" "d")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_MIPS16"
- "sltu\t%0,%z2,%1\;xori\t%0,%0,0x0001"
- [(set_attr "type" "multi")
- (set_attr "mode" "DI")
- (set_attr "length" "8")])
-
-(define_split
- [(set (match_operand:DI 0 "register_operand")
- (leu:DI (match_operand:DI 1 "register_operand")
- (match_operand:DI 2 "register_operand")))]
- "TARGET_64BIT && TARGET_DEBUG_C_MODE && !TARGET_DEBUG_D_MODE
- && !TARGET_MIPS16"
- [(set (match_dup 0)
- (ltu:DI (match_dup 2)
- (match_dup 1)))
- (set (match_dup 0)
- (xor:DI (match_dup 0)
- (const_int 1)))]
- "")
;;
;; ....................