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[committed] Add prefetch patterns for PA 2.0
- From: "John David Anglin" <dave at hiauly1 dot hia dot nrc dot ca>
- To: gcc-patches at gcc dot gnu dot org
- Date: Wed, 30 Jun 2004 22:28:11 -2800 (EDT)
- Subject: [committed] Add prefetch patterns for PA 2.0
Tested with bootstrap and check on hppa-unknown-linux-gnu, and by
inspecting all code permutations with __builtin_prefetch. Committed
to trunk.
Dave
--
J. David Anglin dave.anglin@nrc-cnrc.gc.ca
National Research Council of Canada (613) 990-0752 (FAX: 952-6602)
2004-06-30 John David Anglin <dave.anglin@nrc-cnrc.gc.ca>
* pa-protos.h (prefetch_operand): Add prototype.
* pa.c (prefetch_operand): New function.
* pa.h (prefetch_operand): Add to PREDICATE_CODES.
* pa.md (prefetch, prefetch_32, prefetch_64): New prefetch patterns.
Index: config/pa/pa-protos.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/pa/pa-protos.h,v
retrieving revision 1.32
diff -u -3 -p -r1.32 pa-protos.h
--- config/pa/pa-protos.h 26 Jan 2004 00:09:43 -0000 1.32
+++ config/pa/pa-protos.h 1 Jul 2004 00:59:44 -0000
@@ -80,6 +80,7 @@ extern int arith_operand (rtx, enum mach
extern int read_only_operand (rtx, enum machine_mode);
extern int move_dest_operand (rtx, enum machine_mode);
extern int move_src_operand (rtx, enum machine_mode);
+extern int prefetch_operand (rtx, enum machine_mode);
extern int and_operand (rtx, enum machine_mode);
extern int ior_operand (rtx, enum machine_mode);
extern int arith32_operand (rtx, enum machine_mode);
Index: config/pa/pa.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/pa/pa.c,v
retrieving revision 1.252
diff -u -3 -p -r1.252 pa.c
--- config/pa/pa.c 21 Jun 2004 23:48:59 -0000 1.252
+++ config/pa/pa.c 1 Jul 2004 00:59:45 -0000
@@ -617,6 +617,27 @@ move_src_operand (rtx op, enum machine_m
return memory_address_p (mode, XEXP (op, 0));
}
+/* Accept anything that can be used as the source operand for a prefetch
+ instruction. */
+int
+prefetch_operand (rtx op, enum machine_mode mode)
+{
+ if (GET_CODE (op) != MEM)
+ return 0;
+
+ /* Until problems with management of the REG_POINTER flag are resolved,
+ we need to delay creating prefetch insns with unscaled indexed addresses
+ until CSE is not expected. */
+ if (!TARGET_NO_SPACE_REGS
+ && !cse_not_expected
+ && GET_CODE (XEXP (op, 0)) == PLUS
+ && REG_P (XEXP (XEXP (op, 0), 0))
+ && REG_P (XEXP (XEXP (op, 0), 1)))
+ return 0;
+
+ return memory_address_p (mode, XEXP (op, 0));
+}
+
/* Accept REG and any CONST_INT that can be moved in one instruction into a
general register. */
int
Index: config/pa/pa.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/pa/pa.h,v
retrieving revision 1.219
diff -u -3 -p -r1.219 pa.h
--- config/pa/pa.h 21 Jun 2004 23:49:04 -0000 1.219
+++ config/pa/pa.h 1 Jul 2004 00:59:45 -0000
@@ -2023,6 +2023,7 @@ do { \
CONST_DOUBLE}}, \
{"move_dest_operand", {SUBREG, REG, MEM}}, \
{"move_src_operand", {SUBREG, REG, CONST_INT, MEM}}, \
+ {"prefetch_operand", {MEM}}, \
{"reg_or_cint_move_operand", {SUBREG, REG, CONST_INT}}, \
{"pic_label_operand", {LABEL_REF, CONST}}, \
{"fp_reg_operand", {REG}}, \
Index: config/pa/pa.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/pa/pa.md,v
retrieving revision 1.149
diff -u -3 -p -r1.149 pa.md
--- config/pa/pa.md 11 Jun 2004 22:46:13 -0000 1.149
+++ config/pa/pa.md 1 Jul 2004 00:59:45 -0000
@@ -9352,3 +9352,121 @@ add,l %2,%3,%3\;bv,n %%r0(%3)"
}
DONE;
}")
+
+(define_expand "prefetch"
+ [(match_operand 0 "address_operand" "")
+ (match_operand 1 "const_int_operand" "")
+ (match_operand 2 "const_int_operand" "")]
+ "TARGET_PA_20"
+{
+ /* We change operand0 to a MEM as we don't have the infrastructure to
+ output all the supported address modes for ldw/ldd but we do have
+ it for MEMs. */
+ operands[0] = gen_rtx_MEM (Pmode, operands[0]);
+
+ if (!TARGET_NO_SPACE_REGS
+ && !cse_not_expected
+ && GET_CODE (XEXP (operands[0], 0)) == PLUS
+ && REG_P (XEXP (XEXP (operands[0], 0), 0))
+ && REG_P (XEXP (XEXP (operands[0], 0), 1)))
+ operands[0]
+ = replace_equiv_address (operands[0],
+ copy_to_mode_reg (Pmode,
+ XEXP (operands[0], 0)));
+
+ if (TARGET_64BIT)
+ emit_insn (gen_prefetch_64 (operands[0], operands[1], operands[2]));
+ else
+ emit_insn (gen_prefetch_32 (operands[0], operands[1], operands[2]));
+ DONE;
+})
+
+(define_insn "prefetch_64"
+ [(prefetch (match_operand:DI 0 "prefetch_operand" "A,RQ")
+ (match_operand:DI 1 "const_int_operand" "n,n")
+ (match_operand:DI 2 "const_int_operand" "n,n"))]
+ "TARGET_64BIT"
+{
+ /* The SL completor indicates good spatial locality but poor temporal
+ locality. The ldw instruction with a target of general register 0
+ prefetches a cache line for a read. The ldd instruction prefetches
+ a cache line for a write. */
+ static const char * const instr[2][2][2] = {
+ {
+ {
+ "ldw,sl RT'%A0,%%r0",
+ "ldw RT'%A0,%%r0",
+ },
+ {
+ "ldd,sl RT'%A0,%%r0",
+ "ldd RT'%A0,%%r0",
+ },
+ },
+ {
+ {
+ "ldw%M0,sl %0,%%r0",
+ "ldw%M0 %0,%%r0",
+ },
+ {
+ "ldd%M0,sl %0,%%r0",
+ "ldd%M0 %0,%%r0",
+ }
+ }
+ };
+ int read_or_write = INTVAL (operands[1]);
+ int locality = INTVAL (operands[2]);
+
+ if ((which_alternative != 0 && which_alternative != 1)
+ || (read_or_write != 0 && read_or_write != 1)
+ || (locality < 0 || locality > 3))
+ abort ();
+
+ return instr [which_alternative][read_or_write][locality == 0 ? 0 : 1];
+}
+ [(set_attr "type" "load")
+ (set_attr "length" "4")])
+
+(define_insn "prefetch_32"
+ [(prefetch (match_operand:SI 0 "prefetch_operand" "A,RQ")
+ (match_operand:SI 1 "const_int_operand" "n,n")
+ (match_operand:SI 2 "const_int_operand" "n,n"))]
+ "TARGET_PA_20"
+{
+ /* The SL completor indicates good spatial locality but poor temporal
+ locality. The ldw instruction with a target of general register 0
+ prefetches a cache line for a read. The ldd instruction prefetches
+ a cache line for a write. */
+ static const char * const instr[2][2][2] = {
+ {
+ {
+ "ldw,sl RT'%A0,%%r0",
+ "ldw RT'%A0,%%r0",
+ },
+ {
+ "ldd,sl RT'%A0,%%r0",
+ "ldd RT'%A0,%%r0",
+ },
+ },
+ {
+ {
+ "ldw%M0,sl %0,%%r0",
+ "ldw%M0 %0,%%r0",
+ },
+ {
+ "ldd%M0,sl %0,%%r0",
+ "ldd%M0 %0,%%r0",
+ }
+ }
+ };
+ int read_or_write = INTVAL (operands[1]);
+ int locality = INTVAL (operands[2]);
+
+ if ((which_alternative != 0 && which_alternative != 1)
+ || (read_or_write != 0 && read_or_write != 1)
+ || (locality < 0 || locality > 3))
+ abort ();
+
+ return instr [which_alternative][read_or_write][locality == 0 ? 0 : 1];
+}
+ [(set_attr "type" "load")
+ (set_attr "length" "4")])