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Re: [committed] PR16176: Fix invalid lwl/lwr pairs

> In the PR, reduced to the testcase below, we were expanding an lwl/lwr
> pair in which the destination register was also mentioned in the source
> operand.  We ended up something like:
>         lwl r1,(r1)
>         lwr r1,3(r1)
> in which the lwr address was wrongly clobbered.

We're seeing a similar problem with a 3.4.x based compiler, except that the 
culprit is the MIPSpro assembler.  GCC emits sequences like

  ldl     $2,.LC0+1
  ldr     $2,.LC0+8

which are expanded by the assembler into

  20:   8f820000        lw      v0,0(gp)
  24:   64420000        daddiu  v0,v0,0
  28:   68420001        ldl     v0,1(v0)

  2c:   8f820000        lw      v0,0(gp)
  30:   64420000        daddiu  v0,v0,0
  34:   6c420008        ldr     v0,8(v0)

so $2 is wrongly clobbered.

Olivier spotted the problem and also pointed out that the manual states that 
the second operand is expected to be an effective address expressed as 
offset(basereg).  However SGI seems to have acknowledged it is a genuine 

At this point we don't know yet if we'll have to work around it or require 
the fixed assembler.

Eric Botcazou

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