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Re: Alphebetize manual
Gerald Pfeifer wrote:
On Mon, 21 Jun 2004, Nathan Sidwell wrote:
the list of machine dependent options is in a random order. This
alphabetizes them, ok?
I like this, but suggest to wait two, three days to see whether there
_was_ some secret logic behind the original sorting. :-)
Here's the corresponding changes further down the manual. I presume these
are likewise ok, if no one explains the current ordering.
nathan
--
Nathan Sidwell :: http://www.codesourcery.com :: CodeSourcery LLC
nathan@codesourcery.com :: http://www.planetfall.pwp.blueyonder.co.uk
2004-06-21 Nathan Sidwell <nathan@codesourcery.com>
* doc/invoke.texi (Submodel Options): Alphabetize.
Index: doc/invoke.texi
===================================================================
RCS file: /cvs/gcc/gcc/gcc/doc/invoke.texi,v
retrieving revision 1.468
diff -c -3 -p -r1.468 invoke.texi
*** doc/invoke.texi 1 Jun 2004 07:13:51 -0000 1.468
--- doc/invoke.texi 21 Jun 2004 11:08:52 -0000
*************** These options are defined by the macro @
*** 6214,10389 ****
machine description. The default for the options is also defined by
that macro, which enables you to change the defaults.
@menu
! * M680x0 Options::
! * M68hc1x Options::
! * VAX Options::
! * SPARC Options::
* ARM Options::
! * MN10300 Options::
! * M32R/D Options::
! * RS/6000 and PowerPC Options::
* Darwin Options::
- * MIPS Options::
- * i386 and x86-64 Options::
- * HPPA Options::
* DEC Alpha Options::
* DEC Alpha/VMS Options::
* H8/300 Options::
* SH Options::
* System V Options::
* TMS320C3x/C4x Options::
* V850 Options::
! * ARC Options::
! * NS32K Options::
! * AVR Options::
! * MCore Options::
! * IA-64 Options::
! * S/390 and zSeries Options::
! * CRIS Options::
! * MMIX Options::
! * PDP-11 Options::
* Xstormy16 Options::
* Xtensa Options::
! * FRV Options::
@end menu
! @node M680x0 Options
! @subsection M680x0 Options
! @cindex M680x0 options
! These are the @samp{-m} options defined for the 68000 series. The default
! values for these options depends on which style of 68000 was selected when
! the compiler was configured; the defaults for the most common choices are
! given below.
@table @gcctabopt
! @item -m68000
! @itemx -mc68000
! @opindex m68000
! @opindex mc68000
! Generate output for a 68000. This is the default
! when the compiler is configured for 68000-based systems.
! Use this option for microcontrollers with a 68000 or EC000 core,
! including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356.
! @item -m68020
! @itemx -mc68020
! @opindex m68020
! @opindex mc68020
! Generate output for a 68020. This is the default
! when the compiler is configured for 68020-based systems.
! @item -m68881
! @opindex m68881
! Generate output containing 68881 instructions for floating point.
! This is the default for most 68020 systems unless @option{--nfp} was
! specified when the compiler was configured.
! @item -m68030
! @opindex m68030
! Generate output for a 68030. This is the default when the compiler is
! configured for 68030-based systems.
! @item -m68040
! @opindex m68040
! Generate output for a 68040. This is the default when the compiler is
! configured for 68040-based systems.
! This option inhibits the use of 68881/68882 instructions that have to be
! emulated by software on the 68040. Use this option if your 68040 does not
! have code to emulate those instructions.
! @item -m68060
! @opindex m68060
! Generate output for a 68060. This is the default when the compiler is
! configured for 68060-based systems.
! This option inhibits the use of 68020 and 68881/68882 instructions that
! have to be emulated by software on the 68060. Use this option if your 68060
! does not have code to emulate those instructions.
! @item -mcpu32
! @opindex mcpu32
! Generate output for a CPU32. This is the default
! when the compiler is configured for CPU32-based systems.
! Use this option for microcontrollers with a
! CPU32 or CPU32+ core, including the 68330, 68331, 68332, 68333, 68334,
! 68336, 68340, 68341, 68349 and 68360.
! @item -m5200
! @opindex m5200
! Generate output for a 520X ``coldfire'' family cpu. This is the default
! when the compiler is configured for 520X-based systems.
! Use this option for microcontroller with a 5200 core, including
! the MCF5202, MCF5203, MCF5204 and MCF5202.
! @item -m68020-40
! @opindex m68020-40
! Generate output for a 68040, without using any of the new instructions.
! This results in code which can run relatively efficiently on either a
! 68020/68881 or a 68030 or a 68040. The generated code does use the
! 68881 instructions that are emulated on the 68040.
! @item -m68020-60
! @opindex m68020-60
! Generate output for a 68060, without using any of the new instructions.
! This results in code which can run relatively efficiently on either a
! 68020/68881 or a 68030 or a 68040. The generated code does use the
! 68881 instructions that are emulated on the 68060.
@item -msoft-float
@opindex msoft-float
Generate output containing library calls for floating point.
! @strong{Warning:} the requisite libraries are not available for all m68k
targets. Normally the facilities of the machine's usual C compiler are
! used, but this can't be done directly in cross-compilation. You must
! make your own arrangements to provide suitable library functions for
! cross-compilation. The embedded targets @samp{m68k-*-aout} and
! @samp{m68k-*-coff} do provide software floating point support.
!
! @item -mshort
! @opindex mshort
! Consider type @code{int} to be 16 bits wide, like @code{short int}.
! Additionally, parameters passed on the stack are also aligned to a
! 16-bit boundary even on targets whose API mandates promotion to 32-bit.
! @item -mnobitfield
! @opindex mnobitfield
! Do not use the bit-field instructions. The @option{-m68000}, @option{-mcpu32}
! and @option{-m5200} options imply @w{@option{-mnobitfield}}.
! @item -mbitfield
! @opindex mbitfield
! Do use the bit-field instructions. The @option{-m68020} option implies
! @option{-mbitfield}. This is the default if you use a configuration
! designed for a 68020.
! @item -mrtd
! @opindex mrtd
! Use a different function-calling convention, in which functions
! that take a fixed number of arguments return with the @code{rtd}
! instruction, which pops their arguments while returning. This
! saves one instruction in the caller since there is no need to pop
! the arguments there.
! This calling convention is incompatible with the one normally
! used on Unix, so you cannot use it if you need to call libraries
! compiled with the Unix compiler.
!
! Also, you must provide function prototypes for all functions that
! take variable numbers of arguments (including @code{printf});
! otherwise incorrect code will be generated for calls to those
! functions.
!
! In addition, seriously incorrect code will result if you call a
! function with too many arguments. (Normally, extra arguments are
! harmlessly ignored.)
!
! The @code{rtd} instruction is supported by the 68010, 68020, 68030,
! 68040, 68060 and CPU32 processors, but not by the 68000 or 5200.
!
! @item -malign-int
! @itemx -mno-align-int
! @opindex malign-int
! @opindex mno-align-int
! Control whether GCC aligns @code{int}, @code{long}, @code{long long},
! @code{float}, @code{double}, and @code{long double} variables on a 32-bit
! boundary (@option{-malign-int}) or a 16-bit boundary (@option{-mno-align-int}).
! Aligning variables on 32-bit boundaries produces code that runs somewhat
! faster on processors with 32-bit busses at the expense of more memory.
!
! @strong{Warning:} if you use the @option{-malign-int} switch, GCC will
! align structures containing the above types differently than
! most published application binary interface specifications for the m68k.
!
! @item -mpcrel
! @opindex mpcrel
! Use the pc-relative addressing mode of the 68000 directly, instead of
! using a global offset table. At present, this option implies @option{-fpic},
! allowing at most a 16-bit offset for pc-relative addressing. @option{-fPIC} is
! not presently supported with @option{-mpcrel}, though this could be supported for
! 68020 and higher processors.
!
! @item -mno-strict-align
! @itemx -mstrict-align
! @opindex mno-strict-align
! @opindex mstrict-align
! Do not (do) assume that unaligned memory references will be handled by
! the system.
!
! @item -msep-data
! Generate code that allows the data segment to be located in a different
! area of memory from the text segment. This allows for execute in place in
! an environment without virtual memory management. This option implies -fPIC.
!
! @item -mno-sep-data
! Generate code that assumes that the data segment follows the text segment.
! This is the default.
!
! @item -mid-shared-library
! Generate code that supports shared libraries via the library ID method.
! This allows for execute in place and shared libraries in an environment
! without virtual memory management. This option implies -fPIC.
! @item -mno-id-shared-library
! Generate code that doesn't assume ID based shared libraries are being used.
! This is the default.
! @item -mshared-library-id=n
! Specified the identification number of the ID based shared library being
! compiled. Specifying a value of 0 will generate more compact code, specifying
! other values will force the allocation of that number to the current
! library but is no more space or time efficient than omitting this option.
! @end table
! @node M68hc1x Options
! @subsection M68hc1x Options
! @cindex M68hc1x options
! These are the @samp{-m} options defined for the 68hc11 and 68hc12
! microcontrollers. The default values for these options depends on
! which style of microcontroller was selected when the compiler was configured;
! the defaults for the most common choices are given below.
! @table @gcctabopt
! @item -m6811
! @itemx -m68hc11
! @opindex m6811
! @opindex m68hc11
! Generate output for a 68HC11. This is the default
! when the compiler is configured for 68HC11-based systems.
! @item -m6812
! @itemx -m68hc12
! @opindex m6812
! @opindex m68hc12
! Generate output for a 68HC12. This is the default
! when the compiler is configured for 68HC12-based systems.
! @item -m68S12
! @itemx -m68hcs12
! @opindex m68S12
! @opindex m68hcs12
! Generate output for a 68HCS12.
! @item -mauto-incdec
! @opindex mauto-incdec
! Enable the use of 68HC12 pre and post auto-increment and auto-decrement
! addressing modes.
! @item -minmax
! @itemx -nominmax
! @opindex minmax
! @opindex mnominmax
! Enable the use of 68HC12 min and max instructions.
@item -mlong-calls
@itemx -mno-long-calls
@opindex mlong-calls
@opindex mno-long-calls
! Treat all calls as being far away (near). If calls are assumed to be
! far away, the compiler will use the @code{call} instruction to
! call a function and the @code{rtc} instruction for returning.
! @item -mshort
! @opindex mshort
! Consider type @code{int} to be 16 bits wide, like @code{short int}.
! @item -msoft-reg-count=@var{count}
! @opindex msoft-reg-count
! Specify the number of pseudo-soft registers which are used for the
! code generation. The maximum number is 32. Using more pseudo-soft
! register may or may not result in better code depending on the program.
! The default is 4 for 68HC11 and 2 for 68HC12.
! @end table
! @node VAX Options
! @subsection VAX Options
! @cindex VAX options
! These @samp{-m} options are defined for the VAX:
! @table @gcctabopt
! @item -munix
! @opindex munix
! Do not output certain jump instructions (@code{aobleq} and so on)
! that the Unix assembler for the VAX cannot handle across long
! ranges.
! @item -mgnu
! @opindex mgnu
! Do output those jump instructions, on the assumption that you
! will assemble with the GNU assembler.
! @item -mg
! @opindex mg
! Output code for g-format floating point numbers instead of d-format.
! @end table
! @node SPARC Options
! @subsection SPARC Options
! @cindex SPARC options
! These @samp{-m} options are supported on the SPARC:
! @table @gcctabopt
! @item -mno-app-regs
! @itemx -mapp-regs
! @opindex mno-app-regs
! @opindex mapp-regs
! Specify @option{-mapp-regs} to generate output using the global registers
! 2 through 4, which the SPARC SVR4 ABI reserves for applications. This
! is the default.
! To be fully SVR4 ABI compliant at the cost of some performance loss,
! specify @option{-mno-app-regs}. You should compile libraries and system
! software with this option.
! @item -mfpu
! @itemx -mhard-float
! @opindex mfpu
! @opindex mhard-float
! Generate output containing floating point instructions. This is the
! default.
! @item -mno-fpu
! @itemx -msoft-float
! @opindex mno-fpu
! @opindex msoft-float
! Generate output containing library calls for floating point.
! @strong{Warning:} the requisite libraries are not available for all SPARC
! targets. Normally the facilities of the machine's usual C compiler are
! used, but this cannot be done directly in cross-compilation. You must make
! your own arrangements to provide suitable library functions for
! cross-compilation. The embedded targets @samp{sparc-*-aout} and
! @samp{sparclite-*-*} do provide software floating point support.
! @option{-msoft-float} changes the calling convention in the output file;
! therefore, it is only useful if you compile @emph{all} of a program with
! this option. In particular, you need to compile @file{libgcc.a}, the
! library that comes with GCC, with @option{-msoft-float} in order for
! this to work.
! @item -mhard-quad-float
! @opindex mhard-quad-float
! Generate output containing quad-word (long double) floating point
! instructions.
! @item -msoft-quad-float
! @opindex msoft-quad-float
! Generate output containing library calls for quad-word (long double)
! floating point instructions. The functions called are those specified
! in the SPARC ABI@. This is the default.
! As of this writing, there are no SPARC implementations that have hardware
! support for the quad-word floating point instructions. They all invoke
! a trap handler for one of these instructions, and then the trap handler
! emulates the effect of the instruction. Because of the trap handler overhead,
! this is much slower than calling the ABI library routines. Thus the
! @option{-msoft-quad-float} option is the default.
! @item -mno-unaligned-doubles
! @itemx -munaligned-doubles
! @opindex mno-unaligned-doubles
! @opindex munaligned-doubles
! Assume that doubles have 8 byte alignment. This is the default.
! With @option{-munaligned-doubles}, GCC assumes that doubles have 8 byte
! alignment only if they are contained in another type, or if they have an
! absolute address. Otherwise, it assumes they have 4 byte alignment.
! Specifying this option avoids some rare compatibility problems with code
! generated by other compilers. It is not the default because it results
! in a performance loss, especially for floating point code.
! @item -mno-faster-structs
! @itemx -mfaster-structs
! @opindex mno-faster-structs
! @opindex mfaster-structs
! With @option{-mfaster-structs}, the compiler assumes that structures
! should have 8 byte alignment. This enables the use of pairs of
! @code{ldd} and @code{std} instructions for copies in structure
! assignment, in place of twice as many @code{ld} and @code{st} pairs.
! However, the use of this changed alignment directly violates the SPARC
! ABI@. Thus, it's intended only for use on targets where the developer
! acknowledges that their resulting code will not be directly in line with
! the rules of the ABI@.
! @item -mimpure-text
! @opindex mimpure-text
! @option{-mimpure-text}, used in addition to @option{-shared}, tells
! the compiler to not pass @option{-z text} to the linker when linking a
! shared object. Using this option, you can link position-dependent
! code into a shared object.
! @option{-mimpure-text} suppresses the ``relocations remain against
! allocatable but non-writable sections'' linker error message.
! However, the necessary relocations will trigger copy-on-write, and the
! shared object is not actually shared across processes. Instead of
! using @option{-mimpure-text}, you should compile all source code with
! @option{-fpic} or @option{-fPIC}.
! This option is only available on SunOS and Solaris.
! @item -mcpu=@var{cpu_type}
! @opindex mcpu
! Set the instruction set, register set, and instruction scheduling parameters
! for machine type @var{cpu_type}. Supported values for @var{cpu_type} are
! @samp{v7}, @samp{cypress}, @samp{v8}, @samp{supersparc}, @samp{sparclite},
! @samp{f930}, @samp{f934}, @samp{hypersparc}, @samp{sparclite86x},
! @samp{sparclet}, @samp{tsc701}, @samp{v9}, @samp{ultrasparc}, and
! @samp{ultrasparc3}.
! Default instruction scheduling parameters are used for values that select
! an architecture and not an implementation. These are @samp{v7}, @samp{v8},
! @samp{sparclite}, @samp{sparclet}, @samp{v9}.
! Here is a list of each supported architecture and their supported
! implementations.
! @smallexample
! v7: cypress
! v8: supersparc, hypersparc
! sparclite: f930, f934, sparclite86x
! sparclet: tsc701
! v9: ultrasparc, ultrasparc3
! @end smallexample
! By default (unless configured otherwise), GCC generates code for the V7
! variant of the SPARC architecture. With @option{-mcpu=cypress}, the compiler
! additionally optimizes it for the Cypress CY7C602 chip, as used in the
! SPARCStation/SPARCServer 3xx series. This is also appropriate for the older
! SPARCStation 1, 2, IPX etc.
! With @option{-mcpu=v8}, GCC generates code for the V8 variant of the SPARC
! architecture. The only difference from V7 code is that the compiler emits
! the integer multiply and integer divide instructions which exist in SPARC-V8
! but not in SPARC-V7. With @option{-mcpu=supersparc}, the compiler additionally
! optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and
! 2000 series.
! With @option{-mcpu=sparclite}, GCC generates code for the SPARClite variant of
! the SPARC architecture. This adds the integer multiply, integer divide step
! and scan (@code{ffs}) instructions which exist in SPARClite but not in SPARC-V7.
! With @option{-mcpu=f930}, the compiler additionally optimizes it for the
! Fujitsu MB86930 chip, which is the original SPARClite, with no FPU. With
! @option{-mcpu=f934}, the compiler additionally optimizes it for the Fujitsu
! MB86934 chip, which is the more recent SPARClite with FPU.
! With @option{-mcpu=sparclet}, GCC generates code for the SPARClet variant of
! the SPARC architecture. This adds the integer multiply, multiply/accumulate,
! integer divide step and scan (@code{ffs}) instructions which exist in SPARClet
! but not in SPARC-V7. With @option{-mcpu=tsc701}, the compiler additionally
! optimizes it for the TEMIC SPARClet chip.
! With @option{-mcpu=v9}, GCC generates code for the V9 variant of the SPARC
! architecture. This adds 64-bit integer and floating-point move instructions,
! 3 additional floating-point condition code registers and conditional move
! instructions. With @option{-mcpu=ultrasparc}, the compiler additionally
! optimizes it for the Sun UltraSPARC I/II chips. With
! @option{-mcpu=ultrasparc3}, the compiler additionally optimizes it for the
! Sun UltraSPARC III chip.
! @item -mtune=@var{cpu_type}
@opindex mtune
! Set the instruction scheduling parameters for machine type
! @var{cpu_type}, but do not set the instruction set or register set that the
! option @option{-mcpu=@var{cpu_type}} would.
!
! The same values for @option{-mcpu=@var{cpu_type}} can be used for
! @option{-mtune=@var{cpu_type}}, but the only useful values are those
! that select a particular cpu implementation. Those are @samp{cypress},
! @samp{supersparc}, @samp{hypersparc}, @samp{f930}, @samp{f934},
! @samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc}, and
! @samp{ultrasparc3}.
!
! @item -mv8plus
! @itemx -mno-v8plus
! @opindex mv8plus
! @opindex mno-v8plus
! With @option{-mv8plus}, GCC generates code for the SPARC-V8+ ABI. The
! difference from the V8 ABI is that the global and out registers are
! considered 64-bit wide. This is enabled by default on Solaris in 32-bit
! mode for all SPARC-V9 processors.
! @item -mvis
! @itemx -mno-vis
! @opindex mvis
! @opindex mno-vis
! With @option{-mvis}, GCC generates code that takes advantage of the UltraSPARC
! Visual Instruction Set extensions. The default is @option{-mno-vis}.
! @end table
! These @samp{-m} options are supported in addition to the above
! on SPARC-V9 processors in 64-bit environments:
! @table @gcctabopt
! @item -mlittle-endian
! @opindex mlittle-endian
! Generate code for a processor running in little-endian mode. It is only
! available for a few configurations and most notably not on Solaris.
! @item -m32
! @itemx -m64
! @opindex m32
! @opindex m64
! Generate code for a 32-bit or 64-bit environment.
! The 32-bit environment sets int, long and pointer to 32 bits.
! The 64-bit environment sets int to 32 bits and long and pointer
! to 64 bits.
! @item -mcmodel=medlow
! @opindex mcmodel=medlow
! Generate code for the Medium/Low code model: 64-bit addresses, programs
! must be linked in the low 32 bits of memory. Programs can be statically
! or dynamically linked.
! @item -mcmodel=medmid
! @opindex mcmodel=medmid
! Generate code for the Medium/Middle code model: 64-bit addresses, programs
! must be linked in the low 44 bits of memory, the text and data segments must
! be less than 2GB in size and the data segment must be located within 2GB of
! the text segment.
! @item -mcmodel=medany
! @opindex mcmodel=medany
! Generate code for the Medium/Anywhere code model: 64-bit addresses, programs
! may be linked anywhere in memory, the text and data segments must be less
! than 2GB in size and the data segment must be located within 2GB of the
! text segment.
! @item -mcmodel=embmedany
! @opindex mcmodel=embmedany
! Generate code for the Medium/Anywhere code model for embedded systems:
! 64-bit addresses, the text and data segments must be less than 2GB in
! size, both starting anywhere in memory (determined at link time). The
! global register %g4 points to the base of the data segment. Programs
! are statically linked and PIC is not supported.
! @item -mstack-bias
! @itemx -mno-stack-bias
! @opindex mstack-bias
! @opindex mno-stack-bias
! With @option{-mstack-bias}, GCC assumes that the stack pointer, and
! frame pointer if present, are offset by @minus{}2047 which must be added back
! when making stack frame references. This is the default in 64-bit mode.
! Otherwise, assume no such offset is present.
! @end table
! @node ARM Options
! @subsection ARM Options
! @cindex ARM options
! These @samp{-m} options are defined for Advanced RISC Machines (ARM)
! architectures:
! @table @gcctabopt
! @item -mabi=@var{name}
! @opindex mabi
! Generate code for the specified ABI. Permissible values are: @samp{apcs-gnu},
! @samp{atpcs}, @samp{aapcs} and @samp{iwmmxt}.
! @item -mapcs-frame
! @opindex mapcs-frame
! Generate a stack frame that is compliant with the ARM Procedure Call
! Standard for all functions, even if this is not strictly necessary for
! correct execution of the code. Specifying @option{-fomit-frame-pointer}
! with this option will cause the stack frames not to be generated for
! leaf functions. The default is @option{-mno-apcs-frame}.
! @item -mapcs
! @opindex mapcs
! This is a synonym for @option{-mapcs-frame}.
! @ignore
! @c not currently implemented
! @item -mapcs-stack-check
! @opindex mapcs-stack-check
! Generate code to check the amount of stack space available upon entry to
! every function (that actually uses some stack space). If there is
! insufficient space available then either the function
! @samp{__rt_stkovf_split_small} or @samp{__rt_stkovf_split_big} will be
! called, depending upon the amount of stack space required. The run time
! system is required to provide these functions. The default is
! @option{-mno-apcs-stack-check}, since this produces smaller code.
! @c not currently implemented
! @item -mapcs-float
! @opindex mapcs-float
! Pass floating point arguments using the float point registers. This is
! one of the variants of the APCS@. This option is recommended if the
! target hardware has a floating point unit or if a lot of floating point
! arithmetic is going to be performed by the code. The default is
! @option{-mno-apcs-float}, since integer only code is slightly increased in
! size if @option{-mapcs-float} is used.
! @c not currently implemented
! @item -mapcs-reentrant
! @opindex mapcs-reentrant
! Generate reentrant, position independent code. The default is
! @option{-mno-apcs-reentrant}.
! @end ignore
! @item -mthumb-interwork
! @opindex mthumb-interwork
! Generate code which supports calling between the ARM and Thumb
! instruction sets. Without this option the two instruction sets cannot
! be reliably used inside one program. The default is
! @option{-mno-thumb-interwork}, since slightly larger code is generated
! when @option{-mthumb-interwork} is specified.
! @item -mno-sched-prolog
! @opindex mno-sched-prolog
! Prevent the reordering of instructions in the function prolog, or the
! merging of those instruction with the instructions in the function's
! body. This means that all functions will start with a recognizable set
! of instructions (or in fact one of a choice from a small set of
! different function prologues), and this information can be used to
! locate the start if functions inside an executable piece of code. The
! default is @option{-msched-prolog}.
! @item -mhard-float
! @opindex mhard-float
! Generate output containing floating point instructions. This is the
! default.
! @item -msoft-float
@opindex msoft-float
! Generate output containing library calls for floating point.
! @strong{Warning:} the requisite libraries are not available for all ARM
! targets. Normally the facilities of the machine's usual C compiler are
! used, but this cannot be done directly in cross-compilation. You must make
! your own arrangements to provide suitable library functions for
! cross-compilation.
! @option{-msoft-float} changes the calling convention in the output file;
! therefore, it is only useful if you compile @emph{all} of a program with
! this option. In particular, you need to compile @file{libgcc.a}, the
! library that comes with GCC, with @option{-msoft-float} in order for
! this to work.
! @item -mfloat-abi=@var{name}
! @opindex mfloat-abi
! Specifies which ABI to use for floating point values. Permissible values
! are: @samp{soft}, @samp{softfp} and @samp{hard}.
! @samp{soft} and @samp{hard} are equivalent to @option{-msoft-float}
! and @option{-mhard-float} respectively. @samp{softfp} allows the generation
! of floating point instructions, but still uses the soft-float calling
! conventions.
! @item -mlittle-endian
! @opindex mlittle-endian
! Generate code for a processor running in little-endian mode. This is
! the default for all standard configurations.
! @item -mbig-endian
! @opindex mbig-endian
! Generate code for a processor running in big-endian mode; the default is
! to compile code for a little-endian processor.
! @item -mwords-little-endian
! @opindex mwords-little-endian
! This option only applies when generating code for big-endian processors.
! Generate code for a little-endian word order but a big-endian byte
! order. That is, a byte order of the form @samp{32107654}. Note: this
! option should only be used if you require compatibility with code for
! big-endian ARM processors generated by versions of the compiler prior to
! 2.8.
! @item -mcpu=@var{name}
! @opindex mcpu
! This specifies the name of the target ARM processor. GCC uses this name
! to determine what kind of instructions it can emit when generating
! assembly code. Permissible names are: @samp{arm2}, @samp{arm250},
! @samp{arm3}, @samp{arm6}, @samp{arm60}, @samp{arm600}, @samp{arm610},
! @samp{arm620}, @samp{arm7}, @samp{arm7m}, @samp{arm7d}, @samp{arm7dm},
! @samp{arm7di}, @samp{arm7dmi}, @samp{arm70}, @samp{arm700},
! @samp{arm700i}, @samp{arm710}, @samp{arm710c}, @samp{arm7100},
! @samp{arm7500}, @samp{arm7500fe}, @samp{arm7tdmi}, @samp{arm8},
! @samp{strongarm}, @samp{strongarm110}, @samp{strongarm1100},
! @samp{arm8}, @samp{arm810}, @samp{arm9}, @samp{arm9e}, @samp{arm920},
! @samp{arm920t}, @samp{arm926ejs}, @samp{arm940t}, @samp{arm9tdmi},
! @samp{arm10tdmi}, @samp{arm1020t}, @samp{arm1026ejs},
! @samp{arm1136js}, @samp{arm1136jfs} ,@samp{xscale}, @samp{iwmmxt},
! @samp{ep9312}.
! @itemx -mtune=@var{name}
! @opindex mtune
! This option is very similar to the @option{-mcpu=} option, except that
! instead of specifying the actual target processor type, and hence
! restricting which instructions can be used, it specifies that GCC should
! tune the performance of the code as if the target were of the type
! specified in this option, but still choosing the instructions that it
! will generate based on the cpu specified by a @option{-mcpu=} option.
! For some ARM implementations better performance can be obtained by using
! this option.
! @item -march=@var{name}
! @opindex march
! This specifies the name of the target ARM architecture. GCC uses this
! name to determine what kind of instructions it can emit when generating
! assembly code. This option can be used in conjunction with or instead
! of the @option{-mcpu=} option. Permissible names are: @samp{armv2},
! @samp{armv2a}, @samp{armv3}, @samp{armv3m}, @samp{armv4}, @samp{armv4t},
! @samp{armv5}, @samp{armv5t}, @samp{armv5te}, @samp{armv6}, @samp{armv6j},
! @samp{iwmmxt}, @samp{ep9312}.
! @item -mfpu=@var{name}
! @itemx -mfpe=@var{number}
! @itemx -mfp=@var{number}
! @opindex mfpu
! @opindex mfpe
! @opindex mfp
! This specifies what floating point hardware (or hardware emulation) is
! available on the target. Permissible names are: @samp{fpa}, @samp{fpe2},
! @samp{fpe3}, @samp{maverick}, @samp{vfp}. @option{-mfp} and @option{-mfpe}
! are synonyms for @option{-mfpu}=@samp{fpe}@var{number}, for compatibility
! with older versions of GCC@.
! If @option{-msoft-float} is specified this specifies the format of
! floating point values.
! @item -mstructure-size-boundary=@var{n}
! @opindex mstructure-size-boundary
! The size of all structures and unions will be rounded up to a multiple
! of the number of bits set by this option. Permissible values are 8, 32
! and 64. The default value varies for different toolchains. For the COFF
! targeted toolchain the default value is 8. A value of 64 is only allowed
! if the underlying ABI supports it.
! Specifying the larger number can produce faster, more efficient code, but
! can also increase the size of the program. Different values are potentially
! incompatible. Code compiled with one value cannot necessarily expect to
! work with code or libraries compiled with another value, if they exchange
! information using structures or unions.
! @item -mabort-on-noreturn
! @opindex mabort-on-noreturn
! Generate a call to the function @code{abort} at the end of a
! @code{noreturn} function. It will be executed if the function tries to
! return.
! @item -mlong-calls
! @itemx -mno-long-calls
! @opindex mlong-calls
! @opindex mno-long-calls
! Tells the compiler to perform function calls by first loading the
! address of the function into a register and then performing a subroutine
! call on this register. This switch is needed if the target function
! will lie outside of the 64 megabyte addressing range of the offset based
! version of subroutine call instruction.
! Even if this switch is enabled, not all function calls will be turned
! into long calls. The heuristic is that static functions, functions
! which have the @samp{short-call} attribute, functions that are inside
! the scope of a @samp{#pragma no_long_calls} directive and functions whose
! definitions have already been compiled within the current compilation
! unit, will not be turned into long calls. The exception to this rule is
! that weak function definitions, functions with the @samp{long-call}
! attribute or the @samp{section} attribute, and functions that are within
! the scope of a @samp{#pragma long_calls} directive, will always be
! turned into long calls.
! This feature is not enabled by default. Specifying
! @option{-mno-long-calls} will restore the default behavior, as will
! placing the function calls within the scope of a @samp{#pragma
! long_calls_off} directive. Note these switches have no effect on how
! the compiler generates code to handle function calls via function
! pointers.
! @item -mnop-fun-dllimport
! @opindex mnop-fun-dllimport
! Disable support for the @code{dllimport} attribute.
! @item -msingle-pic-base
! @opindex msingle-pic-base
! Treat the register used for PIC addressing as read-only, rather than
! loading it in the prologue for each function. The run-time system is
! responsible for initializing this register with an appropriate value
! before execution begins.
! @item -mpic-register=@var{reg}
! @opindex mpic-register
! Specify the register to be used for PIC addressing. The default is R10
! unless stack-checking is enabled, when R9 is used.
! @item -mcirrus-fix-invalid-insns
! @opindex mcirrus-fix-invalid-insns
! @opindex mno-cirrus-fix-invalid-insns
! Insert NOPs into the instruction stream to in order to work around
! problems with invalid Maverick instruction combinations. This option
! is only valid if the @option{-mcpu=ep9312} option has been used to
! enable generation of instructions for the Cirrus Maverick floating
! point co-processor. This option is not enabled by default, since the
! problem is only present in older Maverick implementations. The default
! can be re-enabled by use of the @option{-mno-cirrus-fix-invalid-insns}
! switch.
! @item -mpoke-function-name
! @opindex mpoke-function-name
! Write the name of each function into the text section, directly
! preceding the function prologue. The generated code is similar to this:
! @smallexample
! t0
! .ascii "arm_poke_function_name", 0
! .align
! t1
! .word 0xff000000 + (t1 - t0)
! arm_poke_function_name
! mov ip, sp
! stmfd sp!, @{fp, ip, lr, pc@}
! sub fp, ip, #4
! @end smallexample
! When performing a stack backtrace, code can inspect the value of
! @code{pc} stored at @code{fp + 0}. If the trace function then looks at
! location @code{pc - 12} and the top 8 bits are set, then we know that
! there is a function name embedded immediately preceding this location
! and has length @code{((pc[-3]) & 0xff000000)}.
! @item -mthumb
! @opindex mthumb
! Generate code for the 16-bit Thumb instruction set. The default is to
! use the 32-bit ARM instruction set.
! @item -mtpcs-frame
! @opindex mtpcs-frame
! Generate a stack frame that is compliant with the Thumb Procedure Call
! Standard for all non-leaf functions. (A leaf function is one that does
! not call any other functions.) The default is @option{-mno-tpcs-frame}.
! @item -mtpcs-leaf-frame
! @opindex mtpcs-leaf-frame
! Generate a stack frame that is compliant with the Thumb Procedure Call
! Standard for all leaf functions. (A leaf function is one that does
! not call any other functions.) The default is @option{-mno-apcs-leaf-frame}.
! @item -mcallee-super-interworking
! @opindex mcallee-super-interworking
! Gives all externally visible functions in the file being compiled an ARM
! instruction set header which switches to Thumb mode before executing the
! rest of the function. This allows these functions to be called from
! non-interworking code.
! @item -mcaller-super-interworking
! @opindex mcaller-super-interworking
! Allows calls via function pointers (including virtual functions) to
! execute correctly regardless of whether the target code has been
! compiled for interworking or not. There is a small overhead in the cost
! of executing a function pointer if this option is enabled.
! @end table
! @node MN10300 Options
! @subsection MN10300 Options
! @cindex MN10300 options
! These @option{-m} options are defined for Matsushita MN10300 architectures:
! @table @gcctabopt
! @item -mmult-bug
! @opindex mmult-bug
! Generate code to avoid bugs in the multiply instructions for the MN10300
! processors. This is the default.
! @item -mno-mult-bug
! @opindex mno-mult-bug
! Do not generate code to avoid bugs in the multiply instructions for the
! MN10300 processors.
! @item -mam33
! @opindex mam33
! Generate code which uses features specific to the AM33 processor.
! @item -mno-am33
! @opindex mno-am33
! Do not generate code which uses features specific to the AM33 processor. This
! is the default.
! @item -mno-crt0
! @opindex mno-crt0
! Do not link in the C run-time initialization object file.
! @item -mrelax
! @opindex mrelax
! Indicate to the linker that it should perform a relaxation optimization pass
! to shorten branches, calls and absolute memory addresses. This option only
! has an effect when used on the command line for the final link step.
! This option makes symbolic debugging impossible.
@end table
! @node M32R/D Options
! @subsection M32R/D Options
! @cindex M32R/D options
! These @option{-m} options are defined for Renesas M32R/D architectures:
! @table @gcctabopt
! @item -m32r2
! @opindex m32r2
! Generate code for the M32R/2@.
! @item -m32rx
! @opindex m32rx
! Generate code for the M32R/X@.
! @item -m32r
! @opindex m32r
! Generate code for the M32R@. This is the default.
! @item -mmodel=small
! @opindex mmodel=small
! Assume all objects live in the lower 16MB of memory (so that their addresses
! can be loaded with the @code{ld24} instruction), and assume all subroutines
! are reachable with the @code{bl} instruction.
! This is the default.
! The addressability of a particular object can be set with the
! @code{model} attribute.
! @item -mmodel=medium
! @opindex mmodel=medium
! Assume objects may be anywhere in the 32-bit address space (the compiler
! will generate @code{seth/add3} instructions to load their addresses), and
! assume all subroutines are reachable with the @code{bl} instruction.
! @item -mmodel=large
! @opindex mmodel=large
! Assume objects may be anywhere in the 32-bit address space (the compiler
! will generate @code{seth/add3} instructions to load their addresses), and
! assume subroutines may not be reachable with the @code{bl} instruction
! (the compiler will generate the much slower @code{seth/add3/jl}
! instruction sequence).
! @item -msdata=none
! @opindex msdata=none
! Disable use of the small data area. Variables will be put into
! one of @samp{.data}, @samp{bss}, or @samp{.rodata} (unless the
! @code{section} attribute has been specified).
! This is the default.
! The small data area consists of sections @samp{.sdata} and @samp{.sbss}.
! Objects may be explicitly put in the small data area with the
! @code{section} attribute using one of these sections.
! @item -msdata=sdata
! @opindex msdata=sdata
! Put small global and static data in the small data area, but do not
! generate special code to reference them.
! @item -msdata=use
! @opindex msdata=use
! Put small global and static data in the small data area, and generate
! special instructions to reference them.
! @item -G @var{num}
! @opindex G
! @cindex smaller data references
! Put global and static objects less than or equal to @var{num} bytes
! into the small data or bss sections instead of the normal data or bss
! sections. The default value of @var{num} is 8.
! The @option{-msdata} option must be set to one of @samp{sdata} or @samp{use}
! for this option to have any effect.
! All modules should be compiled with the same @option{-G @var{num}} value.
! Compiling with different values of @var{num} may or may not work; if it
! doesn't the linker will give an error message---incorrect code will not be
! generated.
! @item -mdebug
! @opindex mdebug
! Makes the M32R specific code in the compiler display some statistics
! that might help in debugging programs.
! @item -malign-loops
! @opindex malign-loops
! Align all loops to a 32-byte boundary.
! @item -mno-align-loops
! @opindex mno-align-loops
! Do not enforce a 32-byte alignment for loops. This is the default.
! @item -missue-rate=@var{number}
! @opindex missue-rate=@var{number}
! Issue @var{number} instructions per cycle. @var{number} can only be 1
! or 2.
! @item -mbranch-cost=@var{number}
! @opindex mbranch-cost=@var{number}
! @var{number} can only be 1 or 2. If it is 1 then branches will be
! preferred over conditional code, if it is 2, then the opposite will
! apply.
! @item -mflush-trap=@var{number}
! @opindex mflush-trap=@var{number}
! Specifies the trap number to use to flush the cache. The default is
! 12. Valid numbers are between 0 and 15 inclusive.
! @item -mno-flush-trap
! @opindex mno-flush-trap
! Specifies that the cache cannot be flushed by using a trap.
! @item -mflush-func=@var{name}
! @opindex mflush-func=@var{name}
! Specifies the name of the operating system function to call to flush
! the cache. The default is @emph{_flush_cache}, but a function call
! will only be used if a trap is not available.
! @item -mno-flush-func
! @opindex mno-flush-func
! Indicates that there is no OS function for flushing the cache.
! @end table
! @node RS/6000 and PowerPC Options
! @subsection IBM RS/6000 and PowerPC Options
! @cindex RS/6000 and PowerPC Options
! @cindex IBM RS/6000 and PowerPC Options
! These @samp{-m} options are defined for the IBM RS/6000 and PowerPC:
! @table @gcctabopt
! @item -mpower
! @itemx -mno-power
! @itemx -mpower2
! @itemx -mno-power2
! @itemx -mpowerpc
! @itemx -mno-powerpc
! @itemx -mpowerpc-gpopt
! @itemx -mno-powerpc-gpopt
! @itemx -mpowerpc-gfxopt
! @itemx -mno-powerpc-gfxopt
! @itemx -mpowerpc64
! @itemx -mno-powerpc64
! @opindex mpower
! @opindex mno-power
! @opindex mpower2
! @opindex mno-power2
! @opindex mpowerpc
! @opindex mno-powerpc
! @opindex mpowerpc-gpopt
! @opindex mno-powerpc-gpopt
! @opindex mpowerpc-gfxopt
! @opindex mno-powerpc-gfxopt
! @opindex mpowerpc64
! @opindex mno-powerpc64
! GCC supports two related instruction set architectures for the
! RS/6000 and PowerPC@. The @dfn{POWER} instruction set are those
! instructions supported by the @samp{rios} chip set used in the original
! RS/6000 systems and the @dfn{PowerPC} instruction set is the
! architecture of the Motorola MPC5xx, MPC6xx, MPC8xx microprocessors, and
! the IBM 4xx microprocessors.
! Neither architecture is a subset of the other. However there is a
! large common subset of instructions supported by both. An MQ
! register is included in processors supporting the POWER architecture.
! You use these options to specify which instructions are available on the
! processor you are using. The default value of these options is
! determined when configuring GCC@. Specifying the
! @option{-mcpu=@var{cpu_type}} overrides the specification of these
! options. We recommend you use the @option{-mcpu=@var{cpu_type}} option
! rather than the options listed above.
! The @option{-mpower} option allows GCC to generate instructions that
! are found only in the POWER architecture and to use the MQ register.
! Specifying @option{-mpower2} implies @option{-power} and also allows GCC
! to generate instructions that are present in the POWER2 architecture but
! not the original POWER architecture.
! The @option{-mpowerpc} option allows GCC to generate instructions that
! are found only in the 32-bit subset of the PowerPC architecture.
! Specifying @option{-mpowerpc-gpopt} implies @option{-mpowerpc} and also allows
! GCC to use the optional PowerPC architecture instructions in the
! General Purpose group, including floating-point square root. Specifying
! @option{-mpowerpc-gfxopt} implies @option{-mpowerpc} and also allows GCC to
! use the optional PowerPC architecture instructions in the Graphics
! group, including floating-point select.
! The @option{-mpowerpc64} option allows GCC to generate the additional
! 64-bit instructions that are found in the full PowerPC64 architecture
! and to treat GPRs as 64-bit, doubleword quantities. GCC defaults to
! @option{-mno-powerpc64}.
! If you specify both @option{-mno-power} and @option{-mno-powerpc}, GCC
! will use only the instructions in the common subset of both
! architectures plus some special AIX common-mode calls, and will not use
! the MQ register. Specifying both @option{-mpower} and @option{-mpowerpc}
! permits GCC to use any instruction from either architecture and to
! allow use of the MQ register; specify this for the Motorola MPC601.
! @item -mnew-mnemonics
! @itemx -mold-mnemonics
! @opindex mnew-mnemonics
! @opindex mold-mnemonics
! Select which mnemonics to use in the generated assembler code. With
! @option{-mnew-mnemonics}, GCC uses the assembler mnemonics defined for
! the PowerPC architecture. With @option{-mold-mnemonics} it uses the
! assembler mnemonics defined for the POWER architecture. Instructions
! defined in only one architecture have only one mnemonic; GCC uses that
! mnemonic irrespective of which of these options is specified.
! GCC defaults to the mnemonics appropriate for the architecture in
! use. Specifying @option{-mcpu=@var{cpu_type}} sometimes overrides the
! value of these option. Unless you are building a cross-compiler, you
! should normally not specify either @option{-mnew-mnemonics} or
! @option{-mold-mnemonics}, but should instead accept the default.
! @item -mcpu=@var{cpu_type}
! @opindex mcpu
! Set architecture type, register usage, choice of mnemonics, and
! instruction scheduling parameters for machine type @var{cpu_type}.
! Supported values for @var{cpu_type} are @samp{401}, @samp{403},
! @samp{405}, @samp{405fp}, @samp{440}, @samp{440fp}, @samp{505},
! @samp{601}, @samp{602}, @samp{603}, @samp{603e}, @samp{604},
! @samp{604e}, @samp{620}, @samp{630}, @samp{740}, @samp{7400},
! @samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823},
! @samp{860}, @samp{970}, @samp{common}, @samp{ec603e}, @samp{G3},
! @samp{G4}, @samp{G5}, @samp{power}, @samp{power2}, @samp{power3},
! @samp{power4}, @samp{power5}, @samp{powerpc}, @samp{powerpc64},
! @samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64a}.
! @option{-mcpu=common} selects a completely generic processor. Code
! generated under this option will run on any POWER or PowerPC processor.
! GCC will use only the instructions in the common subset of both
! architectures, and will not use the MQ register. GCC assumes a generic
! processor model for scheduling purposes.
! @option{-mcpu=power}, @option{-mcpu=power2}, @option{-mcpu=powerpc}, and
! @option{-mcpu=powerpc64} specify generic POWER, POWER2, pure 32-bit
! PowerPC (i.e., not MPC601), and 64-bit PowerPC architecture machine
! types, with an appropriate, generic processor model assumed for
! scheduling purposes.
! The other options specify a specific processor. Code generated under
! those options will run best on that processor, and may not run at all on
! others.
! The @option{-mcpu} options automatically enable or disable the
! following options: @option{-maltivec}, @option{-mhard-float},
! @option{-mmfcrf}, @option{-mmultiple}, @option{-mnew-mnemonics},
! @option{-mpower}, @option{-mpower2}, @option{-mpowerpc64},
! @option{-mpowerpc-gpopt}, @option{-mpowerpc-gfxopt},
! @option{-mstring}. The particular options set for any particular CPU
! will vary between compiler versions, depending on what setting seems
! to produce optimal code for that CPU; it doesn't necessarily reflect
! the actual hardware's capabilities. If you wish to set an individual
! option to a particular value, you may specify it after the
! @option{-mcpu} option, like @samp{-mcpu=970 -mno-altivec}.
! On AIX, the @option{-maltivec} and @option{-mpowerpc64} options are
! not enabled or disabled by the @option{-mcpu} option at present, since
! AIX does not have full support for these options. You may still
! enable or disable them individually if you're sure it'll work in your
! environment.
! @item -mtune=@var{cpu_type}
! @opindex mtune
! Set the instruction scheduling parameters for machine type
! @var{cpu_type}, but do not set the architecture type, register usage, or
! choice of mnemonics, as @option{-mcpu=@var{cpu_type}} would. The same
! values for @var{cpu_type} are used for @option{-mtune} as for
! @option{-mcpu}. If both are specified, the code generated will use the
! architecture, registers, and mnemonics set by @option{-mcpu}, but the
! scheduling parameters set by @option{-mtune}.
! @item -maltivec
! @itemx -mno-altivec
! @opindex maltivec
! @opindex mno-altivec
! These switches enable or disable the use of built-in functions that
! allow access to the AltiVec instruction set. You may also need to set
! @option{-mabi=altivec} to adjust the current ABI with AltiVec ABI
! enhancements.
! @item -mabi=spe
! @opindex mabi=spe
! Extend the current ABI with SPE ABI extensions. This does not change
! the default ABI, instead it adds the SPE ABI extensions to the current
! ABI@.
! @item -mabi=no-spe
! @opindex mabi=no-spe
! Disable Booke SPE ABI extensions for the current ABI.
! @item -misel=@var{yes/no}
! @itemx -misel
! @opindex misel
! This switch enables or disables the generation of ISEL instructions.
! @item -mspe=@var{yes/no}
! @itemx -mspe
! @opindex mspe
! This switch enables or disables the generation of SPE simd
! instructions.
! @item -mfloat-gprs=@var{yes/no}
! @itemx -mfloat-gprs
! @opindex mfloat-gprs
! This switch enables or disables the generation of floating point
! operations on the general purpose registers for architectures that
! support it. This option is currently only available on the MPC8540.
! @item -mfull-toc
! @itemx -mno-fp-in-toc
! @itemx -mno-sum-in-toc
! @itemx -mminimal-toc
! @opindex mfull-toc
! @opindex mno-fp-in-toc
! @opindex mno-sum-in-toc
! @opindex mminimal-toc
! Modify generation of the TOC (Table Of Contents), which is created for
! every executable file. The @option{-mfull-toc} option is selected by
! default. In that case, GCC will allocate at least one TOC entry for
! each unique non-automatic variable reference in your program. GCC
! will also place floating-point constants in the TOC@. However, only
! 16,384 entries are available in the TOC@.
! If you receive a linker error message that saying you have overflowed
! the available TOC space, you can reduce the amount of TOC space used
! with the @option{-mno-fp-in-toc} and @option{-mno-sum-in-toc} options.
! @option{-mno-fp-in-toc} prevents GCC from putting floating-point
! constants in the TOC and @option{-mno-sum-in-toc} forces GCC to
! generate code to calculate the sum of an address and a constant at
! run-time instead of putting that sum into the TOC@. You may specify one
! or both of these options. Each causes GCC to produce very slightly
! slower and larger code at the expense of conserving TOC space.
! If you still run out of space in the TOC even when you specify both of
! these options, specify @option{-mminimal-toc} instead. This option causes
! GCC to make only one TOC entry for every file. When you specify this
! option, GCC will produce code that is slower and larger but which
! uses extremely little TOC space. You may wish to use this option
! only on files that contain less frequently executed code.
! @item -maix64
! @itemx -maix32
! @opindex maix64
! @opindex maix32
! Enable 64-bit AIX ABI and calling convention: 64-bit pointers, 64-bit
! @code{long} type, and the infrastructure needed to support them.
! Specifying @option{-maix64} implies @option{-mpowerpc64} and
! @option{-mpowerpc}, while @option{-maix32} disables the 64-bit ABI and
! implies @option{-mno-powerpc64}. GCC defaults to @option{-maix32}.
! @item -mxl-call
! @itemx -mno-xl-call
! @opindex mxl-call
! @opindex mno-xl-call
! On AIX, pass floating-point arguments to prototyped functions beyond the
! register save area (RSA) on the stack in addition to argument FPRs. The
! AIX calling convention was extended but not initially documented to
! handle an obscure K&R C case of calling a function that takes the
! address of its arguments with fewer arguments than declared. AIX XL
! compilers access floating point arguments which do not fit in the
! RSA from the stack when a subroutine is compiled without
! optimization. Because always storing floating-point arguments on the
! stack is inefficient and rarely needed, this option is not enabled by
! default and only is necessary when calling subroutines compiled by AIX
! XL compilers without optimization.
! @item -mpe
! @opindex mpe
! Support @dfn{IBM RS/6000 SP} @dfn{Parallel Environment} (PE)@. Link an
! application written to use message passing with special startup code to
! enable the application to run. The system must have PE installed in the
! standard location (@file{/usr/lpp/ppe.poe/}), or the @file{specs} file
! must be overridden with the @option{-specs=} option to specify the
! appropriate directory location. The Parallel Environment does not
! support threads, so the @option{-mpe} option and the @option{-pthread}
! option are incompatible.
! @item -malign-natural
! @itemx -malign-power
! @opindex malign-natural
! @opindex malign-power
! On AIX, Darwin, and 64-bit PowerPC GNU/Linux, the option
! @option{-malign-natural} overrides the ABI-defined alignment of larger
! types, such as floating-point doubles, on their natural size-based boundary.
! The option @option{-malign-power} instructs GCC to follow the ABI-specified
! alignment rules. GCC defaults to the standard alignment defined in the ABI.
! @item -msoft-float
! @itemx -mhard-float
! @opindex msoft-float
! @opindex mhard-float
! Generate code that does not use (uses) the floating-point register set.
! Software floating point emulation is provided if you use the
! @option{-msoft-float} option, and pass the option to GCC when linking.
! @item -mmultiple
! @itemx -mno-multiple
! @opindex mmultiple
! @opindex mno-multiple
! Generate code that uses (does not use) the load multiple word
! instructions and the store multiple word instructions. These
! instructions are generated by default on POWER systems, and not
! generated on PowerPC systems. Do not use @option{-mmultiple} on little
! endian PowerPC systems, since those instructions do not work when the
! processor is in little endian mode. The exceptions are PPC740 and
! PPC750 which permit the instructions usage in little endian mode.
! @item -mstring
! @itemx -mno-string
! @opindex mstring
! @opindex mno-string
! Generate code that uses (does not use) the load string instructions
! and the store string word instructions to save multiple registers and
! do small block moves. These instructions are generated by default on
! POWER systems, and not generated on PowerPC systems. Do not use
! @option{-mstring} on little endian PowerPC systems, since those
! instructions do not work when the processor is in little endian mode.
! The exceptions are PPC740 and PPC750 which permit the instructions
! usage in little endian mode.
! @item -mupdate
! @itemx -mno-update
! @opindex mupdate
! @opindex mno-update
! Generate code that uses (does not use) the load or store instructions
! that update the base register to the address of the calculated memory
! location. These instructions are generated by default. If you use
! @option{-mno-update}, there is a small window between the time that the
! stack pointer is updated and the address of the previous frame is
! stored, which means code that walks the stack frame across interrupts or
! signals may get corrupted data.
! @item -mfused-madd
! @itemx -mno-fused-madd
! @opindex mfused-madd
! @opindex mno-fused-madd
! Generate code that uses (does not use) the floating point multiply and
! accumulate instructions. These instructions are generated by default if
! hardware floating is used.
! @item -mno-bit-align
! @itemx -mbit-align
! @opindex mno-bit-align
! @opindex mbit-align
! On System V.4 and embedded PowerPC systems do not (do) force structures
! and unions that contain bit-fields to be aligned to the base type of the
! bit-field.
! For example, by default a structure containing nothing but 8
! @code{unsigned} bit-fields of length 1 would be aligned to a 4 byte
! boundary and have a size of 4 bytes. By using @option{-mno-bit-align},
! the structure would be aligned to a 1 byte boundary and be one byte in
! size.
! @item -mno-strict-align
! @itemx -mstrict-align
! @opindex mno-strict-align
! @opindex mstrict-align
! On System V.4 and embedded PowerPC systems do not (do) assume that
! unaligned memory references will be handled by the system.
! @item -mrelocatable
! @itemx -mno-relocatable
! @opindex mrelocatable
! @opindex mno-relocatable
! On embedded PowerPC systems generate code that allows (does not allow)
! the program to be relocated to a different address at runtime. If you
! use @option{-mrelocatable} on any module, all objects linked together must
! be compiled with @option{-mrelocatable} or @option{-mrelocatable-lib}.
! @item -mrelocatable-lib
! @itemx -mno-relocatable-lib
! @opindex mrelocatable-lib
! @opindex mno-relocatable-lib
! On embedded PowerPC systems generate code that allows (does not allow)
! the program to be relocated to a different address at runtime. Modules
! compiled with @option{-mrelocatable-lib} can be linked with either modules
! compiled without @option{-mrelocatable} and @option{-mrelocatable-lib} or
! with modules compiled with the @option{-mrelocatable} options.
! @item -mno-toc
! @itemx -mtoc
! @opindex mno-toc
! @opindex mtoc
! On System V.4 and embedded PowerPC systems do not (do) assume that
! register 2 contains a pointer to a global area pointing to the addresses
! used in the program.
! @item -mlittle
! @itemx -mlittle-endian
! @opindex mlittle
! @opindex mlittle-endian
! On System V.4 and embedded PowerPC systems compile code for the
! processor in little endian mode. The @option{-mlittle-endian} option is
! the same as @option{-mlittle}.
! @item -mbig
! @itemx -mbig-endian
! @opindex mbig
! @opindex mbig-endian
! On System V.4 and embedded PowerPC systems compile code for the
! processor in big endian mode. The @option{-mbig-endian} option is
! the same as @option{-mbig}.
! @item -mdynamic-no-pic
! @opindex mdynamic-no-pic
! On Darwin and Mac OS X systems, compile code so that it is not
! relocatable, but that its external references are relocatable. The
! resulting code is suitable for applications, but not shared
! libraries.
! @item -mprioritize-restricted-insns=@var{priority}
! @opindex mprioritize-restricted-insns
! This option controls the priority that is assigned to
! dispatch-slot restricted instructions during the second scheduling
! pass. The argument @var{priority} takes the value @var{0/1/2} to assign
! @var{no/highest/second-highest} priority to dispatch slot restricted
! instructions.
! @item -msched-costly-dep=@var{dependence_type}
! @opindex msched-costly-dep
! This option controls which dependences are considered costly
! by the target during instruction scheduling. The argument
! @var{dependence_type} takes one of the following values:
! @var{no}: no dependence is costly,
! @var{all}: all dependences are costly,
! @var{true_store_to_load}: a true dependence from store to load is costly,
! @var{store_to_load}: any dependence from store to load is costly,
! @var{number}: any dependence which latency >= @var{number} is costly.
! @item -minsert-sched-nops=@var{scheme}
! @opindex minsert-sched-nops
! This option controls which nop insertion scheme will be used during
! the second scheduling pass. The argument @var{scheme} takes one of the
! following values:
! @var{no}: Don't insert nops.
! @var{pad}: Pad with nops any dispatch group which has vacant issue slots,
! according to the scheduler's grouping.
! @var{regroup_exact}: Insert nops to force costly dependent insns into
! separate groups. Insert exactly as many nops as needed to force an insn
! to a new group, according to the estimated processor grouping.
! @var{number}: Insert nops to force costly dependent insns into
! separate groups. Insert @var{number} nops to force an insn to a new group.
! @item -mcall-sysv
! @opindex mcall-sysv
! On System V.4 and embedded PowerPC systems compile code using calling
! conventions that adheres to the March 1995 draft of the System V
! Application Binary Interface, PowerPC processor supplement. This is the
! default unless you configured GCC using @samp{powerpc-*-eabiaix}.
! @item -mcall-sysv-eabi
! @opindex mcall-sysv-eabi
! Specify both @option{-mcall-sysv} and @option{-meabi} options.
! @item -mcall-sysv-noeabi
! @opindex mcall-sysv-noeabi
! Specify both @option{-mcall-sysv} and @option{-mno-eabi} options.
! @item -mcall-solaris
! @opindex mcall-solaris
! On System V.4 and embedded PowerPC systems compile code for the Solaris
! operating system.
! @item -mcall-linux
! @opindex mcall-linux
! On System V.4 and embedded PowerPC systems compile code for the
! Linux-based GNU system.
! @item -mcall-gnu
! @opindex mcall-gnu
! On System V.4 and embedded PowerPC systems compile code for the
! Hurd-based GNU system.
! @item -mcall-netbsd
! @opindex mcall-netbsd
! On System V.4 and embedded PowerPC systems compile code for the
! NetBSD operating system.
! @item -maix-struct-return
! @opindex maix-struct-return
! Return all structures in memory (as specified by the AIX ABI)@.
! @item -msvr4-struct-return
! @opindex msvr4-struct-return
! Return structures smaller than 8 bytes in registers (as specified by the
! SVR4 ABI)@.
! @item -mabi=altivec
! @opindex mabi=altivec
! Extend the current ABI with AltiVec ABI extensions. This does not
! change the default ABI, instead it adds the AltiVec ABI extensions to
! the current ABI@.
! @item -mabi=no-altivec
! @opindex mabi=no-altivec
! Disable AltiVec ABI extensions for the current ABI.
! @item -mprototype
! @itemx -mno-prototype
! @opindex mprototype
! @opindex mno-prototype
! On System V.4 and embedded PowerPC systems assume that all calls to
! variable argument functions are properly prototyped. Otherwise, the
! compiler must insert an instruction before every non prototyped call to
! set or clear bit 6 of the condition code register (@var{CR}) to
! indicate whether floating point values were passed in the floating point
! registers in case the function takes a variable arguments. With
! @option{-mprototype}, only calls to prototyped variable argument functions
! will set or clear the bit.
! @item -msim
! @opindex msim
! On embedded PowerPC systems, assume that the startup module is called
! @file{sim-crt0.o} and that the standard C libraries are @file{libsim.a} and
! @file{libc.a}. This is the default for @samp{powerpc-*-eabisim}.
! configurations.
! @item -mmvme
! @opindex mmvme
! On embedded PowerPC systems, assume that the startup module is called
! @file{crt0.o} and the standard C libraries are @file{libmvme.a} and
! @file{libc.a}.
! @item -mads
! @opindex mads
! On embedded PowerPC systems, assume that the startup module is called
! @file{crt0.o} and the standard C libraries are @file{libads.a} and
! @file{libc.a}.
! @item -myellowknife
! @opindex myellowknife
! On embedded PowerPC systems, assume that the startup module is called
! @file{crt0.o} and the standard C libraries are @file{libyk.a} and
! @file{libc.a}.
! @item -mvxworks
! @opindex mvxworks
! On System V.4 and embedded PowerPC systems, specify that you are
! compiling for a VxWorks system.
! @item -mwindiss
! @opindex mwindiss
! Specify that you are compiling for the WindISS simulation environment.
! @item -memb
! @opindex memb
! On embedded PowerPC systems, set the @var{PPC_EMB} bit in the ELF flags
! header to indicate that @samp{eabi} extended relocations are used.
! @item -meabi
! @itemx -mno-eabi
! @opindex meabi
! @opindex mno-eabi
! On System V.4 and embedded PowerPC systems do (do not) adhere to the
! Embedded Applications Binary Interface (eabi) which is a set of
! modifications to the System V.4 specifications. Selecting @option{-meabi}
! means that the stack is aligned to an 8 byte boundary, a function
! @code{__eabi} is called to from @code{main} to set up the eabi
! environment, and the @option{-msdata} option can use both @code{r2} and
! @code{r13} to point to two separate small data areas. Selecting
! @option{-mno-eabi} means that the stack is aligned to a 16 byte boundary,
! do not call an initialization function from @code{main}, and the
! @option{-msdata} option will only use @code{r13} to point to a single
! small data area. The @option{-meabi} option is on by default if you
! configured GCC using one of the @samp{powerpc*-*-eabi*} options.
! @item -msdata=eabi
! @opindex msdata=eabi
! On System V.4 and embedded PowerPC systems, put small initialized
! @code{const} global and static data in the @samp{.sdata2} section, which
! is pointed to by register @code{r2}. Put small initialized
! non-@code{const} global and static data in the @samp{.sdata} section,
! which is pointed to by register @code{r13}. Put small uninitialized
! global and static data in the @samp{.sbss} section, which is adjacent to
! the @samp{.sdata} section. The @option{-msdata=eabi} option is
! incompatible with the @option{-mrelocatable} option. The
! @option{-msdata=eabi} option also sets the @option{-memb} option.
! @item -msdata=sysv
! @opindex msdata=sysv
! On System V.4 and embedded PowerPC systems, put small global and static
! data in the @samp{.sdata} section, which is pointed to by register
! @code{r13}. Put small uninitialized global and static data in the
! @samp{.sbss} section, which is adjacent to the @samp{.sdata} section.
! The @option{-msdata=sysv} option is incompatible with the
! @option{-mrelocatable} option.
! @item -msdata=default
! @itemx -msdata
! @opindex msdata=default
! @opindex msdata
! On System V.4 and embedded PowerPC systems, if @option{-meabi} is used,
! compile code the same as @option{-msdata=eabi}, otherwise compile code the
! same as @option{-msdata=sysv}.
! @item -msdata-data
! @opindex msdata-data
! On System V.4 and embedded PowerPC systems, put small global and static
! data in the @samp{.sdata} section. Put small uninitialized global and
! static data in the @samp{.sbss} section. Do not use register @code{r13}
! to address small data however. This is the default behavior unless
! other @option{-msdata} options are used.
! @item -msdata=none
! @itemx -mno-sdata
! @opindex msdata=none
! @opindex mno-sdata
! On embedded PowerPC systems, put all initialized global and static data
! in the @samp{.data} section, and all uninitialized data in the
! @samp{.bss} section.
! @item -G @var{num}
! @opindex G
! @cindex smaller data references (PowerPC)
! @cindex .sdata/.sdata2 references (PowerPC)
! On embedded PowerPC systems, put global and static items less than or
! equal to @var{num} bytes into the small data or bss sections instead of
! the normal data or bss section. By default, @var{num} is 8. The
! @option{-G @var{num}} switch is also passed to the linker.
! All modules should be compiled with the same @option{-G @var{num}} value.
! @item -mregnames
! @itemx -mno-regnames
! @opindex mregnames
! @opindex mno-regnames
! On System V.4 and embedded PowerPC systems do (do not) emit register
! names in the assembly language output using symbolic forms.
! @item -mlongcall
! @itemx -mno-longcall
! @opindex mlongcall
! @opindex mno-longcall
! Default to making all function calls indirectly, using a register, so
! that functions which reside further than 32 megabytes (33,554,432
! bytes) from the current location can be called. This setting can be
! overridden by the @code{shortcall} function attribute, or by
! @code{#pragma longcall(0)}.
! Some linkers are capable of detecting out-of-range calls and generating
! glue code on the fly. On these systems, long calls are unnecessary and
! generate slower code. As of this writing, the AIX linker can do this,
! as can the GNU linker for PowerPC/64. It is planned to add this feature
! to the GNU linker for 32-bit PowerPC systems as well.
! On Darwin/PPC systems, @code{#pragma longcall} will generate ``jbsr
! callee, L42'', plus a ``branch island'' (glue code). The two target
! addresses represent the callee and the ``branch island.'' The
! Darwin/PPC linker will prefer the first address and generate a ``bl
! callee'' if the PPC ``bl'' instruction will reach the callee directly;
! otherwise, the linker will generate ``bl L42'' to call the ``branch
! island.'' The ``branch island'' is appended to the body of the
! calling function; it computes the full 32-bit address of the callee
! and jumps to it.
! On Mach-O (Darwin) systems, this option directs the compiler emit to
! the glue for every direct call, and the Darwin linker decides whether
! to use or discard it.
! In the future, we may cause GCC to ignore all longcall specifications
! when the linker is known to generate glue.
! @item -pthread
! @opindex pthread
! Adds support for multithreading with the @dfn{pthreads} library.
! This option sets flags for both the preprocessor and linker.
! @end table
! @node Darwin Options
! @subsection Darwin Options
! @cindex Darwin options
! These options are defined for all architectures running the Darwin operating
! system. They are useful for compatibility with other Mac OS compilers.
! @table @gcctabopt
! @item -F@var{dir}
! @opindex F
! Add the framework directory @var{dir} to the head of the list of
! directories to be searched for header files. These directories are
! interleaved with those specified by @option{-I} options and are
! scanned in a left-to-right order.
! A framework directory is a directory with frameworks in it. A
! framework is a directory with a @samp{"Headers"} and/or
! @samp{"PrivateHeaders"} directory contained directly in it that ends
! in @samp{".framework"}. The name of a framework is the name of this
! directory excluding the @samp{".framework"}. Headers associated with
! the framework are found in one of those two directories, with
! @samp{"Headers"} being searched first. A subframework is a framework
! directory that is in a framework's @samp{"Frameworks"} directory.
! Includes of subframework headers can only appear in a header of a
! framework that contains the subframework, or in a sibling subframework
! header. Two subframeworks are siblings if they occur in the same
! framework. A subframework should not have the same name as a
! framework, a warning will be issued if this is violated. Currently a
! subframework cannot have subframeworks, in the future, the mechanism
! may be extended to support this. The standard frameworks can be found
! in @samp{"/System/Library/Frameworks"}, @samp{"/Library/Frameworks"}
! and @samp{"/Local/Library/Frameworks"}. An example include looks like
! @code{#include <Framework/header.h>}, where @samp{Framework} denotes
! the name of the framework and header.h is found in the
! @samp{"PrivateHeaders"} or @samp{"Headers"} directory.
! @item -all_load
! @opindex all_load
! Loads all members of static archive libraries.
! See man ld(1) for more information.
! @item -arch_errors_fatal
! @opindex arch_errors_fatal
! Cause the errors having to do with files that have the wrong architecture
! to be fatal.
! @item -bind_at_load
! @opindex bind_at_load
! Causes the output file to be marked such that the dynamic linker will
! bind all undefined references when the file is loaded or launched.
! @item -bundle
! @opindex bundle
! Produce a Mach-o bundle format file.
! See man ld(1) for more information.
! @item -bundle_loader @var{executable}
! @opindex bundle_loader
! This specifies the @var{executable} that will be loading the build
! output file being linked. See man ld(1) for more information.
! @item -allowable_client @var{client_name}
! @itemx -arch_only
! @itemx -client_name
! @itemx -compatibility_version
! @itemx -current_version
! @itemx -dependency-file
! @itemx -dylib_file
! @itemx -dylinker_install_name
! @itemx -dynamic
! @itemx -dynamiclib
! @itemx -exported_symbols_list
! @itemx -filelist
! @itemx -flat_namespace
! @itemx -force_cpusubtype_ALL
! @itemx -force_flat_namespace
! @itemx -headerpad_max_install_names
! @itemx -image_base
! @itemx -init
! @itemx -install_name
! @itemx -keep_private_externs
! @itemx -multi_module
! @itemx -multiply_defined
! @itemx -multiply_defined_unused
! @itemx -noall_load
! @itemx -nofixprebinding
! @itemx -nomultidefs
! @itemx -noprebind
! @itemx -noseglinkedit
! @itemx -pagezero_size
! @itemx -prebind
! @itemx -prebind_all_twolevel_modules
! @itemx -private_bundle
! @itemx -read_only_relocs
! @itemx -sectalign
! @itemx -sectobjectsymbols
! @itemx -whyload
! @itemx -seg1addr
! @itemx -sectcreate
! @itemx -sectobjectsymbols
! @itemx -sectorder
! @itemx -seg_addr_table
! @itemx -seg_addr_table_filename
! @itemx -seglinkedit
! @itemx -segprot
! @itemx -segs_read_only_addr
! @itemx -segs_read_write_addr
! @itemx -single_module
! @itemx -static
! @itemx -sub_library
! @itemx -sub_umbrella
! @itemx -twolevel_namespace
! @itemx -umbrella
! @itemx -undefined
! @itemx -unexported_symbols_list
! @itemx -weak_reference_mismatches
! @itemx -whatsloaded
! @opindex allowable_client
! @opindex arch_only
! @opindex client_name
! @opindex compatibility_version
! @opindex current_version
! @opindex dependency-file
! @opindex dylib_file
! @opindex dylinker_install_name
! @opindex dynamic
! @opindex dynamiclib
! @opindex exported_symbols_list
! @opindex filelist
! @opindex flat_namespace
! @opindex force_cpusubtype_ALL
! @opindex force_flat_namespace
! @opindex headerpad_max_install_names
! @opindex image_base
! @opindex init
! @opindex install_name
! @opindex keep_private_externs
! @opindex multi_module
! @opindex multiply_defined
! @opindex multiply_defined_unused
! @opindex noall_load
! @opindex nofixprebinding
! @opindex nomultidefs
! @opindex noprebind
! @opindex noseglinkedit
! @opindex pagezero_size
! @opindex prebind
! @opindex prebind_all_twolevel_modules
! @opindex private_bundle
! @opindex read_only_relocs
! @opindex sectalign
! @opindex sectobjectsymbols
! @opindex whyload
! @opindex seg1addr
! @opindex sectcreate
! @opindex sectobjectsymbols
! @opindex sectorder
! @opindex seg_addr_table
! @opindex seg_addr_table_filename
! @opindex seglinkedit
! @opindex segprot
! @opindex segs_read_only_addr
! @opindex segs_read_write_addr
! @opindex single_module
! @opindex static
! @opindex sub_library
! @opindex sub_umbrella
! @opindex twolevel_namespace
! @opindex umbrella
! @opindex undefined
! @opindex unexported_symbols_list
! @opindex weak_reference_mismatches
! @opindex whatsloaded
! These options are available for Darwin linker. Darwin linker man page
! describes them in detail.
! @end table
! @node MIPS Options
! @subsection MIPS Options
! @cindex MIPS options
! @table @gcctabopt
! @item -EB
! @opindex EB
! Generate big-endian code.
! @item -EL
! @opindex EL
! Generate little-endian code. This is the default for @samp{mips*el-*-*}
! configurations.
! @item -march=@var{arch}
! @opindex march
! Generate code that will run on @var{arch}, which can be the name of a
! generic MIPS ISA, or the name of a particular processor.
! The ISA names are:
! @samp{mips1}, @samp{mips2}, @samp{mips3}, @samp{mips4},
! @samp{mips32}, @samp{mips32r2}, and @samp{mips64}.
! The processor names are:
! @samp{4kc}, @samp{4kp}, @samp{5kc}, @samp{20kc},
! @samp{m4k},
! @samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400},
! @samp{r4600}, @samp{r4650}, @samp{r6000}, @samp{r8000}, @samp{rm7000},
! @samp{rm9000},
! @samp{orion},
! @samp{sb1},
! @samp{vr4100}, @samp{vr4111}, @samp{vr4120}, @samp{vr4130}, @samp{vr4300},
! @samp{vr5000}, @samp{vr5400} and @samp{vr5500}.
! The special value @samp{from-abi} selects the
! most compatible architecture for the selected ABI (that is,
! @samp{mips1} for 32-bit ABIs and @samp{mips3} for 64-bit ABIs)@.
! In processor names, a final @samp{000} can be abbreviated as @samp{k}
! (for example, @samp{-march=r2k}). Prefixes are optional, and
! @samp{vr} may be written @samp{r}.
! GCC defines two macros based on the value of this option. The first
! is @samp{_MIPS_ARCH}, which gives the name of target architecture, as
! a string. The second has the form @samp{_MIPS_ARCH_@var{foo}},
! where @var{foo} is the capitalized value of @samp{_MIPS_ARCH}@.
! For example, @samp{-march=r2000} will set @samp{_MIPS_ARCH}
! to @samp{"r2000"} and define the macro @samp{_MIPS_ARCH_R2000}.
! Note that the @samp{_MIPS_ARCH} macro uses the processor names given
! above. In other words, it will have the full prefix and will not
! abbreviate @samp{000} as @samp{k}. In the case of @samp{from-abi},
! the macro names the resolved architecture (either @samp{"mips1"} or
! @samp{"mips3"}). It names the default architecture when no
! @option{-march} option is given.
! @item -mtune=@var{arch}
! @opindex mtune
! Optimize for @var{arch}. Among other things, this option controls
! the way instructions are scheduled, and the perceived cost of arithmetic
! operations. The list of @var{arch} values is the same as for
! @option{-march}.
! When this option is not used, GCC will optimize for the processor
! specified by @option{-march}. By using @option{-march} and
! @option{-mtune} together, it is possible to generate code that will
! run on a family of processors, but optimize the code for one
! particular member of that family.
! @samp{-mtune} defines the macros @samp{_MIPS_TUNE} and
! @samp{_MIPS_TUNE_@var{foo}}, which work in the same way as the
! @samp{-march} ones described above.
! @item -mips1
! @opindex mips1
! Equivalent to @samp{-march=mips1}.
! @item -mips2
! @opindex mips2
! Equivalent to @samp{-march=mips2}.
! @item -mips3
! @opindex mips3
! Equivalent to @samp{-march=mips3}.
! @item -mips4
! @opindex mips4
! Equivalent to @samp{-march=mips4}.
! @item -mips32
! @opindex mips32
! Equivalent to @samp{-march=mips32}.
! @item -mips32r2
! @opindex mips32r2
! Equivalent to @samp{-march=mips32r2}.
! @item -mips64
! @opindex mips64
! Equivalent to @samp{-march=mips64}.
! @item -mips16
! @itemx -mno-mips16
! @opindex mips16
! @opindex mno-mips16
! Use (do not use) the MIPS16 ISA.
! @item -mabi=32
! @itemx -mabi=o64
! @itemx -mabi=n32
! @itemx -mabi=64
! @itemx -mabi=eabi
! @opindex mabi=32
! @opindex mabi=o64
! @opindex mabi=n32
! @opindex mabi=64
! @opindex mabi=eabi
! Generate code for the given ABI@.
! Note that the EABI has a 32-bit and a 64-bit variant. GCC normally
! generates 64-bit code when you select a 64-bit architecture, but you
! can use @option{-mgp32} to get 32-bit code instead.
! For information about the O64 ABI, see
! @w{@uref{http://gcc.gnu.org/projects/mipso64-abi.html}}.
! @item -mabicalls
! @itemx -mno-abicalls
! @opindex mabicalls
! @opindex mno-abicalls
! Generate (do not generate) SVR4-style position-independent code.
! @option{-mabicalls} is the default for SVR4-based systems.
! @item -mxgot
! @itemx -mno-xgot
! @opindex mxgot
! @opindex mno-xgot
! Lift (do not lift) the usual restrictions on the size of the global
! offset table.
! GCC normally uses a single instruction to load values from the GOT.
! While this is relatively efficient, it will only work if the GOT
! is smaller than about 64k. Anything larger will cause the linker
! to report an error such as:
! @cindex relocation truncated to fit (MIPS)
! @smallexample
! relocation truncated to fit: R_MIPS_GOT16 foobar
! @end smallexample
! If this happens, you should recompile your code with @option{-mxgot}.
! It should then work with very large GOTs, although it will also be
! less efficient, since it will take three instructions to fetch the
! value of a global symbol.
! Note that some linkers can create multiple GOTs. If you have such a
! linker, you should only need to use @option{-mxgot} when a single object
! file accesses more than 64k's worth of GOT entries. Very few do.
! These options have no effect unless GCC is generating position
! independent code.
! @item -mgp32
! @opindex mgp32
! Assume that general-purpose registers are 32 bits wide.
! @item -mgp64
! @opindex mgp64
! Assume that general-purpose registers are 64 bits wide.
! @item -mfp32
! @opindex mfp32
! Assume that floating-point registers are 32 bits wide.
! @item -mfp64
! @opindex mfp64
! Assume that floating-point registers are 64 bits wide.
! @item -mhard-float
! @opindex mhard-float
! Use floating-point coprocessor instructions.
! @item -msoft-float
! @opindex msoft-float
! Do not use floating-point coprocessor instructions. Implement
! floating-point calculations using library calls instead.
! @item -msingle-float
! @opindex msingle-float
! Assume that the floating-point coprocessor only supports single-precision
! operations.
! @itemx -mdouble-float
! @opindex mdouble-float
! Assume that the floating-point coprocessor supports double-precision
! operations. This is the default.
! @item -mint64
! @opindex mint64
! Force @code{int} and @code{long} types to be 64 bits wide. See
! @option{-mlong32} for an explanation of the default and the way
! that the pointer size is determined.
! @item -mlong64
! @opindex mlong64
! Force @code{long} types to be 64 bits wide. See @option{-mlong32} for
! an explanation of the default and the way that the pointer size is
! determined.
- @item -mlong32
- @opindex mlong32
- Force @code{long}, @code{int}, and pointer types to be 32 bits wide.
! The default size of @code{int}s, @code{long}s and pointers depends on
! the ABI@. All the supported ABIs use 32-bit @code{int}s. The n64 ABI
! uses 64-bit @code{long}s, as does the 64-bit EABI; the others use
! 32-bit @code{long}s. Pointers are the same size as @code{long}s,
! or the same size as integer registers, whichever is smaller.
! @item -G @var{num}
! @opindex G
! @cindex smaller data references (MIPS)
! @cindex gp-relative references (MIPS)
! Put global and static items less than or equal to @var{num} bytes into
! the small data or bss section instead of the normal data or bss section.
! This allows the data to be accessed using a single instruction.
! All modules should be compiled with the same @option{-G @var{num}}
! value.
! @item -membedded-data
! @itemx -mno-embedded-data
! @opindex membedded-data
! @opindex mno-embedded-data
! Allocate variables to the read-only data section first if possible, then
! next in the small data section if possible, otherwise in data. This gives
! slightly slower code than the default, but reduces the amount of RAM required
! when executing, and thus may be preferred for some embedded systems.
! @item -muninit-const-in-rodata
! @itemx -mno-uninit-const-in-rodata
! @opindex muninit-const-in-rodata
! @opindex mno-uninit-const-in-rodata
! Put uninitialized @code{const} variables in the read-only data section.
! This option is only meaningful in conjunction with @option{-membedded-data}.
! @item -msplit-addresses
! @itemx -mno-split-addresses
! @opindex msplit-addresses
! @opindex mno-split-addresses
! Enable (disable) use of the @code{%hi()} and @code{%lo()} assembler
! relocation operators. This option has been superceded by
! @option{-mexplicit-relocs} but is retained for backwards compatibility.
! @item -mexplicit-relocs
! @itemx -mno-explicit-relocs
! @opindex mexplicit-relocs
! @opindex mno-explicit-relocs
! Use (do not use) assembler relocation operators when dealing with symbolic
! addresses. The alternative, selected by @option{-mno-explicit-relocs},
! is to use assembler macros instead.
! @option{-mexplicit-relocs} is usually the default if GCC was configured
! to use an assembler that supports relocation operators. However, the
! combination of @option{-mabicalls} and @option{-fno-unit-at-a-time}
! implies @option{-mno-explicit-relocs} unless explicitly overridden.
! This is because, when generating abicalls, the choice of relocation
! depends on whether a symbol is local or global. In some rare cases,
! GCC will not be able to decide this until the whole compilation unit
! has been read.
! @item -mrnames
! @itemx -mno-rnames
! @opindex mrnames
! @opindex mno-rnames
! Generate (do not generate) code that refers to registers using their
! software names. The default is @option{-mno-rnames}, which tells GCC
! to use hardware names like @samp{$4} instead of software names like
! @samp{a0}. The only assembler known to support @option{-rnames} is
! the Algorithmics assembler.
! @item -mcheck-zero-division
! @itemx -mno-check-zero-division
! @opindex mcheck-zero-division
! @opindex mno-check-zero-division
! Trap (do not trap) on integer division by zero. The default is
! @option{-mcheck-zero-division}.
! @item -mmemcpy
! @itemx -mno-memcpy
! @opindex mmemcpy
! @opindex mno-memcpy
! Force (do not force) the use of @code{memcpy()} for non-trivial block
! moves. The default is @option{-mno-memcpy}, which allows GCC to inline
! most constant-sized copies.
! @item -mlong-calls
! @itemx -mno-long-calls
! @opindex mlong-calls
! @opindex mno-long-calls
! Disable (do not disable) use of the @code{jal} instruction. Calling
! functions using @code{jal} is more efficient but requires the caller
! and callee to be in the same 256 megabyte segment.
! This option has no effect on abicalls code. The default is
! @option{-mno-long-calls}.
! @item -mmad
! @itemx -mno-mad
! @opindex mmad
! @opindex mno-mad
! Enable (disable) use of the @code{mad}, @code{madu} and @code{mul}
! instructions, as provided by the R4650 ISA.
! @item -mfused-madd
! @itemx -mno-fused-madd
! @opindex mfused-madd
! @opindex mno-fused-madd
! Enable (disable) use of the floating point multiply-accumulate
! instructions, when they are available. The default is
! @option{-mfused-madd}.
! When multiply-accumulate instructions are used, the intermediate
! product is calculated to infinite precision and is not subject to
! the FCSR Flush to Zero bit. This may be undesirable in some
! circumstances.
! @item -nocpp
! @opindex nocpp
! Tell the MIPS assembler to not run its preprocessor over user
! assembler files (with a @samp{.s} suffix) when assembling them.
! @item -mfix-r4000
! @itemx -mno-fix-r4000
! @opindex mfix-r4000
! @opindex mno-fix-r4000
! Work around certain R4000 CPU errata:
! @itemize @minus
! @item
! A double-word or a variable shift may give an incorrect result if executed
! immediately after starting an integer division.
! @item
! A double-word or a variable shift may give an incorrect result if executed
! while an integer multiplication is in progress.
! @item
! An integer division may give an incorrect result if started in a delay slot
! of a taken branch or a jump.
! @end itemize
! @item -mfix-r4400
! @itemx -mno-fix-r4400
! @opindex mfix-r4400
! @opindex mno-fix-r4400
! Work around certain R4400 CPU errata:
! @itemize @minus
! @item
! A double-word or a variable shift may give an incorrect result if executed
! immediately after starting an integer division.
! @end itemize
! @item -mfix-vr4120
! @itemx -mno-fix-vr4120
! @opindex mfix-vr4120
! Work around certain VR4120 errata:
! @itemize @minus
! @item
! @code{dmultu} does not always produce the correct result.
! @item
! @code{div} and @code{ddiv} do not always produce the correct result if one
! of the operands is negative.
! @end itemize
! The workarounds for the division errata rely on special functions in
! @file{libgcc.a}. At present, these functions are only provided by
! the @code{mips64vr*-elf} configurations.
! Other VR4120 errata require a nop to be inserted between certain pairs of
! instructions. These errata are handled by the assembler, not by GCC itself.
! @item -mfix-sb1
! @itemx -mno-fix-sb1
! @opindex mfix-sb1
! Work around certain SB-1 CPU core errata.
! (This flag currently works around the SB-1 revision 2
! ``F1'' and ``F2'' floating point errata.)
! @item -mflush-func=@var{func}
! @itemx -mno-flush-func
! @opindex mflush-func
! Specifies the function to call to flush the I and D caches, or to not
! call any such function. If called, the function must take the same
! arguments as the common @code{_flush_func()}, that is, the address of the
! memory range for which the cache is being flushed, the size of the
! memory range, and the number 3 (to flush both caches). The default
! depends on the target GCC was configured for, but commonly is either
! @samp{_flush_func} or @samp{__cpu_flush}.
! @item -mbranch-likely
! @itemx -mno-branch-likely
! @opindex mbranch-likely
! @opindex mno-branch-likely
! Enable or disable use of Branch Likely instructions, regardless of the
! default for the selected architecture. By default, Branch Likely
! instructions may be generated if they are supported by the selected
! architecture. An exception is for the MIPS32 and MIPS64 architectures
! and processors which implement those architectures; for those, Branch
! Likely instructions will not be generated by default because the MIPS32
! and MIPS64 architectures specifically deprecate their use.
! @item -mfp-exceptions
! @itemx -mno-fp-exceptions
! @opindex mfp-exceptions
! Specifies whether FP exceptions are enabled. This affects how we schedule
! FP instructions for some processors. The default is that FP exceptions are
! enabled.
! For instance, on the SB-1, if FP exceptions are disabled, and we are emitting
! 64-bit code, then we can use both FP pipes. Otherwise, we can only use one
! FP pipe.
! @item -mvr4130-align
! @itemx -mno-vr4130-align
! @opindex mvr4130-align
! The VR4130 pipeline is two-way superscalar, but can only issue two
! instructions together if the first one is 8-byte aligned. When this
! option is enabled, GCC will align pairs of instructions that it
! thinks should execute in parallel.
! This option only has an effect when optimizing for the VR4130.
! It normally makes code faster, but at the expense of making it bigger.
! It is enabled by default at optimization level @option{-O3}.
@end table
! @node i386 and x86-64 Options
! @subsection Intel 386 and AMD x86-64 Options
! @cindex i386 Options
! @cindex x86-64 Options
! @cindex Intel 386 Options
! @cindex AMD x86-64 Options
! These @samp{-m} options are defined for the i386 and x86-64 family of
! computers:
@table @gcctabopt
! @item -mtune=@var{cpu-type}
! @opindex mtune
! Tune to @var{cpu-type} everything applicable about the generated code, except
! for the ABI and the set of available instructions. The choices for
! @var{cpu-type} are:
! @table @emph
! @item i386
! Original Intel's i386 CPU.
! @item i486
! Intel's i486 CPU. (No scheduling is implemented for this chip.)
! @item i586, pentium
! Intel Pentium CPU with no MMX support.
! @item pentium-mmx
! Intel PentiumMMX CPU based on Pentium core with MMX instruction set support.
! @item i686, pentiumpro
! Intel PentiumPro CPU.
! @item pentium2
! Intel Pentium2 CPU based on PentiumPro core with MMX instruction set support.
! @item pentium3, pentium3m
! Intel Pentium3 CPU based on PentiumPro core with MMX and SSE instruction set
! support.
! @item pentium-m
! Low power version of Intel Pentium3 CPU with MMX, SSE and SSE2 instruction set
! support. Used by Centrino notebooks.
! @item pentium4, pentium4m
! Intel Pentium4 CPU with MMX, SSE and SSE2 instruction set support.
! @item prescott
! Improved version of Intel Pentium4 CPU with MMX, SSE, SSE2 and SSE3 instruction
! set support.
! @item nocona
! Improved version of Intel Pentium4 CPU with 64-bit extensions, MMX, SSE,
! SSE2 and SSE3 instruction set support.
! @item k6
! AMD K6 CPU with MMX instruction set support.
! @item k6-2, k6-3
! Improved versions of AMD K6 CPU with MMX and 3dNOW! instruction set support.
! @item athlon, athlon-tbird
! AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW! and SSE prefetch instructions
! support.
! @item athlon-4, athlon-xp, athlon-mp
! Improved AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW! and full SSE
! instruction set support.
! @item k8, opteron, athlon64, athlon-fx
! AMD K8 core based CPUs with x86-64 instruction set support. (This supersets
! MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW! and 64-bit instruction set extensions.)
! @item winchip-c6
! IDT Winchip C6 CPU, dealt in same way as i486 with additional MMX instruction
! set support.
! @item winchip2
! IDT Winchip2 CPU, dealt in same way as i486 with additional MMX and 3dNOW!
! instruction set support.
! @item c3
! Via C3 CPU with MMX and 3dNOW! instruction set support. (No scheduling is
! implemented for this chip.)
! @item c3-2
! Via C3-2 CPU with MMX and SSE instruction set support. (No scheduling is
! implemented for this chip.)
! @end table
! While picking a specific @var{cpu-type} will schedule things appropriately
! for that particular chip, the compiler will not generate any code that
! does not run on the i386 without the @option{-march=@var{cpu-type}} option
! being used.
! @item -march=@var{cpu-type}
! @opindex march
! Generate instructions for the machine type @var{cpu-type}. The choices
! for @var{cpu-type} are the same as for @option{-mtune}. Moreover,
! specifying @option{-march=@var{cpu-type}} implies @option{-mtune=@var{cpu-type}}.
! @item -mcpu=@var{cpu-type}
! @opindex mcpu
! A deprecated synonym for @option{-mtune}.
! @item -m386
! @itemx -m486
! @itemx -mpentium
! @itemx -mpentiumpro
! @opindex m386
! @opindex m486
! @opindex mpentium
! @opindex mpentiumpro
! These options are synonyms for @option{-mtune=i386}, @option{-mtune=i486},
! @option{-mtune=pentium}, and @option{-mtune=pentiumpro} respectively.
! These synonyms are deprecated.
! @item -mfpmath=@var{unit}
! @opindex march
! Generate floating point arithmetics for selected unit @var{unit}. The choices
! for @var{unit} are:
! @table @samp
! @item 387
! Use the standard 387 floating point coprocessor present majority of chips and
! emulated otherwise. Code compiled with this option will run almost everywhere.
! The temporary results are computed in 80bit precision instead of precision
! specified by the type resulting in slightly different results compared to most
! of other chips. See @option{-ffloat-store} for more detailed description.
! This is the default choice for i386 compiler.
! @item sse
! Use scalar floating point instructions present in the SSE instruction set.
! This instruction set is supported by Pentium3 and newer chips, in the AMD line
! by Athlon-4, Athlon-xp and Athlon-mp chips. The earlier version of SSE
! instruction set supports only single precision arithmetics, thus the double and
! extended precision arithmetics is still done using 387. Later version, present
! only in Pentium4 and the future AMD x86-64 chips supports double precision
! arithmetics too.
! For i387 you need to use @option{-march=@var{cpu-type}}, @option{-msse} or
! @option{-msse2} switches to enable SSE extensions and make this option
! effective. For x86-64 compiler, these extensions are enabled by default.
! The resulting code should be considerably faster in the majority of cases and avoid
! the numerical instability problems of 387 code, but may break some existing
! code that expects temporaries to be 80bit.
! This is the default choice for the x86-64 compiler.
! @item sse,387
! Attempt to utilize both instruction sets at once. This effectively double the
! amount of available registers and on chips with separate execution units for
! 387 and SSE the execution resources too. Use this option with care, as it is
! still experimental, because the GCC register allocator does not model separate
! functional units well resulting in instable performance.
! @end table
! @item -masm=@var{dialect}
! @opindex masm=@var{dialect}
! Output asm instructions using selected @var{dialect}. Supported choices are
! @samp{intel} or @samp{att} (the default one).
! @item -mieee-fp
! @itemx -mno-ieee-fp
! @opindex mieee-fp
! @opindex mno-ieee-fp
! Control whether or not the compiler uses IEEE floating point
! comparisons. These handle correctly the case where the result of a
! comparison is unordered.
! @item -msoft-float
! @opindex msoft-float
! Generate output containing library calls for floating point.
! @strong{Warning:} the requisite libraries are not part of GCC@.
! Normally the facilities of the machine's usual C compiler are used, but
! this can't be done directly in cross-compilation. You must make your
! own arrangements to provide suitable library functions for
! cross-compilation.
! On machines where a function returns floating point results in the 80387
! register stack, some floating point opcodes may be emitted even if
! @option{-msoft-float} is used.
! @item -mno-fp-ret-in-387
! @opindex mno-fp-ret-in-387
! Do not use the FPU registers for return values of functions.
! The usual calling convention has functions return values of types
! @code{float} and @code{double} in an FPU register, even if there
! is no FPU@. The idea is that the operating system should emulate
! an FPU@.
! The option @option{-mno-fp-ret-in-387} causes such values to be returned
! in ordinary CPU registers instead.
! @item -mno-fancy-math-387
! @opindex mno-fancy-math-387
! Some 387 emulators do not support the @code{sin}, @code{cos} and
! @code{sqrt} instructions for the 387. Specify this option to avoid
! generating those instructions. This option is the default on FreeBSD,
! OpenBSD and NetBSD@. This option is overridden when @option{-march}
! indicates that the target cpu will always have an FPU and so the
! instruction will not need emulation. As of revision 2.6.1, these
! instructions are not generated unless you also use the
! @option{-funsafe-math-optimizations} switch.
! @item -malign-double
! @itemx -mno-align-double
! @opindex malign-double
! @opindex mno-align-double
! Control whether GCC aligns @code{double}, @code{long double}, and
! @code{long long} variables on a two word boundary or a one word
! boundary. Aligning @code{double} variables on a two word boundary will
! produce code that runs somewhat faster on a @samp{Pentium} at the
! expense of more memory.
! @strong{Warning:} if you use the @option{-malign-double} switch,
! structures containing the above types will be aligned differently than
! the published application binary interface specifications for the 386
! and will not be binary compatible with structures in code compiled
! without that switch.
! @item -m96bit-long-double
! @itemx -m128bit-long-double
! @opindex m96bit-long-double
! @opindex m128bit-long-double
! These switches control the size of @code{long double} type. The i386
! application binary interface specifies the size to be 96 bits,
! so @option{-m96bit-long-double} is the default in 32 bit mode.
! Modern architectures (Pentium and newer) would prefer @code{long double}
! to be aligned to an 8 or 16 byte boundary. In arrays or structures
! conforming to the ABI, this would not be possible. So specifying a
! @option{-m128bit-long-double} will align @code{long double}
! to a 16 byte boundary by padding the @code{long double} with an additional
! 32 bit zero.
! In the x86-64 compiler, @option{-m128bit-long-double} is the default choice as
! its ABI specifies that @code{long double} is to be aligned on 16 byte boundary.
! Notice that neither of these options enable any extra precision over the x87
! standard of 80 bits for a @code{long double}.
! @strong{Warning:} if you override the default value for your target ABI, the
! structures and arrays containing @code{long double} variables will change
! their size as well as function calling convention for function taking
! @code{long double} will be modified. Hence they will not be binary
! compatible with arrays or structures in code compiled without that switch.
! @item -msvr3-shlib
! @itemx -mno-svr3-shlib
! @opindex msvr3-shlib
! @opindex mno-svr3-shlib
! Control whether GCC places uninitialized local variables into the
! @code{bss} or @code{data} segments. @option{-msvr3-shlib} places them
! into @code{bss}. These options are meaningful only on System V Release 3.
! @item -mrtd
! @opindex mrtd
! Use a different function-calling convention, in which functions that
! take a fixed number of arguments return with the @code{ret} @var{num}
! instruction, which pops their arguments while returning. This saves one
! instruction in the caller since there is no need to pop the arguments
! there.
! You can specify that an individual function is called with this calling
! sequence with the function attribute @samp{stdcall}. You can also
! override the @option{-mrtd} option by using the function attribute
! @samp{cdecl}. @xref{Function Attributes}.
! @strong{Warning:} this calling convention is incompatible with the one
! normally used on Unix, so you cannot use it if you need to call
! libraries compiled with the Unix compiler.
! Also, you must provide function prototypes for all functions that
! take variable numbers of arguments (including @code{printf});
! otherwise incorrect code will be generated for calls to those
! functions.
! In addition, seriously incorrect code will result if you call a
! function with too many arguments. (Normally, extra arguments are
! harmlessly ignored.)
! @item -mregparm=@var{num}
! @opindex mregparm
! Control how many registers are used to pass integer arguments. By
! default, no registers are used to pass arguments, and at most 3
! registers can be used. You can control this behavior for a specific
! function by using the function attribute @samp{regparm}.
! @xref{Function Attributes}.
! @strong{Warning:} if you use this switch, and
! @var{num} is nonzero, then you must build all modules with the same
! value, including any libraries. This includes the system libraries and
! startup modules.
! @item -mpreferred-stack-boundary=@var{num}
! @opindex mpreferred-stack-boundary
! Attempt to keep the stack boundary aligned to a 2 raised to @var{num}
! byte boundary. If @option{-mpreferred-stack-boundary} is not specified,
! the default is 4 (16 bytes or 128 bits), except when optimizing for code
! size (@option{-Os}), in which case the default is the minimum correct
! alignment (4 bytes for x86, and 8 bytes for x86-64).
! On Pentium and PentiumPro, @code{double} and @code{long double} values
! should be aligned to an 8 byte boundary (see @option{-malign-double}) or
! suffer significant run time performance penalties. On Pentium III, the
! Streaming SIMD Extension (SSE) data type @code{__m128} suffers similar
! penalties if it is not 16 byte aligned.
! To ensure proper alignment of this values on the stack, the stack boundary
! must be as aligned as that required by any value stored on the stack.
! Further, every function must be generated such that it keeps the stack
! aligned. Thus calling a function compiled with a higher preferred
! stack boundary from a function compiled with a lower preferred stack
! boundary will most likely misalign the stack. It is recommended that
! libraries that use callbacks always use the default setting.
! This extra alignment does consume extra stack space, and generally
! increases code size. Code that is sensitive to stack space usage, such
! as embedded systems and operating system kernels, may want to reduce the
! preferred alignment to @option{-mpreferred-stack-boundary=2}.
! @item -mmmx
! @itemx -mno-mmx
! @item -msse
! @itemx -mno-sse
! @item -msse2
! @itemx -mno-sse2
! @item -msse3
! @itemx -mno-sse3
! @item -m3dnow
! @itemx -mno-3dnow
! @opindex mmmx
! @opindex mno-mmx
! @opindex msse
! @opindex mno-sse
! @opindex m3dnow
! @opindex mno-3dnow
! These switches enable or disable the use of built-in functions that allow
! direct access to the MMX, SSE, SSE2, SSE3 and 3Dnow extensions of the
! instruction set.
! @xref{X86 Built-in Functions}, for details of the functions enabled
! and disabled by these switches.
! To have SSE/SSE2 instructions generated automatically from floating-point
! code, see @option{-mfpmath=sse}.
! @item -mpush-args
! @itemx -mno-push-args
! @opindex mpush-args
! @opindex mno-push-args
! Use PUSH operations to store outgoing parameters. This method is shorter
! and usually equally fast as method using SUB/MOV operations and is enabled
! by default. In some cases disabling it may improve performance because of
! improved scheduling and reduced dependencies.
! @item -maccumulate-outgoing-args
! @opindex maccumulate-outgoing-args
! If enabled, the maximum amount of space required for outgoing arguments will be
! computed in the function prologue. This is faster on most modern CPUs
! because of reduced dependencies, improved scheduling and reduced stack usage
! when preferred stack boundary is not equal to 2. The drawback is a notable
! increase in code size. This switch implies @option{-mno-push-args}.
! @item -mthreads
! @opindex mthreads
! Support thread-safe exception handling on @samp{Mingw32}. Code that relies
! on thread-safe exception handling must compile and link all code with the
! @option{-mthreads} option. When compiling, @option{-mthreads} defines
! @option{-D_MT}; when linking, it links in a special thread helper library
! @option{-lmingwthrd} which cleans up per thread exception handling data.
! @item -mno-align-stringops
! @opindex mno-align-stringops
! Do not align destination of inlined string operations. This switch reduces
! code size and improves performance in case the destination is already aligned,
! but GCC doesn't know about it.
! @item -minline-all-stringops
! @opindex minline-all-stringops
! By default GCC inlines string operations only when destination is known to be
! aligned at least to 4 byte boundary. This enables more inlining, increase code
! size, but may improve performance of code that depends on fast memcpy, strlen
! and memset for short lengths.
! @item -momit-leaf-frame-pointer
! @opindex momit-leaf-frame-pointer
! Don't keep the frame pointer in a register for leaf functions. This
! avoids the instructions to save, set up and restore frame pointers and
! makes an extra register available in leaf functions. The option
! @option{-fomit-frame-pointer} removes the frame pointer for all functions
! which might make debugging harder.
! @item -mtls-direct-seg-refs
! @itemx -mno-tls-direct-seg-refs
! @opindex mtls-direct-seg-refs
! Controls whether TLS variables may be accessed with offsets from the
! TLS segment register (@code{%gs} for 32-bit, @code{%fs} for 64-bit),
! or whether the thread base pointer must be added. Whether or not this
! is legal depends on the operating system, and whether it maps the
! segment to cover the entire TLS area.
! For systems that use GNU libc, the default is on.
! @end table
! These @samp{-m} switches are supported in addition to the above
! on AMD x86-64 processors in 64-bit environments.
! @table @gcctabopt
! @item -m32
! @itemx -m64
! @opindex m32
! @opindex m64
! Generate code for a 32-bit or 64-bit environment.
! The 32-bit environment sets int, long and pointer to 32 bits and
! generates code that runs on any i386 system.
! The 64-bit environment sets int to 32 bits and long and pointer
! to 64 bits and generates code for AMD's x86-64 architecture.
! @item -mno-red-zone
! @opindex no-red-zone
! Do not use a so called red zone for x86-64 code. The red zone is mandated
! by the x86-64 ABI, it is a 128-byte area beyond the location of the
! stack pointer that will not be modified by signal or interrupt handlers
! and therefore can be used for temporary data without adjusting the stack
! pointer. The flag @option{-mno-red-zone} disables this red zone.
! @item -mcmodel=small
! @opindex mcmodel=small
! Generate code for the small code model: the program and its symbols must
! be linked in the lower 2 GB of the address space. Pointers are 64 bits.
! Programs can be statically or dynamically linked. This is the default
! code model.
! @item -mcmodel=kernel
! @opindex mcmodel=kernel
! Generate code for the kernel code model. The kernel runs in the
! negative 2 GB of the address space.
! This model has to be used for Linux kernel code.
- @item -mcmodel=medium
- @opindex mcmodel=medium
- Generate code for the medium model: The program is linked in the lower 2
- GB of the address space but symbols can be located anywhere in the
- address space. Programs can be statically or dynamically linked, but
- building of shared libraries are not supported with the medium model.
! @item -mcmodel=large
! @opindex mcmodel=large
! Generate code for the large model: This model makes no assumptions
! about addresses and sizes of sections. Currently GCC does not implement
! this model.
! @end table
! @node HPPA Options
! @subsection HPPA Options
! @cindex HPPA Options
! These @samp{-m} options are defined for the HPPA family of computers:
! @table @gcctabopt
! @item -march=@var{architecture-type}
! @opindex march
! Generate code for the specified architecture. The choices for
! @var{architecture-type} are @samp{1.0} for PA 1.0, @samp{1.1} for PA
! 1.1, and @samp{2.0} for PA 2.0 processors. Refer to
! @file{/usr/lib/sched.models} on an HP-UX system to determine the proper
! architecture option for your machine. Code compiled for lower numbered
! architectures will run on higher numbered architectures, but not the
! other way around.
! PA 2.0 support currently requires gas snapshot 19990413 or later. The
! next release of binutils (current is 2.9.1) will probably contain PA 2.0
! support.
! @item -mpa-risc-1-0
! @itemx -mpa-risc-1-1
! @itemx -mpa-risc-2-0
! @opindex mpa-risc-1-0
! @opindex mpa-risc-1-1
! @opindex mpa-risc-2-0
! Synonyms for @option{-march=1.0}, @option{-march=1.1}, and @option{-march=2.0} respectively.
! @item -mbig-switch
! @opindex mbig-switch
! Generate code suitable for big switch tables. Use this option only if
! the assembler/linker complain about out of range branches within a switch
! table.
! @item -mjump-in-delay
! @opindex mjump-in-delay
! Fill delay slots of function calls with unconditional jump instructions
! by modifying the return pointer for the function call to be the target
! of the conditional jump.
! @item -mdisable-fpregs
! @opindex mdisable-fpregs
! Prevent floating point registers from being used in any manner. This is
! necessary for compiling kernels which perform lazy context switching of
! floating point registers. If you use this option and attempt to perform
! floating point operations, the compiler will abort.
! @item -mdisable-indexing
! @opindex mdisable-indexing
! Prevent the compiler from using indexing address modes. This avoids some
! rather obscure problems when compiling MIG generated code under MACH@.
! @item -mno-space-regs
! @opindex mno-space-regs
! Generate code that assumes the target has no space registers. This allows
! GCC to generate faster indirect calls and use unscaled index address modes.
! Such code is suitable for level 0 PA systems and kernels.
! @item -mfast-indirect-calls
! @opindex mfast-indirect-calls
! Generate code that assumes calls never cross space boundaries. This
! allows GCC to emit code which performs faster indirect calls.
! This option will not work in the presence of shared libraries or nested
! functions.
! @item -mlong-load-store
! @opindex mlong-load-store
! Generate 3-instruction load and store sequences as sometimes required by
! the HP-UX 10 linker. This is equivalent to the @samp{+k} option to
! the HP compilers.
! @item -mportable-runtime
! @opindex mportable-runtime
! Use the portable calling conventions proposed by HP for ELF systems.
! @item -mgas
! @opindex mgas
! Enable the use of assembler directives only GAS understands.
! @item -mschedule=@var{cpu-type}
! @opindex mschedule
! Schedule code according to the constraints for the machine type
! @var{cpu-type}. The choices for @var{cpu-type} are @samp{700}
! @samp{7100}, @samp{7100LC}, @samp{7200}, @samp{7300} and @samp{8000}. Refer
! to @file{/usr/lib/sched.models} on an HP-UX system to determine the
! proper scheduling option for your machine. The default scheduling is
! @samp{8000}.
! @item -mlinker-opt
! @opindex mlinker-opt
! Enable the optimization pass in the HP-UX linker. Note this makes symbolic
! debugging impossible. It also triggers a bug in the HP-UX 8 and HP-UX 9
! linkers in which they give bogus error messages when linking some programs.
! @item -msoft-float
! @opindex msoft-float
! Generate output containing library calls for floating point.
! @strong{Warning:} the requisite libraries are not available for all HPPA
! targets. Normally the facilities of the machine's usual C compiler are
! used, but this cannot be done directly in cross-compilation. You must make
! your own arrangements to provide suitable library functions for
! cross-compilation. The embedded target @samp{hppa1.1-*-pro}
! does provide software floating point support.
! @option{-msoft-float} changes the calling convention in the output file;
! therefore, it is only useful if you compile @emph{all} of a program with
! this option. In particular, you need to compile @file{libgcc.a}, the
! library that comes with GCC, with @option{-msoft-float} in order for
! this to work.
! @item -msio
! @opindex msio
! Generate the predefine, @code{_SIO}, for server IO. The default is
! @option{-mwsio}. This generates the predefines, @code{__hp9000s700},
! @code{__hp9000s700__} and @code{_WSIO}, for workstation IO. These
! options are available under HP-UX and HI-UX.
! @item -mgnu-ld
! @opindex gnu-ld
! Use GNU ld specific options. This passes @option{-shared} to ld when
! building a shared library. It is the default when GCC is configured,
! explicitly or implicitly, with the GNU linker. This option does not
! have any affect on which ld is called, it only changes what parameters
! are passed to that ld. The ld that is called is determined by the
! @option{--with-ld} configure option, GCC's program search path, and
! finally by the user's @env{PATH}. The linker used by GCC can be printed
! using @samp{which `gcc -print-prog-name=ld`}.
! @item -mhp-ld
! @opindex hp-ld
! Use HP ld specific options. This passes @option{-b} to ld when building
! a shared library and passes @option{+Accept TypeMismatch} to ld on all
! links. It is the default when GCC is configured, explicitly or
! implicitly, with the HP linker. This option does not have any affect on
! which ld is called, it only changes what parameters are passed to that
! ld. The ld that is called is determined by the @option{--with-ld}
! configure option, GCC's program search path, and finally by the user's
! @env{PATH}. The linker used by GCC can be printed using @samp{which
! `gcc -print-prog-name=ld`}.
! @item -mfdpic
! @opindex mfdpic
! Select the FDPIC ABI, that uses function descriptors to represent
! pointers to functions. Without any PIC/PIE-related options, it
! implies @option{-fPIE}. With @option{-fpic} or @option{-fpie}, it
! assumes GOT entries and small data are within a 12-bit range from the
! GOT base address; with @option{-fPIC} or @option{-fPIE}, GOT offsets
! are computed with 32 bits.
! @item -minline-plt
! @opindex minline-plt
! Enable inlining of PLT entries in function calls to functions that are
! not known to bind locally. It has no effect without @option{-mfdpic}.
! It's enabled by default if optimizing for speed and compiling for
! shared libraries (i.e., @option{-fPIC} or @option{-fpic}), or when an
! optimization option such as @option{-O3} or above is present in the
! command line.
! @item -mgprel-ro
! @opindex mgprel-ro
! Enable the use of @code{GPREL} relocations in the FDPIC ABI for data
! that is known to be in read-only sections. It's enabled by default,
! except for @option{-fpic} or @option{-fpie}: even though it may help
! make the global offset table smaller, it trades 1 instruction for 4.
! With @option{-fPIC} or @option{-fPIE}, it trades 3 instructions for 4,
! one of which may be shared by multiple symbols, and it avoids the need
! for a GOT entry for the referenced symbol, so it's more likely to be a
! win. If it is not, @option{-mno-gprel-ro} can be used to disable it.
! @item -multilib-library-pic
! @opindex multilib-library-pic
! Link with the (library, not FD) pic libraries. It's implied by
! @option{-mlibrary-pic}, as well as by @option{-fPIC} and
! @option{-fpic} without @option{-mfdpic}. You should never have to use
! it explicitly.
! @item -mlinked-fp
! @opindex mlinked-fp
! Follow the EABI requirement of always creating a frame pointer whenever
! a stack frame is allocated. This option is enabled by default and can
! be disabled with @option{-mno-linked-fp}.
! @item -mlong-calls
! @opindex mno-long-calls
! Generate code that uses long call sequences. This ensures that a call
! is always able to reach linker generated stubs. The default is to generate
! long calls only when the distance from the call site to the beginning
! of the function or translation unit, as the case may be, exceeds a
! predefined limit set by the branch type being used. The limits for
! normal calls are 7,600,000 and 240,000 bytes, respectively for the
! PA 2.0 and PA 1.X architectures. Sibcalls are always limited at
! 240,000 bytes.
! Distances are measured from the beginning of functions when using the
! @option{-ffunction-sections} option, or when using the @option{-mgas}
! and @option{-mno-portable-runtime} options together under HP-UX with
! the SOM linker.
! It is normally not desirable to use this option as it will degrade
! performance. However, it may be useful in large applications,
! particularly when partial linking is used to build the application.
! The types of long calls used depends on the capabilities of the
! assembler and linker, and the type of code being generated. The
! impact on systems that support long absolute calls, and long pic
! symbol-difference or pc-relative calls should be relatively small.
! However, an indirect call is used on 32-bit ELF systems in pic code
! and it is quite long.
! @item -nolibdld
! @opindex nolibdld
! Suppress the generation of link options to search libdld.sl when the
! @option{-static} option is specified on HP-UX 10 and later.
! @item -static
! @opindex static
! The HP-UX implementation of setlocale in libc has a dependency on
! libdld.sl. There isn't an archive version of libdld.sl. Thus,
! when the @option{-static} option is specified, special link options
! are needed to resolve this dependency.
! On HP-UX 10 and later, the GCC driver adds the necessary options to
! link with libdld.sl when the @option{-static} option is specified.
! This causes the resulting binary to be dynamic. On the 64-bit port,
! the linkers generate dynamic binaries by default in any case. The
! @option{-nolibdld} option can be used to prevent the GCC driver from
! adding these link options.
! @item -threads
! @opindex threads
! Add support for multithreading with the @dfn{dce thread} library
! under HP-UX. This option sets flags for both the preprocessor and
! linker.
@end table
! @node DEC Alpha Options
! @subsection DEC Alpha Options
!
! These @samp{-m} options are defined for the DEC Alpha implementations:
@table @gcctabopt
- @item -mno-soft-float
- @itemx -msoft-float
- @opindex mno-soft-float
- @opindex msoft-float
- Use (do not use) the hardware floating-point instructions for
- floating-point operations. When @option{-msoft-float} is specified,
- functions in @file{libgcc.a} will be used to perform floating-point
- operations. Unless they are replaced by routines that emulate the
- floating-point operations, or compiled in such a way as to call such
- emulations routines, these routines will issue floating-point
- operations. If you are compiling for an Alpha without floating-point
- operations, you must ensure that the library is built so as not to call
- them.
! Note that Alpha implementations without floating-point operations are
! required to have floating-point registers.
! @item -mfp-reg
! @itemx -mno-fp-regs
! @opindex mfp-reg
! @opindex mno-fp-regs
! Generate code that uses (does not use) the floating-point register set.
! @option{-mno-fp-regs} implies @option{-msoft-float}. If the floating-point
! register set is not used, floating point operands are passed in integer
! registers as if they were integers and floating-point results are passed
! in @code{$0} instead of @code{$f0}. This is a non-standard calling sequence,
! so any function with a floating-point argument or return value called by code
! compiled with @option{-mno-fp-regs} must also be compiled with that
! option.
! A typical use of this option is building a kernel that does not use,
! and hence need not save and restore, any floating-point registers.
! @item -mieee
! @opindex mieee
! The Alpha architecture implements floating-point hardware optimized for
! maximum performance. It is mostly compliant with the IEEE floating
! point standard. However, for full compliance, software assistance is
! required. This option generates code fully IEEE compliant code
! @emph{except} that the @var{inexact-flag} is not maintained (see below).
! If this option is turned on, the preprocessor macro @code{_IEEE_FP} is
! defined during compilation. The resulting code is less efficient but is
! able to correctly support denormalized numbers and exceptional IEEE
! values such as not-a-number and plus/minus infinity. Other Alpha
! compilers call this option @option{-ieee_with_no_inexact}.
! @item -mieee-with-inexact
! @opindex mieee-with-inexact
! This is like @option{-mieee} except the generated code also maintains
! the IEEE @var{inexact-flag}. Turning on this option causes the
! generated code to implement fully-compliant IEEE math. In addition to
! @code{_IEEE_FP}, @code{_IEEE_FP_EXACT} is defined as a preprocessor
! macro. On some Alpha implementations the resulting code may execute
! significantly slower than the code generated by default. Since there is
! very little code that depends on the @var{inexact-flag}, you should
! normally not specify this option. Other Alpha compilers call this
! option @option{-ieee_with_inexact}.
! @item -mfp-trap-mode=@var{trap-mode}
! @opindex mfp-trap-mode
! This option controls what floating-point related traps are enabled.
! Other Alpha compilers call this option @option{-fptm @var{trap-mode}}.
! The trap mode can be set to one of four values:
! @table @samp
! @item n
! This is the default (normal) setting. The only traps that are enabled
! are the ones that cannot be disabled in software (e.g., division by zero
! trap).
! @item u
! In addition to the traps enabled by @samp{n}, underflow traps are enabled
! as well.
! @item su
! Like @samp{su}, but the instructions are marked to be safe for software
! completion (see Alpha architecture manual for details).
! @item sui
! Like @samp{su}, but inexact traps are enabled as well.
! @end table
! @item -mfp-rounding-mode=@var{rounding-mode}
! @opindex mfp-rounding-mode
! Selects the IEEE rounding mode. Other Alpha compilers call this option
! @option{-fprm @var{rounding-mode}}. The @var{rounding-mode} can be one
! of:
! @table @samp
! @item n
! Normal IEEE rounding mode. Floating point numbers are rounded towards
! the nearest machine number or towards the even machine number in case
! of a tie.
! @item m
! Round towards minus infinity.
! @item c
! Chopped rounding mode. Floating point numbers are rounded towards zero.
! @item d
! Dynamic rounding mode. A field in the floating point control register
! (@var{fpcr}, see Alpha architecture reference manual) controls the
! rounding mode in effect. The C library initializes this register for
! rounding towards plus infinity. Thus, unless your program modifies the
! @var{fpcr}, @samp{d} corresponds to round towards plus infinity.
! @end table
! @item -mtrap-precision=@var{trap-precision}
! @opindex mtrap-precision
! In the Alpha architecture, floating point traps are imprecise. This
! means without software assistance it is impossible to recover from a
! floating trap and program execution normally needs to be terminated.
! GCC can generate code that can assist operating system trap handlers
! in determining the exact location that caused a floating point trap.
! Depending on the requirements of an application, different levels of
! precisions can be selected:
! @table @samp
! @item p
! Program precision. This option is the default and means a trap handler
! can only identify which program caused a floating point exception.
! @item f
! Function precision. The trap handler can determine the function that
! caused a floating point exception.
! @item i
! Instruction precision. The trap handler can determine the exact
! instruction that caused a floating point exception.
! @end table
! Other Alpha compilers provide the equivalent options called
! @option{-scope_safe} and @option{-resumption_safe}.
! @item -mieee-conformant
! @opindex mieee-conformant
! This option marks the generated code as IEEE conformant. You must not
! use this option unless you also specify @option{-mtrap-precision=i} and either
! @option{-mfp-trap-mode=su} or @option{-mfp-trap-mode=sui}. Its only effect
! is to emit the line @samp{.eflag 48} in the function prologue of the
! generated assembly file. Under DEC Unix, this has the effect that
! IEEE-conformant math library routines will be linked in.
! @item -mbuild-constants
! @opindex mbuild-constants
! Normally GCC examines a 32- or 64-bit integer constant to
! see if it can construct it from smaller constants in two or three
! instructions. If it cannot, it will output the constant as a literal and
! generate code to load it from the data segment at runtime.
! Use this option to require GCC to construct @emph{all} integer constants
! using code, even if it takes more instructions (the maximum is six).
! You would typically use this option to build a shared library dynamic
! loader. Itself a shared library, it must relocate itself in memory
! before it can find the variables and constants in its own data segment.
! @item -malpha-as
! @itemx -mgas
! @opindex malpha-as
! @opindex mgas
! Select whether to generate code to be assembled by the vendor-supplied
! assembler (@option{-malpha-as}) or by the GNU assembler @option{-mgas}.
! @item -mbwx
! @itemx -mno-bwx
! @itemx -mcix
! @itemx -mno-cix
! @itemx -mfix
! @itemx -mno-fix
! @itemx -mmax
! @itemx -mno-max
! @opindex mbwx
! @opindex mno-bwx
! @opindex mcix
! @opindex mno-cix
! @opindex mfix
! @opindex mno-fix
! @opindex mmax
! @opindex mno-max
! Indicate whether GCC should generate code to use the optional BWX,
! CIX, FIX and MAX instruction sets. The default is to use the instruction
! sets supported by the CPU type specified via @option{-mcpu=} option or that
! of the CPU on which GCC was built if none was specified.
! @item -mfloat-vax
! @itemx -mfloat-ieee
! @opindex mfloat-vax
! @opindex mfloat-ieee
! Generate code that uses (does not use) VAX F and G floating point
! arithmetic instead of IEEE single and double precision.
! @item -mexplicit-relocs
! @itemx -mno-explicit-relocs
! @opindex mexplicit-relocs
! @opindex mno-explicit-relocs
! Older Alpha assemblers provided no way to generate symbol relocations
! except via assembler macros. Use of these macros does not allow
! optimal instruction scheduling. GNU binutils as of version 2.12
! supports a new syntax that allows the compiler to explicitly mark
! which relocations should apply to which instructions. This option
! is mostly useful for debugging, as GCC detects the capabilities of
! the assembler when it is built and sets the default accordingly.
! @item -msmall-data
! @itemx -mlarge-data
! @opindex msmall-data
! @opindex mlarge-data
! When @option{-mexplicit-relocs} is in effect, static data is
! accessed via @dfn{gp-relative} relocations. When @option{-msmall-data}
! is used, objects 8 bytes long or smaller are placed in a @dfn{small data area}
! (the @code{.sdata} and @code{.sbss} sections) and are accessed via
! 16-bit relocations off of the @code{$gp} register. This limits the
! size of the small data area to 64KB, but allows the variables to be
! directly accessed via a single instruction.
! The default is @option{-mlarge-data}. With this option the data area
! is limited to just below 2GB. Programs that require more than 2GB of
! data must use @code{malloc} or @code{mmap} to allocate the data in the
! heap instead of in the program's data segment.
! When generating code for shared libraries, @option{-fpic} implies
! @option{-msmall-data} and @option{-fPIC} implies @option{-mlarge-data}.
! @item -msmall-text
! @itemx -mlarge-text
! @opindex msmall-text
! @opindex mlarge-text
! When @option{-msmall-text} is used, the compiler assumes that the
! code of the entire program (or shared library) fits in 4MB, and is
! thus reachable with a branch instruction. When @option{-msmall-data}
! is used, the compiler can assume that all local symbols share the
! same @code{$gp} value, and thus reduce the number of instructions
! required for a function call from 4 to 1.
! The default is @option{-mlarge-text}.
! @item -mcpu=@var{cpu_type}
! @opindex mcpu
! Set the instruction set and instruction scheduling parameters for
! machine type @var{cpu_type}. You can specify either the @samp{EV}
! style name or the corresponding chip number. GCC supports scheduling
! parameters for the EV4, EV5 and EV6 family of processors and will
! choose the default values for the instruction set from the processor
! you specify. If you do not specify a processor type, GCC will default
! to the processor on which the compiler was built.
! Supported values for @var{cpu_type} are
! @table @samp
! @item ev4
! @itemx ev45
! @itemx 21064
! Schedules as an EV4 and has no instruction set extensions.
! @item ev5
! @itemx 21164
! Schedules as an EV5 and has no instruction set extensions.
! @item ev56
! @itemx 21164a
! Schedules as an EV5 and supports the BWX extension.
! @item pca56
! @itemx 21164pc
! @itemx 21164PC
! Schedules as an EV5 and supports the BWX and MAX extensions.
! @item ev6
! @itemx 21264
! Schedules as an EV6 and supports the BWX, FIX, and MAX extensions.
! @item ev67
! @itemx 21264a
! Schedules as an EV6 and supports the BWX, CIX, FIX, and MAX extensions.
! @end table
! @item -mtune=@var{cpu_type}
! @opindex mtune
! Set only the instruction scheduling parameters for machine type
! @var{cpu_type}. The instruction set is not changed.
! @item -mmemory-latency=@var{time}
! @opindex mmemory-latency
! Sets the latency the scheduler should assume for typical memory
! references as seen by the application. This number is highly
! dependent on the memory access patterns used by the application
! and the size of the external cache on the machine.
! Valid options for @var{time} are
! @table @samp
! @item @var{number}
! A decimal number representing clock cycles.
! @item L1
! @itemx L2
! @itemx L3
! @itemx main
! The compiler contains estimates of the number of clock cycles for
! ``typical'' EV4 & EV5 hardware for the Level 1, 2 & 3 caches
! (also called Dcache, Scache, and Bcache), as well as to main memory.
! Note that L3 is only valid for EV5.
! @end table
! @end table
! @node DEC Alpha/VMS Options
! @subsection DEC Alpha/VMS Options
! These @samp{-m} options are defined for the DEC Alpha/VMS implementations:
! @table @gcctabopt
! @item -mvms-return-codes
! @opindex mvms-return-codes
! Return VMS condition codes from main. The default is to return POSIX
! style condition (e.g.@ error) codes.
! @end table
! @node H8/300 Options
! @subsection H8/300 Options
! These @samp{-m} options are defined for the H8/300 implementations:
! @table @gcctabopt
! @item -mrelax
! @opindex mrelax
! Shorten some address references at link time, when possible; uses the
! linker option @option{-relax}. @xref{H8/300,, @code{ld} and the H8/300,
! ld, Using ld}, for a fuller description.
! @item -mh
! @opindex mh
! Generate code for the H8/300H@.
! @item -ms
! @opindex ms
! Generate code for the H8S@.
! @item -mn
! @opindex mn
! Generate code for the H8S and H8/300H in the normal mode. This switch
! must be used either with -mh or -ms.
! @item -ms2600
! @opindex ms2600
! Generate code for the H8S/2600. This switch must be used with @option{-ms}.
! @item -mint32
! @opindex mint32
! Make @code{int} data 32 bits by default.
! @item -malign-300
! @opindex malign-300
! On the H8/300H and H8S, use the same alignment rules as for the H8/300.
! The default for the H8/300H and H8S is to align longs and floats on 4
! byte boundaries.
! @option{-malign-300} causes them to be aligned on 2 byte boundaries.
! This option has no effect on the H8/300.
! @end table
! @node SH Options
! @subsection SH Options
! These @samp{-m} options are defined for the SH implementations:
! @table @gcctabopt
! @item -m1
! @opindex m1
! Generate code for the SH1.
! @item -m2
! @opindex m2
! Generate code for the SH2.
! @item -m2e
! Generate code for the SH2e.
! @item -m3
! @opindex m3
! Generate code for the SH3.
! @item -m3e
! @opindex m3e
! Generate code for the SH3e.
! @item -m4-nofpu
! @opindex m4-nofpu
! Generate code for the SH4 without a floating-point unit.
! @item -m4-single-only
! @opindex m4-single-only
! Generate code for the SH4 with a floating-point unit that only
! supports single-precision arithmetic.
! @item -m4-single
! @opindex m4-single
! Generate code for the SH4 assuming the floating-point unit is in
! single-precision mode by default.
! @item -m4
! @opindex m4
! Generate code for the SH4.
! @item -mb
! @opindex mb
! Compile code for the processor in big endian mode.
! @item -ml
! @opindex ml
! Compile code for the processor in little endian mode.
! @item -mdalign
! @opindex mdalign
! Align doubles at 64-bit boundaries. Note that this changes the calling
! conventions, and thus some functions from the standard C library will
! not work unless you recompile it first with @option{-mdalign}.
! @item -mrelax
! @opindex mrelax
! Shorten some address references at link time, when possible; uses the
! linker option @option{-relax}.
! @item -mbigtable
! @opindex mbigtable
! Use 32-bit offsets in @code{switch} tables. The default is to use
! 16-bit offsets.
! @item -mfmovd
! @opindex mfmovd
! Enable the use of the instruction @code{fmovd}.
! @item -mhitachi
! @opindex mhitachi
! Comply with the calling conventions defined by Renesas.
! @item -mnomacsave
! @opindex mnomacsave
! Mark the @code{MAC} register as call-clobbered, even if
! @option{-mhitachi} is given.
! @item -mieee
! @opindex mieee
! Increase IEEE-compliance of floating-point code.
! @item -misize
! @opindex misize
! Dump instruction size and location in the assembly code.
! @item -mpadstruct
! @opindex mpadstruct
! This option is deprecated. It pads structures to multiple of 4 bytes,
! which is incompatible with the SH ABI@.
! @item -mspace
! @opindex mspace
! Optimize for space instead of speed. Implied by @option{-Os}.
! @item -mprefergot
! @opindex mprefergot
! When generating position-independent code, emit function calls using
! the Global Offset Table instead of the Procedure Linkage Table.
! @item -musermode
! @opindex musermode
! Generate a library function call to invalidate instruction cache
! entries, after fixing up a trampoline. This library function call
! doesn't assume it can write to the whole memory address space. This
! is the default when the target is @code{sh-*-linux*}.
@end table
! @node System V Options
! @subsection Options for System V
! These additional options are available on System V Release 4 for
! compatibility with other compilers on those systems:
@table @gcctabopt
! @item -G
! @opindex G
! Create a shared object.
! It is recommended that @option{-symbolic} or @option{-shared} be used instead.
! @item -Qy
! @opindex Qy
! Identify the versions of each tool used by the compiler, in a
! @code{.ident} assembler directive in the output.
! @item -Qn
! @opindex Qn
! Refrain from adding @code{.ident} directives to the output file (this is
! the default).
! @item -YP,@var{dirs}
! @opindex YP
! Search the directories @var{dirs}, and no others, for libraries
! specified with @option{-l}.
! @item -Ym,@var{dir}
! @opindex Ym
! Look in the directory @var{dir} to find the M4 preprocessor.
! The assembler uses this option.
! @c This is supposed to go with a -Yd for predefined M4 macro files, but
! @c the generic assembler that comes with Solaris takes just -Ym.
! @end table
! @node TMS320C3x/C4x Options
! @subsection TMS320C3x/C4x Options
! @cindex TMS320C3x/C4x Options
! These @samp{-m} options are defined for TMS320C3x/C4x implementations:
! @table @gcctabopt
! @item -mcpu=@var{cpu_type}
! @opindex mcpu
! Set the instruction set, register set, and instruction scheduling
! parameters for machine type @var{cpu_type}. Supported values for
! @var{cpu_type} are @samp{c30}, @samp{c31}, @samp{c32}, @samp{c40}, and
! @samp{c44}. The default is @samp{c40} to generate code for the
! TMS320C40.
! @item -mbig-memory
! @itemx -mbig
! @itemx -msmall-memory
! @itemx -msmall
! @opindex mbig-memory
! @opindex mbig
! @opindex msmall-memory
! @opindex msmall
! Generates code for the big or small memory model. The small memory
! model assumed that all data fits into one 64K word page. At run-time
! the data page (DP) register must be set to point to the 64K page
! containing the .bss and .data program sections. The big memory model is
! the default and requires reloading of the DP register for every direct
! memory access.
! @item -mbk
! @itemx -mno-bk
! @opindex mbk
! @opindex mno-bk
! Allow (disallow) allocation of general integer operands into the block
! count register BK@.
! @item -mdb
! @itemx -mno-db
! @opindex mdb
! @opindex mno-db
! Enable (disable) generation of code using decrement and branch,
! DBcond(D), instructions. This is enabled by default for the C4x. To be
! on the safe side, this is disabled for the C3x, since the maximum
! iteration count on the C3x is @math{2^{23} + 1} (but who iterates loops more than
! @math{2^{23}} times on the C3x?). Note that GCC will try to reverse a loop so
! that it can utilize the decrement and branch instruction, but will give
! up if there is more than one memory reference in the loop. Thus a loop
! where the loop counter is decremented can generate slightly more
! efficient code, in cases where the RPTB instruction cannot be utilized.
! @item -mdp-isr-reload
! @itemx -mparanoid
! @opindex mdp-isr-reload
! @opindex mparanoid
! Force the DP register to be saved on entry to an interrupt service
! routine (ISR), reloaded to point to the data section, and restored on
! exit from the ISR@. This should not be required unless someone has
! violated the small memory model by modifying the DP register, say within
! an object library.
! @item -mmpyi
! @itemx -mno-mpyi
! @opindex mmpyi
! @opindex mno-mpyi
! For the C3x use the 24-bit MPYI instruction for integer multiplies
! instead of a library call to guarantee 32-bit results. Note that if one
! of the operands is a constant, then the multiplication will be performed
! using shifts and adds. If the @option{-mmpyi} option is not specified for the C3x,
! then squaring operations are performed inline instead of a library call.
- @item -mfast-fix
- @itemx -mno-fast-fix
- @opindex mfast-fix
- @opindex mno-fast-fix
- The C3x/C4x FIX instruction to convert a floating point value to an
- integer value chooses the nearest integer less than or equal to the
- floating point value rather than to the nearest integer. Thus if the
- floating point number is negative, the result will be incorrectly
- truncated an additional code is necessary to detect and correct this
- case. This option can be used to disable generation of the additional
- code required to correct the result.
! @item -mrptb
! @itemx -mno-rptb
! @opindex mrptb
! @opindex mno-rptb
! Enable (disable) generation of repeat block sequences using the RPTB
! instruction for zero overhead looping. The RPTB construct is only used
! for innermost loops that do not call functions or jump across the loop
! boundaries. There is no advantage having nested RPTB loops due to the
! overhead required to save and restore the RC, RS, and RE registers.
! This is enabled by default with @option{-O2}.
! @item -mrpts=@var{count}
! @itemx -mno-rpts
! @opindex mrpts
! @opindex mno-rpts
! Enable (disable) the use of the single instruction repeat instruction
! RPTS@. If a repeat block contains a single instruction, and the loop
! count can be guaranteed to be less than the value @var{count}, GCC will
! emit a RPTS instruction instead of a RPTB@. If no value is specified,
! then a RPTS will be emitted even if the loop count cannot be determined
! at compile time. Note that the repeated instruction following RPTS does
! not have to be reloaded from memory each iteration, thus freeing up the
! CPU buses for operands. However, since interrupts are blocked by this
! instruction, it is disabled by default.
! @item -mloop-unsigned
! @itemx -mno-loop-unsigned
! @opindex mloop-unsigned
! @opindex mno-loop-unsigned
! The maximum iteration count when using RPTS and RPTB (and DB on the C40)
! is @math{2^{31} + 1} since these instructions test if the iteration count is
! negative to terminate the loop. If the iteration count is unsigned
! there is a possibility than the @math{2^{31} + 1} maximum iteration count may be
! exceeded. This switch allows an unsigned iteration count.
! @item -mti
! @opindex mti
! Try to emit an assembler syntax that the TI assembler (asm30) is happy
! with. This also enforces compatibility with the API employed by the TI
! C3x C compiler. For example, long doubles are passed as structures
! rather than in floating point registers.
! @item -mregparm
! @itemx -mmemparm
! @opindex mregparm
! @opindex mmemparm
! Generate code that uses registers (stack) for passing arguments to functions.
! By default, arguments are passed in registers where possible rather
! than by pushing arguments on to the stack.
! @item -mparallel-insns
! @itemx -mno-parallel-insns
! @opindex mparallel-insns
! @opindex mno-parallel-insns
! Allow the generation of parallel instructions. This is enabled by
! default with @option{-O2}.
! @item -mparallel-mpy
! @itemx -mno-parallel-mpy
! @opindex mparallel-mpy
! @opindex mno-parallel-mpy
! Allow the generation of MPY||ADD and MPY||SUB parallel instructions,
! provided @option{-mparallel-insns} is also specified. These instructions have
! tight register constraints which can pessimize the code generation
! of large functions.
@end table
! @node V850 Options
! @subsection V850 Options
! @cindex V850 Options
! These @samp{-m} options are defined for V850 implementations:
@table @gcctabopt
! @item -mlong-calls
! @itemx -mno-long-calls
! @opindex mlong-calls
! @opindex mno-long-calls
! Treat all calls as being far away (near). If calls are assumed to be
! far away, the compiler will always load the functions address up into a
! register, and call indirect through the pointer.
! @item -mno-ep
! @itemx -mep
! @opindex mno-ep
! @opindex mep
! Do not optimize (do optimize) basic blocks that use the same index
! pointer 4 or more times to copy pointer into the @code{ep} register, and
! use the shorter @code{sld} and @code{sst} instructions. The @option{-mep}
! option is on by default if you optimize.
! @item -mno-prolog-function
! @itemx -mprolog-function
! @opindex mno-prolog-function
! @opindex mprolog-function
! Do not use (do use) external functions to save and restore registers
! at the prologue and epilogue of a function. The external functions
! are slower, but use less code space if more than one function saves
! the same number of registers. The @option{-mprolog-function} option
! is on by default if you optimize.
! @item -mspace
! @opindex mspace
! Try to make the code as small as possible. At present, this just turns
! on the @option{-mep} and @option{-mprolog-function} options.
! @item -mtda=@var{n}
! @opindex mtda
! Put static or global variables whose size is @var{n} bytes or less into
! the tiny data area that register @code{ep} points to. The tiny data
! area can hold up to 256 bytes in total (128 bytes for byte references).
! @item -msda=@var{n}
! @opindex msda
! Put static or global variables whose size is @var{n} bytes or less into
! the small data area that register @code{gp} points to. The small data
! area can hold up to 64 kilobytes.
! @item -mzda=@var{n}
! @opindex mzda
! Put static or global variables whose size is @var{n} bytes or less into
! the first 32 kilobytes of memory.
! @item -mv850
! @opindex mv850
! Specify that the target processor is the V850.
! @item -mbig-switch
! @opindex mbig-switch
! Generate code suitable for big switch tables. Use this option only if
! the assembler/linker complain about out of range branches within a switch
! table.
! @item -mapp-regs
! @opindex mapp-regs
! This option will cause r2 and r5 to be used in the code generated by
! the compiler. This setting is the default.
! @item -mno-app-regs
! @opindex mno-app-regs
! This option will cause r2 and r5 to be treated as fixed registers.
! @item -mv850e1
! @opindex mv850e1
! Specify that the target processor is the V850E1. The preprocessor
! constants @samp{__v850e1__} and @samp{__v850e__} will be defined if
! this option is used.
! @item -mv850e
! @opindex mv850e
! Specify that the target processor is the V850E. The preprocessor
! constant @samp{__v850e__} will be defined if this option is used.
! If neither @option{-mv850} nor @option{-mv850e} nor @option{-mv850e1}
! are defined then a default target processor will be chosen and the
! relevant @samp{__v850*__} preprocessor constant will be defined.
! The preprocessor constants @samp{__v850} and @samp{__v851__} are always
! defined, regardless of which processor variant is the target.
! @item -mdisable-callt
! @opindex mdisable-callt
! This option will suppress generation of the CALLT instruction for the
! v850e and v850e1 flavors of the v850 architecture. The default is
! @option{-mno-disable-callt} which allows the CALLT instruction to be used.
! @end table
! @node ARC Options
! @subsection ARC Options
! @cindex ARC Options
! These options are defined for ARC implementations:
! @table @gcctabopt
! @item -EL
! @opindex EL
! Compile code for little endian mode. This is the default.
! @item -EB
! @opindex EB
! Compile code for big endian mode.
! @item -mmangle-cpu
! @opindex mmangle-cpu
! Prepend the name of the cpu to all public symbol names.
! In multiple-processor systems, there are many ARC variants with different
! instruction and register set characteristics. This flag prevents code
! compiled for one cpu to be linked with code compiled for another.
! No facility exists for handling variants that are ``almost identical''.
! This is an all or nothing option.
! @item -mcpu=@var{cpu}
! @opindex mcpu
! Compile code for ARC variant @var{cpu}.
! Which variants are supported depend on the configuration.
! All variants support @option{-mcpu=base}, this is the default.
! @item -mtext=@var{text-section}
! @itemx -mdata=@var{data-section}
! @itemx -mrodata=@var{readonly-data-section}
! @opindex mtext
! @opindex mdata
! @opindex mrodata
! Put functions, data, and readonly data in @var{text-section},
! @var{data-section}, and @var{readonly-data-section} respectively
! by default. This can be overridden with the @code{section} attribute.
! @xref{Variable Attributes}.
! @end table
! @node NS32K Options
! @subsection NS32K Options
! @cindex NS32K options
! These are the @samp{-m} options defined for the 32000 series. The default
! values for these options depends on which style of 32000 was selected when
! the compiler was configured; the defaults for the most common choices are
! given below.
! @table @gcctabopt
! @item -m32032
! @itemx -m32032
! @opindex m32032
! @opindex m32032
! Generate output for a 32032. This is the default
! when the compiler is configured for 32032 and 32016 based systems.
! @item -m32332
! @itemx -m32332
! @opindex m32332
! @opindex m32332
! Generate output for a 32332. This is the default
! when the compiler is configured for 32332-based systems.
! @item -m32532
! @itemx -m32532
! @opindex m32532
! @opindex m32532
! Generate output for a 32532. This is the default
! when the compiler is configured for 32532-based systems.
! @item -m32081
! @opindex m32081
! Generate output containing 32081 instructions for floating point.
! This is the default for all systems.
! @item -m32381
! @opindex m32381
! Generate output containing 32381 instructions for floating point. This
! also implies @option{-m32081}. The 32381 is only compatible with the 32332
! and 32532 cpus. This is the default for the pc532-netbsd configuration.
! @item -mmulti-add
! @opindex mmulti-add
! Try and generate multiply-add floating point instructions @code{polyF}
! and @code{dotF}. This option is only available if the @option{-m32381}
! option is in effect. Using these instructions requires changes to
! register allocation which generally has a negative impact on
! performance. This option should only be enabled when compiling code
! particularly likely to make heavy use of multiply-add instructions.
! @item -mnomulti-add
! @opindex mnomulti-add
! Do not try and generate multiply-add floating point instructions
! @code{polyF} and @code{dotF}. This is the default on all platforms.
! @item -msoft-float
! @opindex msoft-float
! Generate output containing library calls for floating point.
! @strong{Warning:} the requisite libraries may not be available.
! @item -mieee-compare
! @itemx -mno-ieee-compare
! @opindex mieee-compare
! @opindex mno-ieee-compare
! Control whether or not the compiler uses IEEE floating point
! comparisons. These handle correctly the case where the result of a
! comparison is unordered.
! @strong{Warning:} the requisite kernel support may not be available.
! @item -mnobitfield
! @opindex mnobitfield
! Do not use the bit-field instructions. On some machines it is faster to
! use shifting and masking operations. This is the default for the pc532.
! @item -mbitfield
! @opindex mbitfield
! Do use the bit-field instructions. This is the default for all platforms
! except the pc532.
! @item -mrtd
! @opindex mrtd
! Use a different function-calling convention, in which functions
! that take a fixed number of arguments return pop their
! arguments on return with the @code{ret} instruction.
! This calling convention is incompatible with the one normally
! used on Unix, so you cannot use it if you need to call libraries
! compiled with the Unix compiler.
! Also, you must provide function prototypes for all functions that
! take variable numbers of arguments (including @code{printf});
! otherwise incorrect code will be generated for calls to those
! functions.
! In addition, seriously incorrect code will result if you call a
! function with too many arguments. (Normally, extra arguments are
! harmlessly ignored.)
! This option takes its name from the 680x0 @code{rtd} instruction.
! @item -mregparam
! @opindex mregparam
! Use a different function-calling convention where the first two arguments
! are passed in registers.
! This calling convention is incompatible with the one normally
! used on Unix, so you cannot use it if you need to call libraries
! compiled with the Unix compiler.
! @item -mnoregparam
! @opindex mnoregparam
! Do not pass any arguments in registers. This is the default for all
! targets.
! @item -msb
! @opindex msb
! It is OK to use the sb as an index register which is always loaded with
! zero. This is the default for the pc532-netbsd target.
! @item -mnosb
! @opindex mnosb
! The sb register is not available for use or has not been initialized to
! zero by the run time system. This is the default for all targets except
! the pc532-netbsd. It is also implied whenever @option{-mhimem} or
! @option{-fpic} is set.
! @item -mhimem
! @opindex mhimem
! Many ns32000 series addressing modes use displacements of up to 512MB@.
! If an address is above 512MB then displacements from zero can not be used.
! This option causes code to be generated which can be loaded above 512MB@.
! This may be useful for operating systems or ROM code.
! @item -mnohimem
! @opindex mnohimem
! Assume code will be loaded in the first 512MB of virtual address space.
! This is the default for all platforms.
! @end table
! @node AVR Options
! @subsection AVR Options
! @cindex AVR Options
! These options are defined for AVR implementations:
! @table @gcctabopt
! @item -mmcu=@var{mcu}
! @opindex mmcu
! Specify ATMEL AVR instruction set or MCU type.
! Instruction set avr1 is for the minimal AVR core, not supported by the C
! compiler, only for assembler programs (MCU types: at90s1200, attiny10,
! attiny11, attiny12, attiny15, attiny28).
! Instruction set avr2 (default) is for the classic AVR core with up to
! 8K program memory space (MCU types: at90s2313, at90s2323, attiny22,
! at90s2333, at90s2343, at90s4414, at90s4433, at90s4434, at90s8515,
! at90c8534, at90s8535).
! Instruction set avr3 is for the classic AVR core with up to 128K program
! memory space (MCU types: atmega103, atmega603, at43usb320, at76c711).
! Instruction set avr4 is for the enhanced AVR core with up to 8K program
! memory space (MCU types: atmega8, atmega83, atmega85).
! Instruction set avr5 is for the enhanced AVR core with up to 128K program
! memory space (MCU types: atmega16, atmega161, atmega163, atmega32, atmega323,
! atmega64, atmega128, at43usb355, at94k).
! @item -msize
! @opindex msize
! Output instruction sizes to the asm file.
! @item -minit-stack=@var{N}
! @opindex minit-stack
! Specify the initial stack address, which may be a symbol or numeric value,
! @samp{__stack} is the default.
! @item -mno-interrupts
! @opindex mno-interrupts
! Generated code is not compatible with hardware interrupts.
! Code size will be smaller.
! @item -mcall-prologues
! @opindex mcall-prologues
! Functions prologues/epilogues expanded as call to appropriate
! subroutines. Code size will be smaller.
! @item -mno-tablejump
! @opindex mno-tablejump
! Do not generate tablejump insns which sometimes increase code size.
! @item -mtiny-stack
! @opindex mtiny-stack
! Change only the low 8 bits of the stack pointer.
! @item -mint8
! @opindex mint8
! Assume int to be 8 bit integer. This affects the sizes of all types: A
! char will be 1 byte, an int will be 1 byte, an long will be 2 bytes
! and long long will be 4 bytes. Please note that this option does not
! comply to the C standards, but it will provide you with smaller code
! size.
! @end table
! @node MCore Options
! @subsection MCore Options
! @cindex MCore options
! These are the @samp{-m} options defined for the Motorola M*Core
! processors.
! @table @gcctabopt
! @item -mhardlit
! @itemx -mno-hardlit
! @opindex mhardlit
! @opindex mno-hardlit
! Inline constants into the code stream if it can be done in two
! instructions or less.
! @item -mdiv
! @itemx -mno-div
! @opindex mdiv
! @opindex mno-div
! Use the divide instruction. (Enabled by default).
! @item -mrelax-immediate
! @itemx -mno-relax-immediate
! @opindex mrelax-immediate
! @opindex mno-relax-immediate
! Allow arbitrary sized immediates in bit operations.
! @item -mwide-bitfields
! @itemx -mno-wide-bitfields
! @opindex mwide-bitfields
! @opindex mno-wide-bitfields
! Always treat bit-fields as int-sized.
! @item -m4byte-functions
! @itemx -mno-4byte-functions
! @opindex m4byte-functions
! @opindex mno-4byte-functions
! Force all functions to be aligned to a four byte boundary.
! @item -mcallgraph-data
! @itemx -mno-callgraph-data
! @opindex mcallgraph-data
! @opindex mno-callgraph-data
! Emit callgraph information.
! @item -mslow-bytes
! @itemx -mno-slow-bytes
! @opindex mslow-bytes
! @opindex mno-slow-bytes
! Prefer word access when reading byte quantities.
! @item -mlittle-endian
! @itemx -mbig-endian
! @opindex mlittle-endian
! @opindex mbig-endian
! Generate code for a little endian target.
! @item -m210
! @itemx -m340
! @opindex m210
! @opindex m340
! Generate code for the 210 processor.
! @end table
! @node IA-64 Options
! @subsection IA-64 Options
! @cindex IA-64 Options
! These are the @samp{-m} options defined for the Intel IA-64 architecture.
! @table @gcctabopt
! @item -mbig-endian
! @opindex mbig-endian
! Generate code for a big endian target. This is the default for HP-UX@.
! @item -mlittle-endian
! @opindex mlittle-endian
! Generate code for a little endian target. This is the default for AIX5
! and GNU/Linux.
! @item -mgnu-as
! @itemx -mno-gnu-as
! @opindex mgnu-as
! @opindex mno-gnu-as
! Generate (or don't) code for the GNU assembler. This is the default.
! @c Also, this is the default if the configure option @option{--with-gnu-as}
! @c is used.
! @item -mgnu-ld
! @itemx -mno-gnu-ld
! @opindex mgnu-ld
! @opindex mno-gnu-ld
! Generate (or don't) code for the GNU linker. This is the default.
! @c Also, this is the default if the configure option @option{--with-gnu-ld}
! @c is used.
! @item -mno-pic
! @opindex mno-pic
! Generate code that does not use a global pointer register. The result
! is not position independent code, and violates the IA-64 ABI@.
! @item -mvolatile-asm-stop
! @itemx -mno-volatile-asm-stop
! @opindex mvolatile-asm-stop
! @opindex mno-volatile-asm-stop
! Generate (or don't) a stop bit immediately before and after volatile asm
! statements.
! @item -mb-step
! @opindex mb-step
! Generate code that works around Itanium B step errata.
! @item -mregister-names
! @itemx -mno-register-names
! @opindex mregister-names
! @opindex mno-register-names
! Generate (or don't) @samp{in}, @samp{loc}, and @samp{out} register names for
! the stacked registers. This may make assembler output more readable.
! @item -mno-sdata
@itemx -msdata
! @opindex mno-sdata
@opindex msdata
! Disable (or enable) optimizations that use the small data section. This may
! be useful for working around optimizer bugs.
! @item -mconstant-gp
! @opindex mconstant-gp
! Generate code that uses a single constant global pointer value. This is
! useful when compiling kernel code.
! @item -mauto-pic
! @opindex mauto-pic
! Generate code that is self-relocatable. This implies @option{-mconstant-gp}.
! This is useful when compiling firmware code.
! @item -minline-float-divide-min-latency
! @opindex minline-float-divide-min-latency
! Generate code for inline divides of floating point values
! using the minimum latency algorithm.
! @item -minline-float-divide-max-throughput
! @opindex minline-float-divide-max-throughput
! Generate code for inline divides of floating point values
! using the maximum throughput algorithm.
! @item -minline-int-divide-min-latency
! @opindex minline-int-divide-min-latency
! Generate code for inline divides of integer values
! using the minimum latency algorithm.
! @item -minline-int-divide-max-throughput
! @opindex minline-int-divide-max-throughput
! Generate code for inline divides of integer values
! using the maximum throughput algorithm.
! @item -mno-dwarf2-asm
! @itemx -mdwarf2-asm
! @opindex mno-dwarf2-asm
! @opindex mdwarf2-asm
! Don't (or do) generate assembler code for the DWARF2 line number debugging
! info. This may be useful when not using the GNU assembler.
! @item -mfixed-range=@var{register-range}
! @opindex mfixed-range
! Generate code treating the given register range as fixed registers.
! A fixed register is one that the register allocator can not use. This is
! useful when compiling kernel code. A register range is specified as
! two registers separated by a dash. Multiple register ranges can be
! specified separated by a comma.
- @item -mearly-stop-bits
- @itemx -mno-early-stop-bits
- @opindex mearly-stop-bits
- @opindex mno-early-stop-bits
- Allow stop bits to be placed earlier than immediately preceding the
- instruction that triggered the stop bit. This can improve instruction
- scheduling, but does not always do so.
@end table
@node S/390 and zSeries Options
--- 6214,10288 ----
machine description. The default for the options is also defined by
that macro, which enables you to change the defaults.
+ @c keep this menu in alpha numeric order
@menu
! * ARC Options::
* ARM Options::
! * AVR Options::
! * CRIS Options::
* Darwin Options::
* DEC Alpha Options::
* DEC Alpha/VMS Options::
+ * FRV Options::
* H8/300 Options::
+ * HPPA Options::
+ * i386 and x86-64 Options::
+ * IA-64 Options::
+ * M32R/D Options::
+ * M680x0 Options::
+ * M68hc1x Options::
+ * MCore Options::
+ * MIPS Options::
+ * MMIX Options::
+ * MN10300 Options::
+ * NS32K Options::
+ * PDP-11 Options::
+ * PowerPC Options::
+ * RS/6000 and PowerPC Options::
+ * S/390 and zSeries Options::
* SH Options::
+ * SPARC Options::
* System V Options::
* TMS320C3x/C4x Options::
* V850 Options::
! * VAX Options::
! * x86-64 Options::
* Xstormy16 Options::
* Xtensa Options::
! * zSeries Options::
@end menu
! @node ARC Options
! @subsection ARC Options
! @cindex ARC Options
! These options are defined for ARC implementations:
@table @gcctabopt
! @item -EL
! @opindex EL
! Compile code for little endian mode. This is the default.
! @item -EB
! @opindex EB
! Compile code for big endian mode.
! @item -mmangle-cpu
! @opindex mmangle-cpu
! Prepend the name of the cpu to all public symbol names.
! In multiple-processor systems, there are many ARC variants with different
! instruction and register set characteristics. This flag prevents code
! compiled for one cpu to be linked with code compiled for another.
! No facility exists for handling variants that are ``almost identical''.
! This is an all or nothing option.
! @item -mcpu=@var{cpu}
! @opindex mcpu
! Compile code for ARC variant @var{cpu}.
! Which variants are supported depend on the configuration.
! All variants support @option{-mcpu=base}, this is the default.
! @item -mtext=@var{text-section}
! @itemx -mdata=@var{data-section}
! @itemx -mrodata=@var{readonly-data-section}
! @opindex mtext
! @opindex mdata
! @opindex mrodata
! Put functions, data, and readonly data in @var{text-section},
! @var{data-section}, and @var{readonly-data-section} respectively
! by default. This can be overridden with the @code{section} attribute.
! @xref{Variable Attributes}.
! @end table
! @node ARM Options
! @subsection ARM Options
! @cindex ARM options
! These @samp{-m} options are defined for Advanced RISC Machines (ARM)
! architectures:
! @table @gcctabopt
! @item -mabi=@var{name}
! @opindex mabi
! Generate code for the specified ABI. Permissible values are: @samp{apcs-gnu},
! @samp{atpcs}, @samp{aapcs} and @samp{iwmmxt}.
! @item -mapcs-frame
! @opindex mapcs-frame
! Generate a stack frame that is compliant with the ARM Procedure Call
! Standard for all functions, even if this is not strictly necessary for
! correct execution of the code. Specifying @option{-fomit-frame-pointer}
! with this option will cause the stack frames not to be generated for
! leaf functions. The default is @option{-mno-apcs-frame}.
! @item -mapcs
! @opindex mapcs
! This is a synonym for @option{-mapcs-frame}.
! @ignore
! @c not currently implemented
! @item -mapcs-stack-check
! @opindex mapcs-stack-check
! Generate code to check the amount of stack space available upon entry to
! every function (that actually uses some stack space). If there is
! insufficient space available then either the function
! @samp{__rt_stkovf_split_small} or @samp{__rt_stkovf_split_big} will be
! called, depending upon the amount of stack space required. The run time
! system is required to provide these functions. The default is
! @option{-mno-apcs-stack-check}, since this produces smaller code.
! @c not currently implemented
! @item -mapcs-float
! @opindex mapcs-float
! Pass floating point arguments using the float point registers. This is
! one of the variants of the APCS@. This option is recommended if the
! target hardware has a floating point unit or if a lot of floating point
! arithmetic is going to be performed by the code. The default is
! @option{-mno-apcs-float}, since integer only code is slightly increased in
! size if @option{-mapcs-float} is used.
+ @c not currently implemented
+ @item -mapcs-reentrant
+ @opindex mapcs-reentrant
+ Generate reentrant, position independent code. The default is
+ @option{-mno-apcs-reentrant}.
+ @end ignore
! @item -mthumb-interwork
! @opindex mthumb-interwork
! Generate code which supports calling between the ARM and Thumb
! instruction sets. Without this option the two instruction sets cannot
! be reliably used inside one program. The default is
! @option{-mno-thumb-interwork}, since slightly larger code is generated
! when @option{-mthumb-interwork} is specified.
! @item -mno-sched-prolog
! @opindex mno-sched-prolog
! Prevent the reordering of instructions in the function prolog, or the
! merging of those instruction with the instructions in the function's
! body. This means that all functions will start with a recognizable set
! of instructions (or in fact one of a choice from a small set of
! different function prologues), and this information can be used to
! locate the start if functions inside an executable piece of code. The
! default is @option{-msched-prolog}.
!
! @item -mhard-float
! @opindex mhard-float
! Generate output containing floating point instructions. This is the
! default.
@item -msoft-float
@opindex msoft-float
Generate output containing library calls for floating point.
! @strong{Warning:} the requisite libraries are not available for all ARM
targets. Normally the facilities of the machine's usual C compiler are
! used, but this cannot be done directly in cross-compilation. You must make
! your own arrangements to provide suitable library functions for
! cross-compilation.
! @option{-msoft-float} changes the calling convention in the output file;
! therefore, it is only useful if you compile @emph{all} of a program with
! this option. In particular, you need to compile @file{libgcc.a}, the
! library that comes with GCC, with @option{-msoft-float} in order for
! this to work.
! @item -mfloat-abi=@var{name}
! @opindex mfloat-abi
! Specifies which ABI to use for floating point values. Permissible values
! are: @samp{soft}, @samp{softfp} and @samp{hard}.
! @samp{soft} and @samp{hard} are equivalent to @option{-msoft-float}
! and @option{-mhard-float} respectively. @samp{softfp} allows the generation
! of floating point instructions, but still uses the soft-float calling
! conventions.
! @item -mlittle-endian
! @opindex mlittle-endian
! Generate code for a processor running in little-endian mode. This is
! the default for all standard configurations.
! @item -mbig-endian
! @opindex mbig-endian
! Generate code for a processor running in big-endian mode; the default is
! to compile code for a little-endian processor.
! @item -mwords-little-endian
! @opindex mwords-little-endian
! This option only applies when generating code for big-endian processors.
! Generate code for a little-endian word order but a big-endian byte
! order. That is, a byte order of the form @samp{32107654}. Note: this
! option should only be used if you require compatibility with code for
! big-endian ARM processors generated by versions of the compiler prior to
! 2.8.
! @item -mcpu=@var{name}
! @opindex mcpu
! This specifies the name of the target ARM processor. GCC uses this name
! to determine what kind of instructions it can emit when generating
! assembly code. Permissible names are: @samp{arm2}, @samp{arm250},
! @samp{arm3}, @samp{arm6}, @samp{arm60}, @samp{arm600}, @samp{arm610},
! @samp{arm620}, @samp{arm7}, @samp{arm7m}, @samp{arm7d}, @samp{arm7dm},
! @samp{arm7di}, @samp{arm7dmi}, @samp{arm70}, @samp{arm700},
! @samp{arm700i}, @samp{arm710}, @samp{arm710c}, @samp{arm7100},
! @samp{arm7500}, @samp{arm7500fe}, @samp{arm7tdmi}, @samp{arm8},
! @samp{strongarm}, @samp{strongarm110}, @samp{strongarm1100},
! @samp{arm8}, @samp{arm810}, @samp{arm9}, @samp{arm9e}, @samp{arm920},
! @samp{arm920t}, @samp{arm926ejs}, @samp{arm940t}, @samp{arm9tdmi},
! @samp{arm10tdmi}, @samp{arm1020t}, @samp{arm1026ejs},
! @samp{arm1136js}, @samp{arm1136jfs} ,@samp{xscale}, @samp{iwmmxt},
! @samp{ep9312}.
! @itemx -mtune=@var{name}
! @opindex mtune
! This option is very similar to the @option{-mcpu=} option, except that
! instead of specifying the actual target processor type, and hence
! restricting which instructions can be used, it specifies that GCC should
! tune the performance of the code as if the target were of the type
! specified in this option, but still choosing the instructions that it
! will generate based on the cpu specified by a @option{-mcpu=} option.
! For some ARM implementations better performance can be obtained by using
! this option.
! @item -march=@var{name}
! @opindex march
! This specifies the name of the target ARM architecture. GCC uses this
! name to determine what kind of instructions it can emit when generating
! assembly code. This option can be used in conjunction with or instead
! of the @option{-mcpu=} option. Permissible names are: @samp{armv2},
! @samp{armv2a}, @samp{armv3}, @samp{armv3m}, @samp{armv4}, @samp{armv4t},
! @samp{armv5}, @samp{armv5t}, @samp{armv5te}, @samp{armv6}, @samp{armv6j},
! @samp{iwmmxt}, @samp{ep9312}.
! @item -mfpu=@var{name}
! @itemx -mfpe=@var{number}
! @itemx -mfp=@var{number}
! @opindex mfpu
! @opindex mfpe
! @opindex mfp
! This specifies what floating point hardware (or hardware emulation) is
! available on the target. Permissible names are: @samp{fpa}, @samp{fpe2},
! @samp{fpe3}, @samp{maverick}, @samp{vfp}. @option{-mfp} and @option{-mfpe}
! are synonyms for @option{-mfpu}=@samp{fpe}@var{number}, for compatibility
! with older versions of GCC@.
! If @option{-msoft-float} is specified this specifies the format of
! floating point values.
! @item -mstructure-size-boundary=@var{n}
! @opindex mstructure-size-boundary
! The size of all structures and unions will be rounded up to a multiple
! of the number of bits set by this option. Permissible values are 8, 32
! and 64. The default value varies for different toolchains. For the COFF
! targeted toolchain the default value is 8. A value of 64 is only allowed
! if the underlying ABI supports it.
! Specifying the larger number can produce faster, more efficient code, but
! can also increase the size of the program. Different values are potentially
! incompatible. Code compiled with one value cannot necessarily expect to
! work with code or libraries compiled with another value, if they exchange
! information using structures or unions.
! @item -mabort-on-noreturn
! @opindex mabort-on-noreturn
! Generate a call to the function @code{abort} at the end of a
! @code{noreturn} function. It will be executed if the function tries to
! return.
@item -mlong-calls
@itemx -mno-long-calls
@opindex mlong-calls
@opindex mno-long-calls
! Tells the compiler to perform function calls by first loading the
! address of the function into a register and then performing a subroutine
! call on this register. This switch is needed if the target function
! will lie outside of the 64 megabyte addressing range of the offset based
! version of subroutine call instruction.
! Even if this switch is enabled, not all function calls will be turned
! into long calls. The heuristic is that static functions, functions
! which have the @samp{short-call} attribute, functions that are inside
! the scope of a @samp{#pragma no_long_calls} directive and functions whose
! definitions have already been compiled within the current compilation
! unit, will not be turned into long calls. The exception to this rule is
! that weak function definitions, functions with the @samp{long-call}
! attribute or the @samp{section} attribute, and functions that are within
! the scope of a @samp{#pragma long_calls} directive, will always be
! turned into long calls.
! This feature is not enabled by default. Specifying
! @option{-mno-long-calls} will restore the default behavior, as will
! placing the function calls within the scope of a @samp{#pragma
! long_calls_off} directive. Note these switches have no effect on how
! the compiler generates code to handle function calls via function
! pointers.
! @item -mnop-fun-dllimport
! @opindex mnop-fun-dllimport
! Disable support for the @code{dllimport} attribute.
! @item -msingle-pic-base
! @opindex msingle-pic-base
! Treat the register used for PIC addressing as read-only, rather than
! loading it in the prologue for each function. The run-time system is
! responsible for initializing this register with an appropriate value
! before execution begins.
! @item -mpic-register=@var{reg}
! @opindex mpic-register
! Specify the register to be used for PIC addressing. The default is R10
! unless stack-checking is enabled, when R9 is used.
! @item -mcirrus-fix-invalid-insns
! @opindex mcirrus-fix-invalid-insns
! @opindex mno-cirrus-fix-invalid-insns
! Insert NOPs into the instruction stream to in order to work around
! problems with invalid Maverick instruction combinations. This option
! is only valid if the @option{-mcpu=ep9312} option has been used to
! enable generation of instructions for the Cirrus Maverick floating
! point co-processor. This option is not enabled by default, since the
! problem is only present in older Maverick implementations. The default
! can be re-enabled by use of the @option{-mno-cirrus-fix-invalid-insns}
! switch.
! @item -mpoke-function-name
! @opindex mpoke-function-name
! Write the name of each function into the text section, directly
! preceding the function prologue. The generated code is similar to this:
! @smallexample
! t0
! .ascii "arm_poke_function_name", 0
! .align
! t1
! .word 0xff000000 + (t1 - t0)
! arm_poke_function_name
! mov ip, sp
! stmfd sp!, @{fp, ip, lr, pc@}
! sub fp, ip, #4
! @end smallexample
! When performing a stack backtrace, code can inspect the value of
! @code{pc} stored at @code{fp + 0}. If the trace function then looks at
! location @code{pc - 12} and the top 8 bits are set, then we know that
! there is a function name embedded immediately preceding this location
! and has length @code{((pc[-3]) & 0xff000000)}.
! @item -mthumb
! @opindex mthumb
! Generate code for the 16-bit Thumb instruction set. The default is to
! use the 32-bit ARM instruction set.
! @item -mtpcs-frame
! @opindex mtpcs-frame
! Generate a stack frame that is compliant with the Thumb Procedure Call
! Standard for all non-leaf functions. (A leaf function is one that does
! not call any other functions.) The default is @option{-mno-tpcs-frame}.
! @item -mtpcs-leaf-frame
! @opindex mtpcs-leaf-frame
! Generate a stack frame that is compliant with the Thumb Procedure Call
! Standard for all leaf functions. (A leaf function is one that does
! not call any other functions.) The default is @option{-mno-apcs-leaf-frame}.
! @item -mcallee-super-interworking
! @opindex mcallee-super-interworking
! Gives all externally visible functions in the file being compiled an ARM
! instruction set header which switches to Thumb mode before executing the
! rest of the function. This allows these functions to be called from
! non-interworking code.
! @item -mcaller-super-interworking
! @opindex mcaller-super-interworking
! Allows calls via function pointers (including virtual functions) to
! execute correctly regardless of whether the target code has been
! compiled for interworking or not. There is a small overhead in the cost
! of executing a function pointer if this option is enabled.
! @end table
! @node AVR Options
! @subsection AVR Options
! @cindex AVR Options
! These options are defined for AVR implementations:
! @table @gcctabopt
! @item -mmcu=@var{mcu}
! @opindex mmcu
! Specify ATMEL AVR instruction set or MCU type.
! Instruction set avr1 is for the minimal AVR core, not supported by the C
! compiler, only for assembler programs (MCU types: at90s1200, attiny10,
! attiny11, attiny12, attiny15, attiny28).
! Instruction set avr2 (default) is for the classic AVR core with up to
! 8K program memory space (MCU types: at90s2313, at90s2323, attiny22,
! at90s2333, at90s2343, at90s4414, at90s4433, at90s4434, at90s8515,
! at90c8534, at90s8535).
! Instruction set avr3 is for the classic AVR core with up to 128K program
! memory space (MCU types: atmega103, atmega603, at43usb320, at76c711).
! Instruction set avr4 is for the enhanced AVR core with up to 8K program
! memory space (MCU types: atmega8, atmega83, atmega85).
! Instruction set avr5 is for the enhanced AVR core with up to 128K program
! memory space (MCU types: atmega16, atmega161, atmega163, atmega32, atmega323,
! atmega64, atmega128, at43usb355, at94k).
! @item -msize
! @opindex msize
! Output instruction sizes to the asm file.
! @item -minit-stack=@var{N}
! @opindex minit-stack
! Specify the initial stack address, which may be a symbol or numeric value,
! @samp{__stack} is the default.
! @item -mno-interrupts
! @opindex mno-interrupts
! Generated code is not compatible with hardware interrupts.
! Code size will be smaller.
! @item -mcall-prologues
! @opindex mcall-prologues
! Functions prologues/epilogues expanded as call to appropriate
! subroutines. Code size will be smaller.
! @item -mno-tablejump
! @opindex mno-tablejump
! Do not generate tablejump insns which sometimes increase code size.
! @item -mtiny-stack
! @opindex mtiny-stack
! Change only the low 8 bits of the stack pointer.
! @item -mint8
! @opindex mint8
! Assume int to be 8 bit integer. This affects the sizes of all types: A
! char will be 1 byte, an int will be 1 byte, an long will be 2 bytes
! and long long will be 4 bytes. Please note that this option does not
! comply to the C standards, but it will provide you with smaller code
! size.
! @end table
! @node CRIS Options
! @subsection CRIS Options
! @cindex CRIS Options
! These options are defined specifically for the CRIS ports.
! @table @gcctabopt
! @item -march=@var{architecture-type}
! @itemx -mcpu=@var{architecture-type}
! @opindex march
! @opindex mcpu
! Generate code for the specified architecture. The choices for
! @var{architecture-type} are @samp{v3}, @samp{v8} and @samp{v10} for
! respectively ETRAX@w{ }4, ETRAX@w{ }100, and ETRAX@w{ }100@w{ }LX.
! Default is @samp{v0} except for cris-axis-linux-gnu, where the default is
! @samp{v10}.
! @item -mtune=@var{architecture-type}
@opindex mtune
! Tune to @var{architecture-type} everything applicable about the generated
! code, except for the ABI and the set of available instructions. The
! choices for @var{architecture-type} are the same as for
! @option{-march=@var{architecture-type}}.
! @item -mmax-stack-frame=@var{n}
! @opindex mmax-stack-frame
! Warn when the stack frame of a function exceeds @var{n} bytes.
! @item -melinux-stacksize=@var{n}
! @opindex melinux-stacksize
! Only available with the @samp{cris-axis-aout} target. Arranges for
! indications in the program to the kernel loader that the stack of the
! program should be set to @var{n} bytes.
! @item -metrax4
! @itemx -metrax100
! @opindex metrax4
! @opindex metrax100
! The options @option{-metrax4} and @option{-metrax100} are synonyms for
! @option{-march=v3} and @option{-march=v8} respectively.
! @item -mmul-bug-workaround
! @itemx -mno-mul-bug-workaround
! @opindex mmul-bug-workaround
! @opindex mno-mul-bug-workaround
! Work around a bug in the @code{muls} and @code{mulu} instructions for CPU
! models where it applies. This option is active by default.
! @item -mpdebug
! @opindex mpdebug
! Enable CRIS-specific verbose debug-related information in the assembly
! code. This option also has the effect to turn off the @samp{#NO_APP}
! formatted-code indicator to the assembler at the beginning of the
! assembly file.
! @item -mcc-init
! @opindex mcc-init
! Do not use condition-code results from previous instruction; always emit
! compare and test instructions before use of condition codes.
! @item -mno-side-effects
! @opindex mno-side-effects
! Do not emit instructions with side-effects in addressing modes other than
! post-increment.
! @item -mstack-align
! @itemx -mno-stack-align
! @itemx -mdata-align
! @itemx -mno-data-align
! @itemx -mconst-align
! @itemx -mno-const-align
! @opindex mstack-align
! @opindex mno-stack-align
! @opindex mdata-align
! @opindex mno-data-align
! @opindex mconst-align
! @opindex mno-const-align
! These options (no-options) arranges (eliminate arrangements) for the
! stack-frame, individual data and constants to be aligned for the maximum
! single data access size for the chosen CPU model. The default is to
! arrange for 32-bit alignment. ABI details such as structure layout are
! not affected by these options.
! @item -m32-bit
! @itemx -m16-bit
! @itemx -m8-bit
! @opindex m32-bit
! @opindex m16-bit
! @opindex m8-bit
! Similar to the stack- data- and const-align options above, these options
! arrange for stack-frame, writable data and constants to all be 32-bit,
! 16-bit or 8-bit aligned. The default is 32-bit alignment.
! @item -mno-prologue-epilogue
! @itemx -mprologue-epilogue
! @opindex mno-prologue-epilogue
! @opindex mprologue-epilogue
! With @option{-mno-prologue-epilogue}, the normal function prologue and
! epilogue that sets up the stack-frame are omitted and no return
! instructions or return sequences are generated in the code. Use this
! option only together with visual inspection of the compiled code: no
! warnings or errors are generated when call-saved registers must be saved,
! or storage for local variable needs to be allocated.
! @item -mno-gotplt
! @itemx -mgotplt
! @opindex mno-gotplt
! @opindex mgotplt
! With @option{-fpic} and @option{-fPIC}, don't generate (do generate)
! instruction sequences that load addresses for functions from the PLT part
! of the GOT rather than (traditional on other architectures) calls to the
! PLT. The default is @option{-mgotplt}.
! @item -maout
! @opindex maout
! Legacy no-op option only recognized with the cris-axis-aout target.
! @item -melf
! @opindex melf
! Legacy no-op option only recognized with the cris-axis-elf and
! cris-axis-linux-gnu targets.
! @item -melinux
! @opindex melinux
! Only recognized with the cris-axis-aout target, where it selects a
! GNU/linux-like multilib, include files and instruction set for
! @option{-march=v8}.
! @item -mlinux
! @opindex mlinux
! Legacy no-op option only recognized with the cris-axis-linux-gnu target.
! @item -sim
! @opindex sim
! This option, recognized for the cris-axis-aout and cris-axis-elf arranges
! to link with input-output functions from a simulator library. Code,
! initialized data and zero-initialized data are allocated consecutively.
! @item -sim2
! @opindex sim2
! Like @option{-sim}, but pass linker options to locate initialized data at
! 0x40000000 and zero-initialized data at 0x80000000.
! @end table
! @node Darwin Options
! @subsection Darwin Options
! @cindex Darwin options
! These options are defined for all architectures running the Darwin operating
! system. They are useful for compatibility with other Mac OS compilers.
! @table @gcctabopt
! @item -F@var{dir}
! @opindex F
! Add the framework directory @var{dir} to the head of the list of
! directories to be searched for header files. These directories are
! interleaved with those specified by @option{-I} options and are
! scanned in a left-to-right order.
! A framework directory is a directory with frameworks in it. A
! framework is a directory with a @samp{"Headers"} and/or
! @samp{"PrivateHeaders"} directory contained directly in it that ends
! in @samp{".framework"}. The name of a framework is the name of this
! directory excluding the @samp{".framework"}. Headers associated with
! the framework are found in one of those two directories, with
! @samp{"Headers"} being searched first. A subframework is a framework
! directory that is in a framework's @samp{"Frameworks"} directory.
! Includes of subframework headers can only appear in a header of a
! framework that contains the subframework, or in a sibling subframework
! header. Two subframeworks are siblings if they occur in the same
! framework. A subframework should not have the same name as a
! framework, a warning will be issued if this is violated. Currently a
! subframework cannot have subframeworks, in the future, the mechanism
! may be extended to support this. The standard frameworks can be found
! in @samp{"/System/Library/Frameworks"}, @samp{"/Library/Frameworks"}
! and @samp{"/Local/Library/Frameworks"}. An example include looks like
! @code{#include <Framework/header.h>}, where @samp{Framework} denotes
! the name of the framework and header.h is found in the
! @samp{"PrivateHeaders"} or @samp{"Headers"} directory.
!
! @item -all_load
! @opindex all_load
! Loads all members of static archive libraries.
! See man ld(1) for more information.
!
! @item -arch_errors_fatal
! @opindex arch_errors_fatal
! Cause the errors having to do with files that have the wrong architecture
! to be fatal.
!
! @item -bind_at_load
! @opindex bind_at_load
! Causes the output file to be marked such that the dynamic linker will
! bind all undefined references when the file is loaded or launched.
!
! @item -bundle
! @opindex bundle
! Produce a Mach-o bundle format file.
! See man ld(1) for more information.
!
! @item -bundle_loader @var{executable}
! @opindex bundle_loader
! This specifies the @var{executable} that will be loading the build
! output file being linked. See man ld(1) for more information.
!
! @item -allowable_client @var{client_name}
! @itemx -arch_only
!
! @itemx -client_name
! @itemx -compatibility_version
! @itemx -current_version
! @itemx -dependency-file
! @itemx -dylib_file
! @itemx -dylinker_install_name
! @itemx -dynamic
! @itemx -dynamiclib
! @itemx -exported_symbols_list
! @itemx -filelist
! @itemx -flat_namespace
! @itemx -force_cpusubtype_ALL
! @itemx -force_flat_namespace
! @itemx -headerpad_max_install_names
! @itemx -image_base
! @itemx -init
! @itemx -install_name
! @itemx -keep_private_externs
! @itemx -multi_module
! @itemx -multiply_defined
! @itemx -multiply_defined_unused
! @itemx -noall_load
! @itemx -nofixprebinding
! @itemx -nomultidefs
! @itemx -noprebind
! @itemx -noseglinkedit
! @itemx -pagezero_size
! @itemx -prebind
! @itemx -prebind_all_twolevel_modules
! @itemx -private_bundle
! @itemx -read_only_relocs
! @itemx -sectalign
! @itemx -sectobjectsymbols
! @itemx -whyload
! @itemx -seg1addr
! @itemx -sectcreate
! @itemx -sectobjectsymbols
! @itemx -sectorder
! @itemx -seg_addr_table
! @itemx -seg_addr_table_filename
! @itemx -seglinkedit
! @itemx -segprot
! @itemx -segs_read_only_addr
! @itemx -segs_read_write_addr
! @itemx -single_module
! @itemx -static
! @itemx -sub_library
! @itemx -sub_umbrella
! @itemx -twolevel_namespace
! @itemx -umbrella
! @itemx -undefined
! @itemx -unexported_symbols_list
! @itemx -weak_reference_mismatches
! @itemx -whatsloaded
!
! @opindex allowable_client
! @opindex arch_only
! @opindex client_name
! @opindex compatibility_version
! @opindex current_version
! @opindex dependency-file
! @opindex dylib_file
! @opindex dylinker_install_name
! @opindex dynamic
! @opindex dynamiclib
! @opindex exported_symbols_list
! @opindex filelist
! @opindex flat_namespace
! @opindex force_cpusubtype_ALL
! @opindex force_flat_namespace
! @opindex headerpad_max_install_names
! @opindex image_base
! @opindex init
! @opindex install_name
! @opindex keep_private_externs
! @opindex multi_module
! @opindex multiply_defined
! @opindex multiply_defined_unused
! @opindex noall_load
! @opindex nofixprebinding
! @opindex nomultidefs
! @opindex noprebind
! @opindex noseglinkedit
! @opindex pagezero_size
! @opindex prebind
! @opindex prebind_all_twolevel_modules
! @opindex private_bundle
! @opindex read_only_relocs
! @opindex sectalign
! @opindex sectobjectsymbols
! @opindex whyload
! @opindex seg1addr
! @opindex sectcreate
! @opindex sectobjectsymbols
! @opindex sectorder
! @opindex seg_addr_table
! @opindex seg_addr_table_filename
! @opindex seglinkedit
! @opindex segprot
! @opindex segs_read_only_addr
! @opindex segs_read_write_addr
! @opindex single_module
! @opindex static
! @opindex sub_library
! @opindex sub_umbrella
! @opindex twolevel_namespace
! @opindex umbrella
! @opindex undefined
! @opindex unexported_symbols_list
! @opindex weak_reference_mismatches
! @opindex whatsloaded
!
! These options are available for Darwin linker. Darwin linker man page
! describes them in detail.
! @end table
!
! @node DEC Alpha Options
! @subsection DEC Alpha Options
!
! These @samp{-m} options are defined for the DEC Alpha implementations:
!
! @table @gcctabopt
! @item -mno-soft-float
! @itemx -msoft-float
! @opindex mno-soft-float
@opindex msoft-float
! Use (do not use) the hardware floating-point instructions for
! floating-point operations. When @option{-msoft-float} is specified,
! functions in @file{libgcc.a} will be used to perform floating-point
! operations. Unless they are replaced by routines that emulate the
! floating-point operations, or compiled in such a way as to call such
! emulations routines, these routines will issue floating-point
! operations. If you are compiling for an Alpha without floating-point
! operations, you must ensure that the library is built so as not to call
! them.
! Note that Alpha implementations without floating-point operations are
! required to have floating-point registers.
! @item -mfp-reg
! @itemx -mno-fp-regs
! @opindex mfp-reg
! @opindex mno-fp-regs
! Generate code that uses (does not use) the floating-point register set.
! @option{-mno-fp-regs} implies @option{-msoft-float}. If the floating-point
! register set is not used, floating point operands are passed in integer
! registers as if they were integers and floating-point results are passed
! in @code{$0} instead of @code{$f0}. This is a non-standard calling sequence,
! so any function with a floating-point argument or return value called by code
! compiled with @option{-mno-fp-regs} must also be compiled with that
! option.
! A typical use of this option is building a kernel that does not use,
! and hence need not save and restore, any floating-point registers.
! @item -mieee
! @opindex mieee
! The Alpha architecture implements floating-point hardware optimized for
! maximum performance. It is mostly compliant with the IEEE floating
! point standard. However, for full compliance, software assistance is
! required. This option generates code fully IEEE compliant code
! @emph{except} that the @var{inexact-flag} is not maintained (see below).
! If this option is turned on, the preprocessor macro @code{_IEEE_FP} is
! defined during compilation. The resulting code is less efficient but is
! able to correctly support denormalized numbers and exceptional IEEE
! values such as not-a-number and plus/minus infinity. Other Alpha
! compilers call this option @option{-ieee_with_no_inexact}.
! @item -mieee-with-inexact
! @opindex mieee-with-inexact
! This is like @option{-mieee} except the generated code also maintains
! the IEEE @var{inexact-flag}. Turning on this option causes the
! generated code to implement fully-compliant IEEE math. In addition to
! @code{_IEEE_FP}, @code{_IEEE_FP_EXACT} is defined as a preprocessor
! macro. On some Alpha implementations the resulting code may execute
! significantly slower than the code generated by default. Since there is
! very little code that depends on the @var{inexact-flag}, you should
! normally not specify this option. Other Alpha compilers call this
! option @option{-ieee_with_inexact}.
! @item -mfp-trap-mode=@var{trap-mode}
! @opindex mfp-trap-mode
! This option controls what floating-point related traps are enabled.
! Other Alpha compilers call this option @option{-fptm @var{trap-mode}}.
! The trap mode can be set to one of four values:
! @table @samp
! @item n
! This is the default (normal) setting. The only traps that are enabled
! are the ones that cannot be disabled in software (e.g., division by zero
! trap).
! @item u
! In addition to the traps enabled by @samp{n}, underflow traps are enabled
! as well.
! @item su
! Like @samp{su}, but the instructions are marked to be safe for software
! completion (see Alpha architecture manual for details).
! @item sui
! Like @samp{su}, but inexact traps are enabled as well.
! @end table
! @item -mfp-rounding-mode=@var{rounding-mode}
! @opindex mfp-rounding-mode
! Selects the IEEE rounding mode. Other Alpha compilers call this option
! @option{-fprm @var{rounding-mode}}. The @var{rounding-mode} can be one
! of:
! @table @samp
! @item n
! Normal IEEE rounding mode. Floating point numbers are rounded towards
! the nearest machine number or towards the even machine number in case
! of a tie.
! @item m
! Round towards minus infinity.
! @item c
! Chopped rounding mode. Floating point numbers are rounded towards zero.
! @item d
! Dynamic rounding mode. A field in the floating point control register
! (@var{fpcr}, see Alpha architecture reference manual) controls the
! rounding mode in effect. The C library initializes this register for
! rounding towards plus infinity. Thus, unless your program modifies the
! @var{fpcr}, @samp{d} corresponds to round towards plus infinity.
! @end table
! @item -mtrap-precision=@var{trap-precision}
! @opindex mtrap-precision
! In the Alpha architecture, floating point traps are imprecise. This
! means without software assistance it is impossible to recover from a
! floating trap and program execution normally needs to be terminated.
! GCC can generate code that can assist operating system trap handlers
! in determining the exact location that caused a floating point trap.
! Depending on the requirements of an application, different levels of
! precisions can be selected:
! @table @samp
! @item p
! Program precision. This option is the default and means a trap handler
! can only identify which program caused a floating point exception.
! @item f
! Function precision. The trap handler can determine the function that
! caused a floating point exception.
! @item i
! Instruction precision. The trap handler can determine the exact
! instruction that caused a floating point exception.
! @end table
! Other Alpha compilers provide the equivalent options called
! @option{-scope_safe} and @option{-resumption_safe}.
! @item -mieee-conformant
! @opindex mieee-conformant
! This option marks the generated code as IEEE conformant. You must not
! use this option unless you also specify @option{-mtrap-precision=i} and either
! @option{-mfp-trap-mode=su} or @option{-mfp-trap-mode=sui}. Its only effect
! is to emit the line @samp{.eflag 48} in the function prologue of the
! generated assembly file. Under DEC Unix, this has the effect that
! IEEE-conformant math library routines will be linked in.
! @item -mbuild-constants
! @opindex mbuild-constants
! Normally GCC examines a 32- or 64-bit integer constant to
! see if it can construct it from smaller constants in two or three
! instructions. If it cannot, it will output the constant as a literal and
! generate code to load it from the data segment at runtime.
! Use this option to require GCC to construct @emph{all} integer constants
! using code, even if it takes more instructions (the maximum is six).
! You would typically use this option to build a shared library dynamic
! loader. Itself a shared library, it must relocate itself in memory
! before it can find the variables and constants in its own data segment.
!
! @item -malpha-as
! @itemx -mgas
! @opindex malpha-as
! @opindex mgas
! Select whether to generate code to be assembled by the vendor-supplied
! assembler (@option{-malpha-as}) or by the GNU assembler @option{-mgas}.
!
! @item -mbwx
! @itemx -mno-bwx
! @itemx -mcix
! @itemx -mno-cix
! @itemx -mfix
! @itemx -mno-fix
! @itemx -mmax
! @itemx -mno-max
! @opindex mbwx
! @opindex mno-bwx
! @opindex mcix
! @opindex mno-cix
! @opindex mfix
! @opindex mno-fix
! @opindex mmax
! @opindex mno-max
! Indicate whether GCC should generate code to use the optional BWX,
! CIX, FIX and MAX instruction sets. The default is to use the instruction
! sets supported by the CPU type specified via @option{-mcpu=} option or that
! of the CPU on which GCC was built if none was specified.
! @item -mfloat-vax
! @itemx -mfloat-ieee
! @opindex mfloat-vax
! @opindex mfloat-ieee
! Generate code that uses (does not use) VAX F and G floating point
! arithmetic instead of IEEE single and double precision.
! @item -mexplicit-relocs
! @itemx -mno-explicit-relocs
! @opindex mexplicit-relocs
! @opindex mno-explicit-relocs
! Older Alpha assemblers provided no way to generate symbol relocations
! except via assembler macros. Use of these macros does not allow
! optimal instruction scheduling. GNU binutils as of version 2.12
! supports a new syntax that allows the compiler to explicitly mark
! which relocations should apply to which instructions. This option
! is mostly useful for debugging, as GCC detects the capabilities of
! the assembler when it is built and sets the default accordingly.
! @item -msmall-data
! @itemx -mlarge-data
! @opindex msmall-data
! @opindex mlarge-data
! When @option{-mexplicit-relocs} is in effect, static data is
! accessed via @dfn{gp-relative} relocations. When @option{-msmall-data}
! is used, objects 8 bytes long or smaller are placed in a @dfn{small data area}
! (the @code{.sdata} and @code{.sbss} sections) and are accessed via
! 16-bit relocations off of the @code{$gp} register. This limits the
! size of the small data area to 64KB, but allows the variables to be
! directly accessed via a single instruction.
! The default is @option{-mlarge-data}. With this option the data area
! is limited to just below 2GB. Programs that require more than 2GB of
! data must use @code{malloc} or @code{mmap} to allocate the data in the
! heap instead of in the program's data segment.
! When generating code for shared libraries, @option{-fpic} implies
! @option{-msmall-data} and @option{-fPIC} implies @option{-mlarge-data}.
! @item -msmall-text
! @itemx -mlarge-text
! @opindex msmall-text
! @opindex mlarge-text
! When @option{-msmall-text} is used, the compiler assumes that the
! code of the entire program (or shared library) fits in 4MB, and is
! thus reachable with a branch instruction. When @option{-msmall-data}
! is used, the compiler can assume that all local symbols share the
! same @code{$gp} value, and thus reduce the number of instructions
! required for a function call from 4 to 1.
! The default is @option{-mlarge-text}.
! @item -mcpu=@var{cpu_type}
! @opindex mcpu
! Set the instruction set and instruction scheduling parameters for
! machine type @var{cpu_type}. You can specify either the @samp{EV}
! style name or the corresponding chip number. GCC supports scheduling
! parameters for the EV4, EV5 and EV6 family of processors and will
! choose the default values for the instruction set from the processor
! you specify. If you do not specify a processor type, GCC will default
! to the processor on which the compiler was built.
! Supported values for @var{cpu_type} are
! @table @samp
! @item ev4
! @itemx ev45
! @itemx 21064
! Schedules as an EV4 and has no instruction set extensions.
! @item ev5
! @itemx 21164
! Schedules as an EV5 and has no instruction set extensions.
! @item ev56
! @itemx 21164a
! Schedules as an EV5 and supports the BWX extension.
! @item pca56
! @itemx 21164pc
! @itemx 21164PC
! Schedules as an EV5 and supports the BWX and MAX extensions.
! @item ev6
! @itemx 21264
! Schedules as an EV6 and supports the BWX, FIX, and MAX extensions.
! @item ev67
! @itemx 21264a
! Schedules as an EV6 and supports the BWX, CIX, FIX, and MAX extensions.
@end table
+ @item -mtune=@var{cpu_type}
+ @opindex mtune
+ Set only the instruction scheduling parameters for machine type
+ @var{cpu_type}. The instruction set is not changed.
! @item -mmemory-latency=@var{time}
! @opindex mmemory-latency
! Sets the latency the scheduler should assume for typical memory
! references as seen by the application. This number is highly
! dependent on the memory access patterns used by the application
! and the size of the external cache on the machine.
! Valid options for @var{time} are
! @table @samp
! @item @var{number}
! A decimal number representing clock cycles.
! @item L1
! @itemx L2
! @itemx L3
! @itemx main
! The compiler contains estimates of the number of clock cycles for
! ``typical'' EV4 & EV5 hardware for the Level 1, 2 & 3 caches
! (also called Dcache, Scache, and Bcache), as well as to main memory.
! Note that L3 is only valid for EV5.
! @end table
! @end table
! @node DEC Alpha/VMS Options
! @subsection DEC Alpha/VMS Options
! These @samp{-m} options are defined for the DEC Alpha/VMS implementations:
! @table @gcctabopt
! @item -mvms-return-codes
! @opindex mvms-return-codes
! Return VMS condition codes from main. The default is to return POSIX
! style condition (e.g.@ error) codes.
! @end table
! @node FRV Options
! @subsection FRV Options
! @cindex FRV Options
! @table @gcctabopt
! @item -mgpr-32
! @opindex mgpr-32
! Only use the first 32 general purpose registers.
! @item -mgpr-64
! @opindex mgpr-64
! Use all 64 general purpose registers.
! @item -mfpr-32
! @opindex mfpr-32
! Use only the first 32 floating point registers.
! @item -mfpr-64
! @opindex mfpr-64
! Use all 64 floating point registers
!
! @item -mhard-float
! @opindex mhard-float
! Use hardware instructions for floating point operations.
! @item -msoft-float
! @opindex msoft-float
! Use library routines for floating point operations.
! @item -malloc-cc
! @opindex malloc-cc
! Dynamically allocate condition code registers.
! @item -mfixed-cc
! @opindex mfixed-cc
! Do not try to dynamically allocate condition code registers, only
! use @code{icc0} and @code{fcc0}.
! @item -mdword
! @opindex mdword
! Change ABI to use double word insns.
! @item -mno-dword
! @opindex mno-dword
! Do not use double word instructions.
! @item -mdouble
! @opindex mdouble
! Use floating point double instructions.
! @item -mno-double
! @opindex mno-double
! Do not use floating point double instructions.
! @item -mmedia
! @opindex mmedia
! Use media instructions.
! @item -mno-media
! @opindex mno-media
! Do not use media instructions.
! @item -mmuladd
! @opindex mmuladd
! Use multiply and add/subtract instructions.
! @item -mno-muladd
! @opindex mno-muladd
! Do not use multiply and add/subtract instructions.
! @item -mlibrary-pic
! @opindex mlibrary-pic
! Generate position-independent EABI code.
! @item -macc-4
! @opindex macc-4
! Use only the first four media accumulator registers.
! @item -macc-8
! @opindex macc-8
! Use all eight media accumulator registers.
! @item -mpack
! @opindex mpack
! Pack VLIW instructions.
! @item -mno-pack
! @opindex mno-pack
! Do not pack VLIW instructions.
! @item -mno-eflags
! @opindex mno-eflags
! Do not mark ABI switches in e_flags.
! @item -mcond-move
! @opindex mcond-move
! Enable the use of conditional-move instructions (default).
! This switch is mainly for debugging the compiler and will likely be removed
! in a future version.
! @item -mno-cond-move
! @opindex mno-cond-move
! Disable the use of conditional-move instructions.
! This switch is mainly for debugging the compiler and will likely be removed
! in a future version.
! @item -mscc
! @opindex mscc
! Enable the use of conditional set instructions (default).
! This switch is mainly for debugging the compiler and will likely be removed
! in a future version.
! @item -mno-scc
! @opindex mno-scc
! Disable the use of conditional set instructions.
! This switch is mainly for debugging the compiler and will likely be removed
! in a future version.
! @item -mcond-exec
! @opindex mcond-exec
! Enable the use of conditional execution (default).
! This switch is mainly for debugging the compiler and will likely be removed
! in a future version.
! @item -mno-cond-exec
! @opindex mno-cond-exec
! Disable the use of conditional execution.
! This switch is mainly for debugging the compiler and will likely be removed
! in a future version.
! @item -mvliw-branch
! @opindex mvliw-branch
! Run a pass to pack branches into VLIW instructions (default).
! This switch is mainly for debugging the compiler and will likely be removed
! in a future version.
!
! @item -mno-vliw-branch
! @opindex mno-vliw-branch
!
! Do not run a pass to pack branches into VLIW instructions.
!
! This switch is mainly for debugging the compiler and will likely be removed
! in a future version.
!
! @item -mmulti-cond-exec
! @opindex mmulti-cond-exec
!
! Enable optimization of @code{&&} and @code{||} in conditional execution
! (default).
! This switch is mainly for debugging the compiler and will likely be removed
! in a future version.
! @item -mno-multi-cond-exec
! @opindex mno-multi-cond-exec
! Disable optimization of @code{&&} and @code{||} in conditional execution.
! This switch is mainly for debugging the compiler and will likely be removed
! in a future version.
! @item -mnested-cond-exec
! @opindex mnested-cond-exec
! Enable nested conditional execution optimizations (default).
! This switch is mainly for debugging the compiler and will likely be removed
! in a future version.
! @item -mno-nested-cond-exec
! @opindex mno-nested-cond-exec
! Disable nested conditional execution optimizations.
! This switch is mainly for debugging the compiler and will likely be removed
! in a future version.
! @item -mtomcat-stats
! @opindex mtomcat-stats
! Cause gas to print out tomcat statistics.
! @item -mcpu=@var{cpu}
! @opindex mcpu
! Select the processor type for which to generate code. Possible values are
! @samp{simple}, @samp{tomcat}, @samp{fr500}, @samp{fr400}, @samp{fr300},
! @samp{frv}.
! @end table
! @node H8/300 Options
! @subsection H8/300 Options
! These @samp{-m} options are defined for the H8/300 implementations:
! @table @gcctabopt
! @item -mrelax
! @opindex mrelax
! Shorten some address references at link time, when possible; uses the
! linker option @option{-relax}. @xref{H8/300,, @code{ld} and the H8/300,
! ld, Using ld}, for a fuller description.
! @item -mh
! @opindex mh
! Generate code for the H8/300H@.
! @item -ms
! @opindex ms
! Generate code for the H8S@.
! @item -mn
! @opindex mn
! Generate code for the H8S and H8/300H in the normal mode. This switch
! must be used either with -mh or -ms.
! @item -ms2600
! @opindex ms2600
! Generate code for the H8S/2600. This switch must be used with @option{-ms}.
! @item -mint32
! @opindex mint32
! Make @code{int} data 32 bits by default.
! @item -malign-300
! @opindex malign-300
! On the H8/300H and H8S, use the same alignment rules as for the H8/300.
! The default for the H8/300H and H8S is to align longs and floats on 4
! byte boundaries.
! @option{-malign-300} causes them to be aligned on 2 byte boundaries.
! This option has no effect on the H8/300.
! @end table
! @node HPPA Options
! @subsection HPPA Options
! @cindex HPPA Options
! These @samp{-m} options are defined for the HPPA family of computers:
! @table @gcctabopt
! @item -march=@var{architecture-type}
! @opindex march
! Generate code for the specified architecture. The choices for
! @var{architecture-type} are @samp{1.0} for PA 1.0, @samp{1.1} for PA
! 1.1, and @samp{2.0} for PA 2.0 processors. Refer to
! @file{/usr/lib/sched.models} on an HP-UX system to determine the proper
! architecture option for your machine. Code compiled for lower numbered
! architectures will run on higher numbered architectures, but not the
! other way around.
! PA 2.0 support currently requires gas snapshot 19990413 or later. The
! next release of binutils (current is 2.9.1) will probably contain PA 2.0
! support.
! @item -mpa-risc-1-0
! @itemx -mpa-risc-1-1
! @itemx -mpa-risc-2-0
! @opindex mpa-risc-1-0
! @opindex mpa-risc-1-1
! @opindex mpa-risc-2-0
! Synonyms for @option{-march=1.0}, @option{-march=1.1}, and @option{-march=2.0} respectively.
! @item -mbig-switch
! @opindex mbig-switch
! Generate code suitable for big switch tables. Use this option only if
! the assembler/linker complain about out of range branches within a switch
! table.
! @item -mjump-in-delay
! @opindex mjump-in-delay
! Fill delay slots of function calls with unconditional jump instructions
! by modifying the return pointer for the function call to be the target
! of the conditional jump.
! @item -mdisable-fpregs
! @opindex mdisable-fpregs
! Prevent floating point registers from being used in any manner. This is
! necessary for compiling kernels which perform lazy context switching of
! floating point registers. If you use this option and attempt to perform
! floating point operations, the compiler will abort.
! @item -mdisable-indexing
! @opindex mdisable-indexing
! Prevent the compiler from using indexing address modes. This avoids some
! rather obscure problems when compiling MIG generated code under MACH@.
! @item -mno-space-regs
! @opindex mno-space-regs
! Generate code that assumes the target has no space registers. This allows
! GCC to generate faster indirect calls and use unscaled index address modes.
! Such code is suitable for level 0 PA systems and kernels.
! @item -mfast-indirect-calls
! @opindex mfast-indirect-calls
! Generate code that assumes calls never cross space boundaries. This
! allows GCC to emit code which performs faster indirect calls.
! This option will not work in the presence of shared libraries or nested
! functions.
! @item -mlong-load-store
! @opindex mlong-load-store
! Generate 3-instruction load and store sequences as sometimes required by
! the HP-UX 10 linker. This is equivalent to the @samp{+k} option to
! the HP compilers.
! @item -mportable-runtime
! @opindex mportable-runtime
! Use the portable calling conventions proposed by HP for ELF systems.
! @item -mgas
! @opindex mgas
! Enable the use of assembler directives only GAS understands.
! @item -mschedule=@var{cpu-type}
! @opindex mschedule
! Schedule code according to the constraints for the machine type
! @var{cpu-type}. The choices for @var{cpu-type} are @samp{700}
! @samp{7100}, @samp{7100LC}, @samp{7200}, @samp{7300} and @samp{8000}. Refer
! to @file{/usr/lib/sched.models} on an HP-UX system to determine the
! proper scheduling option for your machine. The default scheduling is
! @samp{8000}.
! @item -mlinker-opt
! @opindex mlinker-opt
! Enable the optimization pass in the HP-UX linker. Note this makes symbolic
! debugging impossible. It also triggers a bug in the HP-UX 8 and HP-UX 9
! linkers in which they give bogus error messages when linking some programs.
! @item -msoft-float
! @opindex msoft-float
! Generate output containing library calls for floating point.
! @strong{Warning:} the requisite libraries are not available for all HPPA
! targets. Normally the facilities of the machine's usual C compiler are
! used, but this cannot be done directly in cross-compilation. You must make
! your own arrangements to provide suitable library functions for
! cross-compilation. The embedded target @samp{hppa1.1-*-pro}
! does provide software floating point support.
! @option{-msoft-float} changes the calling convention in the output file;
! therefore, it is only useful if you compile @emph{all} of a program with
! this option. In particular, you need to compile @file{libgcc.a}, the
! library that comes with GCC, with @option{-msoft-float} in order for
! this to work.
! @item -msio
! @opindex msio
! Generate the predefine, @code{_SIO}, for server IO. The default is
! @option{-mwsio}. This generates the predefines, @code{__hp9000s700},
! @code{__hp9000s700__} and @code{_WSIO}, for workstation IO. These
! options are available under HP-UX and HI-UX.
!
! @item -mgnu-ld
! @opindex gnu-ld
! Use GNU ld specific options. This passes @option{-shared} to ld when
! building a shared library. It is the default when GCC is configured,
! explicitly or implicitly, with the GNU linker. This option does not
! have any affect on which ld is called, it only changes what parameters
! are passed to that ld. The ld that is called is determined by the
! @option{--with-ld} configure option, GCC's program search path, and
! finally by the user's @env{PATH}. The linker used by GCC can be printed
! using @samp{which `gcc -print-prog-name=ld`}.
! @item -mhp-ld
! @opindex hp-ld
! Use HP ld specific options. This passes @option{-b} to ld when building
! a shared library and passes @option{+Accept TypeMismatch} to ld on all
! links. It is the default when GCC is configured, explicitly or
! implicitly, with the HP linker. This option does not have any affect on
! which ld is called, it only changes what parameters are passed to that
! ld. The ld that is called is determined by the @option{--with-ld}
! configure option, GCC's program search path, and finally by the user's
! @env{PATH}. The linker used by GCC can be printed using @samp{which
! `gcc -print-prog-name=ld`}.
+ @item -mfdpic
+ @opindex mfdpic
! Select the FDPIC ABI, that uses function descriptors to represent
! pointers to functions. Without any PIC/PIE-related options, it
! implies @option{-fPIE}. With @option{-fpic} or @option{-fpie}, it
! assumes GOT entries and small data are within a 12-bit range from the
! GOT base address; with @option{-fPIC} or @option{-fPIE}, GOT offsets
! are computed with 32 bits.
! @item -minline-plt
! @opindex minline-plt
! Enable inlining of PLT entries in function calls to functions that are
! not known to bind locally. It has no effect without @option{-mfdpic}.
! It's enabled by default if optimizing for speed and compiling for
! shared libraries (i.e., @option{-fPIC} or @option{-fpic}), or when an
! optimization option such as @option{-O3} or above is present in the
! command line.
! @item -mgprel-ro
! @opindex mgprel-ro
! Enable the use of @code{GPREL} relocations in the FDPIC ABI for data
! that is known to be in read-only sections. It's enabled by default,
! except for @option{-fpic} or @option{-fpie}: even though it may help
! make the global offset table smaller, it trades 1 instruction for 4.
! With @option{-fPIC} or @option{-fPIE}, it trades 3 instructions for 4,
! one of which may be shared by multiple symbols, and it avoids the need
! for a GOT entry for the referenced symbol, so it's more likely to be a
! win. If it is not, @option{-mno-gprel-ro} can be used to disable it.
! @item -multilib-library-pic
! @opindex multilib-library-pic
! Link with the (library, not FD) pic libraries. It's implied by
! @option{-mlibrary-pic}, as well as by @option{-fPIC} and
! @option{-fpic} without @option{-mfdpic}. You should never have to use
! it explicitly.
! @item -mlinked-fp
! @opindex mlinked-fp
! Follow the EABI requirement of always creating a frame pointer whenever
! a stack frame is allocated. This option is enabled by default and can
! be disabled with @option{-mno-linked-fp}.
! @item -mlong-calls
! @opindex mno-long-calls
! Generate code that uses long call sequences. This ensures that a call
! is always able to reach linker generated stubs. The default is to generate
! long calls only when the distance from the call site to the beginning
! of the function or translation unit, as the case may be, exceeds a
! predefined limit set by the branch type being used. The limits for
! normal calls are 7,600,000 and 240,000 bytes, respectively for the
! PA 2.0 and PA 1.X architectures. Sibcalls are always limited at
! 240,000 bytes.
! Distances are measured from the beginning of functions when using the
! @option{-ffunction-sections} option, or when using the @option{-mgas}
! and @option{-mno-portable-runtime} options together under HP-UX with
! the SOM linker.
! It is normally not desirable to use this option as it will degrade
! performance. However, it may be useful in large applications,
! particularly when partial linking is used to build the application.
! The types of long calls used depends on the capabilities of the
! assembler and linker, and the type of code being generated. The
! impact on systems that support long absolute calls, and long pic
! symbol-difference or pc-relative calls should be relatively small.
! However, an indirect call is used on 32-bit ELF systems in pic code
! and it is quite long.
! @item -nolibdld
! @opindex nolibdld
! Suppress the generation of link options to search libdld.sl when the
! @option{-static} option is specified on HP-UX 10 and later.
!
! @item -static
! @opindex static
! The HP-UX implementation of setlocale in libc has a dependency on
! libdld.sl. There isn't an archive version of libdld.sl. Thus,
! when the @option{-static} option is specified, special link options
! are needed to resolve this dependency.
!
! On HP-UX 10 and later, the GCC driver adds the necessary options to
! link with libdld.sl when the @option{-static} option is specified.
! This causes the resulting binary to be dynamic. On the 64-bit port,
! the linkers generate dynamic binaries by default in any case. The
! @option{-nolibdld} option can be used to prevent the GCC driver from
! adding these link options.
!
! @item -threads
! @opindex threads
! Add support for multithreading with the @dfn{dce thread} library
! under HP-UX. This option sets flags for both the preprocessor and
! linker.
! @end table
!
! @node i386 and x86-64 Options
! @subsection Intel 386 and AMD x86-64 Options
! @cindex i386 Options
! @cindex x86-64 Options
! @cindex Intel 386 Options
! @cindex AMD x86-64 Options
!
! These @samp{-m} options are defined for the i386 and x86-64 family of
! computers:
!
! @table @gcctabopt
! @item -mtune=@var{cpu-type}
! @opindex mtune
! Tune to @var{cpu-type} everything applicable about the generated code, except
! for the ABI and the set of available instructions. The choices for
! @var{cpu-type} are:
! @table @emph
! @item i386
! Original Intel's i386 CPU.
! @item i486
! Intel's i486 CPU. (No scheduling is implemented for this chip.)
! @item i586, pentium
! Intel Pentium CPU with no MMX support.
! @item pentium-mmx
! Intel PentiumMMX CPU based on Pentium core with MMX instruction set support.
! @item i686, pentiumpro
! Intel PentiumPro CPU.
! @item pentium2
! Intel Pentium2 CPU based on PentiumPro core with MMX instruction set support.
! @item pentium3, pentium3m
! Intel Pentium3 CPU based on PentiumPro core with MMX and SSE instruction set
! support.
! @item pentium-m
! Low power version of Intel Pentium3 CPU with MMX, SSE and SSE2 instruction set
! support. Used by Centrino notebooks.
! @item pentium4, pentium4m
! Intel Pentium4 CPU with MMX, SSE and SSE2 instruction set support.
! @item prescott
! Improved version of Intel Pentium4 CPU with MMX, SSE, SSE2 and SSE3 instruction
! set support.
! @item nocona
! Improved version of Intel Pentium4 CPU with 64-bit extensions, MMX, SSE,
! SSE2 and SSE3 instruction set support.
! @item k6
! AMD K6 CPU with MMX instruction set support.
! @item k6-2, k6-3
! Improved versions of AMD K6 CPU with MMX and 3dNOW! instruction set support.
! @item athlon, athlon-tbird
! AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW! and SSE prefetch instructions
! support.
! @item athlon-4, athlon-xp, athlon-mp
! Improved AMD Athlon CPU with MMX, 3dNOW!, enhanced 3dNOW! and full SSE
! instruction set support.
! @item k8, opteron, athlon64, athlon-fx
! AMD K8 core based CPUs with x86-64 instruction set support. (This supersets
! MMX, SSE, SSE2, 3dNOW!, enhanced 3dNOW! and 64-bit instruction set extensions.)
! @item winchip-c6
! IDT Winchip C6 CPU, dealt in same way as i486 with additional MMX instruction
! set support.
! @item winchip2
! IDT Winchip2 CPU, dealt in same way as i486 with additional MMX and 3dNOW!
! instruction set support.
! @item c3
! Via C3 CPU with MMX and 3dNOW! instruction set support. (No scheduling is
! implemented for this chip.)
! @item c3-2
! Via C3-2 CPU with MMX and SSE instruction set support. (No scheduling is
! implemented for this chip.)
! @end table
!
! While picking a specific @var{cpu-type} will schedule things appropriately
! for that particular chip, the compiler will not generate any code that
! does not run on the i386 without the @option{-march=@var{cpu-type}} option
! being used.
!
! @item -march=@var{cpu-type}
! @opindex march
! Generate instructions for the machine type @var{cpu-type}. The choices
! for @var{cpu-type} are the same as for @option{-mtune}. Moreover,
! specifying @option{-march=@var{cpu-type}} implies @option{-mtune=@var{cpu-type}}.
! @item -mcpu=@var{cpu-type}
! @opindex mcpu
! A deprecated synonym for @option{-mtune}.
! @item -m386
! @itemx -m486
! @itemx -mpentium
! @itemx -mpentiumpro
! @opindex m386
! @opindex m486
! @opindex mpentium
! @opindex mpentiumpro
! These options are synonyms for @option{-mtune=i386}, @option{-mtune=i486},
! @option{-mtune=pentium}, and @option{-mtune=pentiumpro} respectively.
! These synonyms are deprecated.
! @item -mfpmath=@var{unit}
! @opindex march
! Generate floating point arithmetics for selected unit @var{unit}. The choices
! for @var{unit} are:
! @table @samp
! @item 387
! Use the standard 387 floating point coprocessor present majority of chips and
! emulated otherwise. Code compiled with this option will run almost everywhere.
! The temporary results are computed in 80bit precision instead of precision
! specified by the type resulting in slightly different results compared to most
! of other chips. See @option{-ffloat-store} for more detailed description.
! This is the default choice for i386 compiler.
! @item sse
! Use scalar floating point instructions present in the SSE instruction set.
! This instruction set is supported by Pentium3 and newer chips, in the AMD line
! by Athlon-4, Athlon-xp and Athlon-mp chips. The earlier version of SSE
! instruction set supports only single precision arithmetics, thus the double and
! extended precision arithmetics is still done using 387. Later version, present
! only in Pentium4 and the future AMD x86-64 chips supports double precision
! arithmetics too.
! For i387 you need to use @option{-march=@var{cpu-type}}, @option{-msse} or
! @option{-msse2} switches to enable SSE extensions and make this option
! effective. For x86-64 compiler, these extensions are enabled by default.
! The resulting code should be considerably faster in the majority of cases and avoid
! the numerical instability problems of 387 code, but may break some existing
! code that expects temporaries to be 80bit.
! This is the default choice for the x86-64 compiler.
! @item sse,387
! Attempt to utilize both instruction sets at once. This effectively double the
! amount of available registers and on chips with separate execution units for
! 387 and SSE the execution resources too. Use this option with care, as it is
! still experimental, because the GCC register allocator does not model separate
! functional units well resulting in instable performance.
! @end table
! @item -masm=@var{dialect}
! @opindex masm=@var{dialect}
! Output asm instructions using selected @var{dialect}. Supported choices are
! @samp{intel} or @samp{att} (the default one).
! @item -mieee-fp
! @itemx -mno-ieee-fp
! @opindex mieee-fp
! @opindex mno-ieee-fp
! Control whether or not the compiler uses IEEE floating point
! comparisons. These handle correctly the case where the result of a
! comparison is unordered.
! @item -msoft-float
! @opindex msoft-float
! Generate output containing library calls for floating point.
! @strong{Warning:} the requisite libraries are not part of GCC@.
! Normally the facilities of the machine's usual C compiler are used, but
! this can't be done directly in cross-compilation. You must make your
! own arrangements to provide suitable library functions for
! cross-compilation.
! On machines where a function returns floating point results in the 80387
! register stack, some floating point opcodes may be emitted even if
! @option{-msoft-float} is used.
! @item -mno-fp-ret-in-387
! @opindex mno-fp-ret-in-387
! Do not use the FPU registers for return values of functions.
! The usual calling convention has functions return values of types
! @code{float} and @code{double} in an FPU register, even if there
! is no FPU@. The idea is that the operating system should emulate
! an FPU@.
! The option @option{-mno-fp-ret-in-387} causes such values to be returned
! in ordinary CPU registers instead.
! @item -mno-fancy-math-387
! @opindex mno-fancy-math-387
! Some 387 emulators do not support the @code{sin}, @code{cos} and
! @code{sqrt} instructions for the 387. Specify this option to avoid
! generating those instructions. This option is the default on FreeBSD,
! OpenBSD and NetBSD@. This option is overridden when @option{-march}
! indicates that the target cpu will always have an FPU and so the
! instruction will not need emulation. As of revision 2.6.1, these
! instructions are not generated unless you also use the
! @option{-funsafe-math-optimizations} switch.
! @item -malign-double
! @itemx -mno-align-double
! @opindex malign-double
! @opindex mno-align-double
! Control whether GCC aligns @code{double}, @code{long double}, and
! @code{long long} variables on a two word boundary or a one word
! boundary. Aligning @code{double} variables on a two word boundary will
! produce code that runs somewhat faster on a @samp{Pentium} at the
! expense of more memory.
! @strong{Warning:} if you use the @option{-malign-double} switch,
! structures containing the above types will be aligned differently than
! the published application binary interface specifications for the 386
! and will not be binary compatible with structures in code compiled
! without that switch.
! @item -m96bit-long-double
! @itemx -m128bit-long-double
! @opindex m96bit-long-double
! @opindex m128bit-long-double
! These switches control the size of @code{long double} type. The i386
! application binary interface specifies the size to be 96 bits,
! so @option{-m96bit-long-double} is the default in 32 bit mode.
! Modern architectures (Pentium and newer) would prefer @code{long double}
! to be aligned to an 8 or 16 byte boundary. In arrays or structures
! conforming to the ABI, this would not be possible. So specifying a
! @option{-m128bit-long-double} will align @code{long double}
! to a 16 byte boundary by padding the @code{long double} with an additional
! 32 bit zero.
! In the x86-64 compiler, @option{-m128bit-long-double} is the default choice as
! its ABI specifies that @code{long double} is to be aligned on 16 byte boundary.
! Notice that neither of these options enable any extra precision over the x87
! standard of 80 bits for a @code{long double}.
! @strong{Warning:} if you override the default value for your target ABI, the
! structures and arrays containing @code{long double} variables will change
! their size as well as function calling convention for function taking
! @code{long double} will be modified. Hence they will not be binary
! compatible with arrays or structures in code compiled without that switch.
! @item -msvr3-shlib
! @itemx -mno-svr3-shlib
! @opindex msvr3-shlib
! @opindex mno-svr3-shlib
! Control whether GCC places uninitialized local variables into the
! @code{bss} or @code{data} segments. @option{-msvr3-shlib} places them
! into @code{bss}. These options are meaningful only on System V Release 3.
! @item -mrtd
! @opindex mrtd
! Use a different function-calling convention, in which functions that
! take a fixed number of arguments return with the @code{ret} @var{num}
! instruction, which pops their arguments while returning. This saves one
! instruction in the caller since there is no need to pop the arguments
! there.
!
! You can specify that an individual function is called with this calling
! sequence with the function attribute @samp{stdcall}. You can also
! override the @option{-mrtd} option by using the function attribute
! @samp{cdecl}. @xref{Function Attributes}.
! @strong{Warning:} this calling convention is incompatible with the one
! normally used on Unix, so you cannot use it if you need to call
! libraries compiled with the Unix compiler.
! Also, you must provide function prototypes for all functions that
! take variable numbers of arguments (including @code{printf});
! otherwise incorrect code will be generated for calls to those
! functions.
! In addition, seriously incorrect code will result if you call a
! function with too many arguments. (Normally, extra arguments are
! harmlessly ignored.)
! @item -mregparm=@var{num}
! @opindex mregparm
! Control how many registers are used to pass integer arguments. By
! default, no registers are used to pass arguments, and at most 3
! registers can be used. You can control this behavior for a specific
! function by using the function attribute @samp{regparm}.
! @xref{Function Attributes}.
! @strong{Warning:} if you use this switch, and
! @var{num} is nonzero, then you must build all modules with the same
! value, including any libraries. This includes the system libraries and
! startup modules.
! @item -mpreferred-stack-boundary=@var{num}
! @opindex mpreferred-stack-boundary
! Attempt to keep the stack boundary aligned to a 2 raised to @var{num}
! byte boundary. If @option{-mpreferred-stack-boundary} is not specified,
! the default is 4 (16 bytes or 128 bits), except when optimizing for code
! size (@option{-Os}), in which case the default is the minimum correct
! alignment (4 bytes for x86, and 8 bytes for x86-64).
! On Pentium and PentiumPro, @code{double} and @code{long double} values
! should be aligned to an 8 byte boundary (see @option{-malign-double}) or
! suffer significant run time performance penalties. On Pentium III, the
! Streaming SIMD Extension (SSE) data type @code{__m128} suffers similar
! penalties if it is not 16 byte aligned.
! To ensure proper alignment of this values on the stack, the stack boundary
! must be as aligned as that required by any value stored on the stack.
! Further, every function must be generated such that it keeps the stack
! aligned. Thus calling a function compiled with a higher preferred
! stack boundary from a function compiled with a lower preferred stack
! boundary will most likely misalign the stack. It is recommended that
! libraries that use callbacks always use the default setting.
! This extra alignment does consume extra stack space, and generally
! increases code size. Code that is sensitive to stack space usage, such
! as embedded systems and operating system kernels, may want to reduce the
! preferred alignment to @option{-mpreferred-stack-boundary=2}.
! @item -mmmx
! @itemx -mno-mmx
! @item -msse
! @itemx -mno-sse
! @item -msse2
! @itemx -mno-sse2
! @item -msse3
! @itemx -mno-sse3
! @item -m3dnow
! @itemx -mno-3dnow
! @opindex mmmx
! @opindex mno-mmx
! @opindex msse
! @opindex mno-sse
! @opindex m3dnow
! @opindex mno-3dnow
! These switches enable or disable the use of built-in functions that allow
! direct access to the MMX, SSE, SSE2, SSE3 and 3Dnow extensions of the
! instruction set.
! @xref{X86 Built-in Functions}, for details of the functions enabled
! and disabled by these switches.
! To have SSE/SSE2 instructions generated automatically from floating-point
! code, see @option{-mfpmath=sse}.
! @item -mpush-args
! @itemx -mno-push-args
! @opindex mpush-args
! @opindex mno-push-args
! Use PUSH operations to store outgoing parameters. This method is shorter
! and usually equally fast as method using SUB/MOV operations and is enabled
! by default. In some cases disabling it may improve performance because of
! improved scheduling and reduced dependencies.
! @item -maccumulate-outgoing-args
! @opindex maccumulate-outgoing-args
! If enabled, the maximum amount of space required for outgoing arguments will be
! computed in the function prologue. This is faster on most modern CPUs
! because of reduced dependencies, improved scheduling and reduced stack usage
! when preferred stack boundary is not equal to 2. The drawback is a notable
! increase in code size. This switch implies @option{-mno-push-args}.
! @item -mthreads
! @opindex mthreads
! Support thread-safe exception handling on @samp{Mingw32}. Code that relies
! on thread-safe exception handling must compile and link all code with the
! @option{-mthreads} option. When compiling, @option{-mthreads} defines
! @option{-D_MT}; when linking, it links in a special thread helper library
! @option{-lmingwthrd} which cleans up per thread exception handling data.
! @item -mno-align-stringops
! @opindex mno-align-stringops
! Do not align destination of inlined string operations. This switch reduces
! code size and improves performance in case the destination is already aligned,
! but GCC doesn't know about it.
! @item -minline-all-stringops
! @opindex minline-all-stringops
! By default GCC inlines string operations only when destination is known to be
! aligned at least to 4 byte boundary. This enables more inlining, increase code
! size, but may improve performance of code that depends on fast memcpy, strlen
! and memset for short lengths.
! @item -momit-leaf-frame-pointer
! @opindex momit-leaf-frame-pointer
! Don't keep the frame pointer in a register for leaf functions. This
! avoids the instructions to save, set up and restore frame pointers and
! makes an extra register available in leaf functions. The option
! @option{-fomit-frame-pointer} removes the frame pointer for all functions
! which might make debugging harder.
! @item -mtls-direct-seg-refs
! @itemx -mno-tls-direct-seg-refs
! @opindex mtls-direct-seg-refs
! Controls whether TLS variables may be accessed with offsets from the
! TLS segment register (@code{%gs} for 32-bit, @code{%fs} for 64-bit),
! or whether the thread base pointer must be added. Whether or not this
! is legal depends on the operating system, and whether it maps the
! segment to cover the entire TLS area.
! For systems that use GNU libc, the default is on.
! @end table
! These @samp{-m} switches are supported in addition to the above
! on AMD x86-64 processors in 64-bit environments.
! @table @gcctabopt
! @item -m32
! @itemx -m64
! @opindex m32
! @opindex m64
! Generate code for a 32-bit or 64-bit environment.
! The 32-bit environment sets int, long and pointer to 32 bits and
! generates code that runs on any i386 system.
! The 64-bit environment sets int to 32 bits and long and pointer
! to 64 bits and generates code for AMD's x86-64 architecture.
! @item -mno-red-zone
! @opindex no-red-zone
! Do not use a so called red zone for x86-64 code. The red zone is mandated
! by the x86-64 ABI, it is a 128-byte area beyond the location of the
! stack pointer that will not be modified by signal or interrupt handlers
! and therefore can be used for temporary data without adjusting the stack
! pointer. The flag @option{-mno-red-zone} disables this red zone.
! @item -mcmodel=small
! @opindex mcmodel=small
! Generate code for the small code model: the program and its symbols must
! be linked in the lower 2 GB of the address space. Pointers are 64 bits.
! Programs can be statically or dynamically linked. This is the default
! code model.
! @item -mcmodel=kernel
! @opindex mcmodel=kernel
! Generate code for the kernel code model. The kernel runs in the
! negative 2 GB of the address space.
! This model has to be used for Linux kernel code.
! @item -mcmodel=medium
! @opindex mcmodel=medium
! Generate code for the medium model: The program is linked in the lower 2
! GB of the address space but symbols can be located anywhere in the
! address space. Programs can be statically or dynamically linked, but
! building of shared libraries are not supported with the medium model.
!
! @item -mcmodel=large
! @opindex mcmodel=large
! Generate code for the large model: This model makes no assumptions
! about addresses and sizes of sections. Currently GCC does not implement
! this model.
@end table
! @node IA-64 Options
! @subsection IA-64 Options
! @cindex IA-64 Options
! These are the @samp{-m} options defined for the Intel IA-64 architecture.
@table @gcctabopt
! @item -mbig-endian
! @opindex mbig-endian
! Generate code for a big endian target. This is the default for HP-UX@.
! @item -mlittle-endian
! @opindex mlittle-endian
! Generate code for a little endian target. This is the default for AIX5
! and GNU/Linux.
! @item -mgnu-as
! @itemx -mno-gnu-as
! @opindex mgnu-as
! @opindex mno-gnu-as
! Generate (or don't) code for the GNU assembler. This is the default.
! @c Also, this is the default if the configure option @option{--with-gnu-as}
! @c is used.
! @item -mgnu-ld
! @itemx -mno-gnu-ld
! @opindex mgnu-ld
! @opindex mno-gnu-ld
! Generate (or don't) code for the GNU linker. This is the default.
! @c Also, this is the default if the configure option @option{--with-gnu-ld}
! @c is used.
! @item -mno-pic
! @opindex mno-pic
! Generate code that does not use a global pointer register. The result
! is not position independent code, and violates the IA-64 ABI@.
! @item -mvolatile-asm-stop
! @itemx -mno-volatile-asm-stop
! @opindex mvolatile-asm-stop
! @opindex mno-volatile-asm-stop
! Generate (or don't) a stop bit immediately before and after volatile asm
! statements.
! @item -mb-step
! @opindex mb-step
! Generate code that works around Itanium B step errata.
! @item -mregister-names
! @itemx -mno-register-names
! @opindex mregister-names
! @opindex mno-register-names
! Generate (or don't) @samp{in}, @samp{loc}, and @samp{out} register names for
! the stacked registers. This may make assembler output more readable.
! @item -mno-sdata
! @itemx -msdata
! @opindex mno-sdata
! @opindex msdata
! Disable (or enable) optimizations that use the small data section. This may
! be useful for working around optimizer bugs.
! @item -mconstant-gp
! @opindex mconstant-gp
! Generate code that uses a single constant global pointer value. This is
! useful when compiling kernel code.
! @item -mauto-pic
! @opindex mauto-pic
! Generate code that is self-relocatable. This implies @option{-mconstant-gp}.
! This is useful when compiling firmware code.
! @item -minline-float-divide-min-latency
! @opindex minline-float-divide-min-latency
! Generate code for inline divides of floating point values
! using the minimum latency algorithm.
! @item -minline-float-divide-max-throughput
! @opindex minline-float-divide-max-throughput
! Generate code for inline divides of floating point values
! using the maximum throughput algorithm.
! @item -minline-int-divide-min-latency
! @opindex minline-int-divide-min-latency
! Generate code for inline divides of integer values
! using the minimum latency algorithm.
! @item -minline-int-divide-max-throughput
! @opindex minline-int-divide-max-throughput
! Generate code for inline divides of integer values
! using the maximum throughput algorithm.
! @item -mno-dwarf2-asm
! @itemx -mdwarf2-asm
! @opindex mno-dwarf2-asm
! @opindex mdwarf2-asm
! Don't (or do) generate assembler code for the DWARF2 line number debugging
! info. This may be useful when not using the GNU assembler.
! @item -mfixed-range=@var{register-range}
! @opindex mfixed-range
! Generate code treating the given register range as fixed registers.
! A fixed register is one that the register allocator can not use. This is
! useful when compiling kernel code. A register range is specified as
! two registers separated by a dash. Multiple register ranges can be
! specified separated by a comma.
! @item -mearly-stop-bits
! @itemx -mno-early-stop-bits
! @opindex mearly-stop-bits
! @opindex mno-early-stop-bits
! Allow stop bits to be placed earlier than immediately preceding the
! instruction that triggered the stop bit. This can improve instruction
! scheduling, but does not always do so.
! @end table
! @node M32R/D Options
! @subsection M32R/D Options
! @cindex M32R/D options
! These @option{-m} options are defined for Renesas M32R/D architectures:
! @table @gcctabopt
! @item -m32r2
! @opindex m32r2
! Generate code for the M32R/2@.
! @item -m32rx
! @opindex m32rx
! Generate code for the M32R/X@.
! @item -m32r
! @opindex m32r
! Generate code for the M32R@. This is the default.
! @item -mmodel=small
! @opindex mmodel=small
! Assume all objects live in the lower 16MB of memory (so that their addresses
! can be loaded with the @code{ld24} instruction), and assume all subroutines
! are reachable with the @code{bl} instruction.
! This is the default.
! The addressability of a particular object can be set with the
! @code{model} attribute.
! @item -mmodel=medium
! @opindex mmodel=medium
! Assume objects may be anywhere in the 32-bit address space (the compiler
! will generate @code{seth/add3} instructions to load their addresses), and
! assume all subroutines are reachable with the @code{bl} instruction.
! @item -mmodel=large
! @opindex mmodel=large
! Assume objects may be anywhere in the 32-bit address space (the compiler
! will generate @code{seth/add3} instructions to load their addresses), and
! assume subroutines may not be reachable with the @code{bl} instruction
! (the compiler will generate the much slower @code{seth/add3/jl}
! instruction sequence).
! @item -msdata=none
! @opindex msdata=none
! Disable use of the small data area. Variables will be put into
! one of @samp{.data}, @samp{bss}, or @samp{.rodata} (unless the
! @code{section} attribute has been specified).
! This is the default.
+ The small data area consists of sections @samp{.sdata} and @samp{.sbss}.
+ Objects may be explicitly put in the small data area with the
+ @code{section} attribute using one of these sections.
! @item -msdata=sdata
! @opindex msdata=sdata
! Put small global and static data in the small data area, but do not
! generate special code to reference them.
! @item -msdata=use
! @opindex msdata=use
! Put small global and static data in the small data area, and generate
! special instructions to reference them.
! @item -G @var{num}
! @opindex G
! @cindex smaller data references
! Put global and static objects less than or equal to @var{num} bytes
! into the small data or bss sections instead of the normal data or bss
! sections. The default value of @var{num} is 8.
! The @option{-msdata} option must be set to one of @samp{sdata} or @samp{use}
! for this option to have any effect.
! All modules should be compiled with the same @option{-G @var{num}} value.
! Compiling with different values of @var{num} may or may not work; if it
! doesn't the linker will give an error message---incorrect code will not be
! generated.
! @item -mdebug
! @opindex mdebug
! Makes the M32R specific code in the compiler display some statistics
! that might help in debugging programs.
! @item -malign-loops
! @opindex malign-loops
! Align all loops to a 32-byte boundary.
! @item -mno-align-loops
! @opindex mno-align-loops
! Do not enforce a 32-byte alignment for loops. This is the default.
! @item -missue-rate=@var{number}
! @opindex missue-rate=@var{number}
! Issue @var{number} instructions per cycle. @var{number} can only be 1
! or 2.
! @item -mbranch-cost=@var{number}
! @opindex mbranch-cost=@var{number}
! @var{number} can only be 1 or 2. If it is 1 then branches will be
! preferred over conditional code, if it is 2, then the opposite will
! apply.
!
! @item -mflush-trap=@var{number}
! @opindex mflush-trap=@var{number}
! Specifies the trap number to use to flush the cache. The default is
! 12. Valid numbers are between 0 and 15 inclusive.
! @item -mno-flush-trap
! @opindex mno-flush-trap
! Specifies that the cache cannot be flushed by using a trap.
! @item -mflush-func=@var{name}
! @opindex mflush-func=@var{name}
! Specifies the name of the operating system function to call to flush
! the cache. The default is @emph{_flush_cache}, but a function call
! will only be used if a trap is not available.
! @item -mno-flush-func
! @opindex mno-flush-func
! Indicates that there is no OS function for flushing the cache.
! @end table
! @node M680x0 Options
! @subsection M680x0 Options
! @cindex M680x0 options
! These are the @samp{-m} options defined for the 68000 series. The default
! values for these options depends on which style of 68000 was selected when
! the compiler was configured; the defaults for the most common choices are
! given below.
! @table @gcctabopt
! @item -m68000
! @itemx -mc68000
! @opindex m68000
! @opindex mc68000
! Generate output for a 68000. This is the default
! when the compiler is configured for 68000-based systems.
! Use this option for microcontrollers with a 68000 or EC000 core,
! including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356.
! @item -m68020
! @itemx -mc68020
! @opindex m68020
! @opindex mc68020
! Generate output for a 68020. This is the default
! when the compiler is configured for 68020-based systems.
! @item -m68881
! @opindex m68881
! Generate output containing 68881 instructions for floating point.
! This is the default for most 68020 systems unless @option{--nfp} was
! specified when the compiler was configured.
! @item -m68030
! @opindex m68030
! Generate output for a 68030. This is the default when the compiler is
! configured for 68030-based systems.
! @item -m68040
! @opindex m68040
! Generate output for a 68040. This is the default when the compiler is
! configured for 68040-based systems.
! This option inhibits the use of 68881/68882 instructions that have to be
! emulated by software on the 68040. Use this option if your 68040 does not
! have code to emulate those instructions.
! @item -m68060
! @opindex m68060
! Generate output for a 68060. This is the default when the compiler is
! configured for 68060-based systems.
! This option inhibits the use of 68020 and 68881/68882 instructions that
! have to be emulated by software on the 68060. Use this option if your 68060
! does not have code to emulate those instructions.
! @item -mcpu32
! @opindex mcpu32
! Generate output for a CPU32. This is the default
! when the compiler is configured for CPU32-based systems.
! Use this option for microcontrollers with a
! CPU32 or CPU32+ core, including the 68330, 68331, 68332, 68333, 68334,
! 68336, 68340, 68341, 68349 and 68360.
! @item -m5200
! @opindex m5200
! Generate output for a 520X ``coldfire'' family cpu. This is the default
! when the compiler is configured for 520X-based systems.
! Use this option for microcontroller with a 5200 core, including
! the MCF5202, MCF5203, MCF5204 and MCF5202.
! @item -m68020-40
! @opindex m68020-40
! Generate output for a 68040, without using any of the new instructions.
! This results in code which can run relatively efficiently on either a
! 68020/68881 or a 68030 or a 68040. The generated code does use the
! 68881 instructions that are emulated on the 68040.
! @item -m68020-60
! @opindex m68020-60
! Generate output for a 68060, without using any of the new instructions.
! This results in code which can run relatively efficiently on either a
! 68020/68881 or a 68030 or a 68040. The generated code does use the
! 68881 instructions that are emulated on the 68060.
! @item -msoft-float
! @opindex msoft-float
! Generate output containing library calls for floating point.
! @strong{Warning:} the requisite libraries are not available for all m68k
! targets. Normally the facilities of the machine's usual C compiler are
! used, but this can't be done directly in cross-compilation. You must
! make your own arrangements to provide suitable library functions for
! cross-compilation. The embedded targets @samp{m68k-*-aout} and
! @samp{m68k-*-coff} do provide software floating point support.
! @item -mshort
! @opindex mshort
! Consider type @code{int} to be 16 bits wide, like @code{short int}.
! Additionally, parameters passed on the stack are also aligned to a
! 16-bit boundary even on targets whose API mandates promotion to 32-bit.
! @item -mnobitfield
! @opindex mnobitfield
! Do not use the bit-field instructions. The @option{-m68000}, @option{-mcpu32}
! and @option{-m5200} options imply @w{@option{-mnobitfield}}.
!
! @item -mbitfield
! @opindex mbitfield
! Do use the bit-field instructions. The @option{-m68020} option implies
! @option{-mbitfield}. This is the default if you use a configuration
! designed for a 68020.
!
! @item -mrtd
! @opindex mrtd
! Use a different function-calling convention, in which functions
! that take a fixed number of arguments return with the @code{rtd}
! instruction, which pops their arguments while returning. This
! saves one instruction in the caller since there is no need to pop
! the arguments there.
! This calling convention is incompatible with the one normally
! used on Unix, so you cannot use it if you need to call libraries
! compiled with the Unix compiler.
! Also, you must provide function prototypes for all functions that
! take variable numbers of arguments (including @code{printf});
! otherwise incorrect code will be generated for calls to those
! functions.
! In addition, seriously incorrect code will result if you call a
! function with too many arguments. (Normally, extra arguments are
! harmlessly ignored.)
! The @code{rtd} instruction is supported by the 68010, 68020, 68030,
! 68040, 68060 and CPU32 processors, but not by the 68000 or 5200.
! @item -malign-int
! @itemx -mno-align-int
! @opindex malign-int
! @opindex mno-align-int
! Control whether GCC aligns @code{int}, @code{long}, @code{long long},
! @code{float}, @code{double}, and @code{long double} variables on a 32-bit
! boundary (@option{-malign-int}) or a 16-bit boundary (@option{-mno-align-int}).
! Aligning variables on 32-bit boundaries produces code that runs somewhat
! faster on processors with 32-bit busses at the expense of more memory.
! @strong{Warning:} if you use the @option{-malign-int} switch, GCC will
! align structures containing the above types differently than
! most published application binary interface specifications for the m68k.
! @item -mpcrel
! @opindex mpcrel
! Use the pc-relative addressing mode of the 68000 directly, instead of
! using a global offset table. At present, this option implies @option{-fpic},
! allowing at most a 16-bit offset for pc-relative addressing. @option{-fPIC} is
! not presently supported with @option{-mpcrel}, though this could be supported for
! 68020 and higher processors.
! @item -mno-strict-align
! @itemx -mstrict-align
! @opindex mno-strict-align
! @opindex mstrict-align
! Do not (do) assume that unaligned memory references will be handled by
! the system.
! @item -msep-data
! Generate code that allows the data segment to be located in a different
! area of memory from the text segment. This allows for execute in place in
! an environment without virtual memory management. This option implies -fPIC.
! @item -mno-sep-data
! Generate code that assumes that the data segment follows the text segment.
! This is the default.
! @item -mid-shared-library
! Generate code that supports shared libraries via the library ID method.
! This allows for execute in place and shared libraries in an environment
! without virtual memory management. This option implies -fPIC.
! @item -mno-id-shared-library
! Generate code that doesn't assume ID based shared libraries are being used.
! This is the default.
! @item -mshared-library-id=n
! Specified the identification number of the ID based shared library being
! compiled. Specifying a value of 0 will generate more compact code, specifying
! other values will force the allocation of that number to the current
! library but is no more space or time efficient than omitting this option.
! @end table
! @node M68hc1x Options
! @subsection M68hc1x Options
! @cindex M68hc1x options
! These are the @samp{-m} options defined for the 68hc11 and 68hc12
! microcontrollers. The default values for these options depends on
! which style of microcontroller was selected when the compiler was configured;
! the defaults for the most common choices are given below.
! @table @gcctabopt
! @item -m6811
! @itemx -m68hc11
! @opindex m6811
! @opindex m68hc11
! Generate output for a 68HC11. This is the default
! when the compiler is configured for 68HC11-based systems.
! @item -m6812
! @itemx -m68hc12
! @opindex m6812
! @opindex m68hc12
! Generate output for a 68HC12. This is the default
! when the compiler is configured for 68HC12-based systems.
! @item -m68S12
! @itemx -m68hcs12
! @opindex m68S12
! @opindex m68hcs12
! Generate output for a 68HCS12.
! @item -mauto-incdec
! @opindex mauto-incdec
! Enable the use of 68HC12 pre and post auto-increment and auto-decrement
! addressing modes.
! @item -minmax
! @itemx -nominmax
! @opindex minmax
! @opindex mnominmax
! Enable the use of 68HC12 min and max instructions.
! @item -mlong-calls
! @itemx -mno-long-calls
! @opindex mlong-calls
! @opindex mno-long-calls
! Treat all calls as being far away (near). If calls are assumed to be
! far away, the compiler will use the @code{call} instruction to
! call a function and the @code{rtc} instruction for returning.
! @item -mshort
! @opindex mshort
! Consider type @code{int} to be 16 bits wide, like @code{short int}.
! @item -msoft-reg-count=@var{count}
! @opindex msoft-reg-count
! Specify the number of pseudo-soft registers which are used for the
! code generation. The maximum number is 32. Using more pseudo-soft
! register may or may not result in better code depending on the program.
! The default is 4 for 68HC11 and 2 for 68HC12.
! @end table
! @node MCore Options
! @subsection MCore Options
! @cindex MCore options
! These are the @samp{-m} options defined for the Motorola M*Core
! processors.
! @table @gcctabopt
! @item -mhardlit
! @itemx -mno-hardlit
! @opindex mhardlit
! @opindex mno-hardlit
! Inline constants into the code stream if it can be done in two
! instructions or less.
! @item -mdiv
! @itemx -mno-div
! @opindex mdiv
! @opindex mno-div
! Use the divide instruction. (Enabled by default).
! @item -mrelax-immediate
! @itemx -mno-relax-immediate
! @opindex mrelax-immediate
! @opindex mno-relax-immediate
! Allow arbitrary sized immediates in bit operations.
! @item -mwide-bitfields
! @itemx -mno-wide-bitfields
! @opindex mwide-bitfields
! @opindex mno-wide-bitfields
! Always treat bit-fields as int-sized.
! @item -m4byte-functions
! @itemx -mno-4byte-functions
! @opindex m4byte-functions
! @opindex mno-4byte-functions
! Force all functions to be aligned to a four byte boundary.
! @item -mcallgraph-data
! @itemx -mno-callgraph-data
! @opindex mcallgraph-data
! @opindex mno-callgraph-data
! Emit callgraph information.
! @item -mslow-bytes
! @itemx -mno-slow-bytes
! @opindex mslow-bytes
! @opindex mno-slow-bytes
! Prefer word access when reading byte quantities.
! @item -mlittle-endian
! @itemx -mbig-endian
! @opindex mlittle-endian
! @opindex mbig-endian
! Generate code for a little endian target.
! @item -m210
! @itemx -m340
! @opindex m210
! @opindex m340
! Generate code for the 210 processor.
@end table
! @node MIPS Options
! @subsection MIPS Options
! @cindex MIPS options
@table @gcctabopt
! @item -EB
! @opindex EB
! Generate big-endian code.
! @item -EL
! @opindex EL
! Generate little-endian code. This is the default for @samp{mips*el-*-*}
! configurations.
! @item -march=@var{arch}
! @opindex march
! Generate code that will run on @var{arch}, which can be the name of a
! generic MIPS ISA, or the name of a particular processor.
! The ISA names are:
! @samp{mips1}, @samp{mips2}, @samp{mips3}, @samp{mips4},
! @samp{mips32}, @samp{mips32r2}, and @samp{mips64}.
! The processor names are:
! @samp{4kc}, @samp{4kp}, @samp{5kc}, @samp{20kc},
! @samp{m4k},
! @samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400},
! @samp{r4600}, @samp{r4650}, @samp{r6000}, @samp{r8000}, @samp{rm7000},
! @samp{rm9000},
! @samp{orion},
! @samp{sb1},
! @samp{vr4100}, @samp{vr4111}, @samp{vr4120}, @samp{vr4130}, @samp{vr4300},
! @samp{vr5000}, @samp{vr5400} and @samp{vr5500}.
! The special value @samp{from-abi} selects the
! most compatible architecture for the selected ABI (that is,
! @samp{mips1} for 32-bit ABIs and @samp{mips3} for 64-bit ABIs)@.
! In processor names, a final @samp{000} can be abbreviated as @samp{k}
! (for example, @samp{-march=r2k}). Prefixes are optional, and
! @samp{vr} may be written @samp{r}.
! GCC defines two macros based on the value of this option. The first
! is @samp{_MIPS_ARCH}, which gives the name of target architecture, as
! a string. The second has the form @samp{_MIPS_ARCH_@var{foo}},
! where @var{foo} is the capitalized value of @samp{_MIPS_ARCH}@.
! For example, @samp{-march=r2000} will set @samp{_MIPS_ARCH}
! to @samp{"r2000"} and define the macro @samp{_MIPS_ARCH_R2000}.
! Note that the @samp{_MIPS_ARCH} macro uses the processor names given
! above. In other words, it will have the full prefix and will not
! abbreviate @samp{000} as @samp{k}. In the case of @samp{from-abi},
! the macro names the resolved architecture (either @samp{"mips1"} or
! @samp{"mips3"}). It names the default architecture when no
! @option{-march} option is given.
! @item -mtune=@var{arch}
! @opindex mtune
! Optimize for @var{arch}. Among other things, this option controls
! the way instructions are scheduled, and the perceived cost of arithmetic
! operations. The list of @var{arch} values is the same as for
! @option{-march}.
! When this option is not used, GCC will optimize for the processor
! specified by @option{-march}. By using @option{-march} and
! @option{-mtune} together, it is possible to generate code that will
! run on a family of processors, but optimize the code for one
! particular member of that family.
! @samp{-mtune} defines the macros @samp{_MIPS_TUNE} and
! @samp{_MIPS_TUNE_@var{foo}}, which work in the same way as the
! @samp{-march} ones described above.
! @item -mips1
! @opindex mips1
! Equivalent to @samp{-march=mips1}.
! @item -mips2
! @opindex mips2
! Equivalent to @samp{-march=mips2}.
! @item -mips3
! @opindex mips3
! Equivalent to @samp{-march=mips3}.
! @item -mips4
! @opindex mips4
! Equivalent to @samp{-march=mips4}.
!
! @item -mips32
! @opindex mips32
! Equivalent to @samp{-march=mips32}.
! @item -mips32r2
! @opindex mips32r2
! Equivalent to @samp{-march=mips32r2}.
! @item -mips64
! @opindex mips64
! Equivalent to @samp{-march=mips64}.
! @item -mips16
! @itemx -mno-mips16
! @opindex mips16
! @opindex mno-mips16
! Use (do not use) the MIPS16 ISA.
! @item -mabi=32
! @itemx -mabi=o64
! @itemx -mabi=n32
! @itemx -mabi=64
! @itemx -mabi=eabi
! @opindex mabi=32
! @opindex mabi=o64
! @opindex mabi=n32
! @opindex mabi=64
! @opindex mabi=eabi
! Generate code for the given ABI@.
! Note that the EABI has a 32-bit and a 64-bit variant. GCC normally
! generates 64-bit code when you select a 64-bit architecture, but you
! can use @option{-mgp32} to get 32-bit code instead.
! For information about the O64 ABI, see
! @w{@uref{http://gcc.gnu.org/projects/mipso64-abi.html}}.
! @item -mabicalls
! @itemx -mno-abicalls
! @opindex mabicalls
! @opindex mno-abicalls
! Generate (do not generate) SVR4-style position-independent code.
! @option{-mabicalls} is the default for SVR4-based systems.
! @item -mxgot
! @itemx -mno-xgot
! @opindex mxgot
! @opindex mno-xgot
! Lift (do not lift) the usual restrictions on the size of the global
! offset table.
! GCC normally uses a single instruction to load values from the GOT.
! While this is relatively efficient, it will only work if the GOT
! is smaller than about 64k. Anything larger will cause the linker
! to report an error such as:
! @cindex relocation truncated to fit (MIPS)
! @smallexample
! relocation truncated to fit: R_MIPS_GOT16 foobar
! @end smallexample
! If this happens, you should recompile your code with @option{-mxgot}.
! It should then work with very large GOTs, although it will also be
! less efficient, since it will take three instructions to fetch the
! value of a global symbol.
! Note that some linkers can create multiple GOTs. If you have such a
! linker, you should only need to use @option{-mxgot} when a single object
! file accesses more than 64k's worth of GOT entries. Very few do.
! These options have no effect unless GCC is generating position
! independent code.
! @item -mgp32
! @opindex mgp32
! Assume that general-purpose registers are 32 bits wide.
! @item -mgp64
! @opindex mgp64
! Assume that general-purpose registers are 64 bits wide.
! @item -mfp32
! @opindex mfp32
! Assume that floating-point registers are 32 bits wide.
! @item -mfp64
! @opindex mfp64
! Assume that floating-point registers are 64 bits wide.
! @item -mhard-float
! @opindex mhard-float
! Use floating-point coprocessor instructions.
! @item -msoft-float
! @opindex msoft-float
! Do not use floating-point coprocessor instructions. Implement
! floating-point calculations using library calls instead.
! @item -msingle-float
! @opindex msingle-float
! Assume that the floating-point coprocessor only supports single-precision
! operations.
! @itemx -mdouble-float
! @opindex mdouble-float
! Assume that the floating-point coprocessor supports double-precision
! operations. This is the default.
! @item -mint64
! @opindex mint64
! Force @code{int} and @code{long} types to be 64 bits wide. See
! @option{-mlong32} for an explanation of the default and the way
! that the pointer size is determined.
! @item -mlong64
! @opindex mlong64
! Force @code{long} types to be 64 bits wide. See @option{-mlong32} for
! an explanation of the default and the way that the pointer size is
! determined.
! @item -mlong32
! @opindex mlong32
! Force @code{long}, @code{int}, and pointer types to be 32 bits wide.
! The default size of @code{int}s, @code{long}s and pointers depends on
! the ABI@. All the supported ABIs use 32-bit @code{int}s. The n64 ABI
! uses 64-bit @code{long}s, as does the 64-bit EABI; the others use
! 32-bit @code{long}s. Pointers are the same size as @code{long}s,
! or the same size as integer registers, whichever is smaller.
! @item -G @var{num}
! @opindex G
! @cindex smaller data references (MIPS)
! @cindex gp-relative references (MIPS)
! Put global and static items less than or equal to @var{num} bytes into
! the small data or bss section instead of the normal data or bss section.
! This allows the data to be accessed using a single instruction.
!
! All modules should be compiled with the same @option{-G @var{num}}
! value.
! @item -membedded-data
! @itemx -mno-embedded-data
! @opindex membedded-data
! @opindex mno-embedded-data
! Allocate variables to the read-only data section first if possible, then
! next in the small data section if possible, otherwise in data. This gives
! slightly slower code than the default, but reduces the amount of RAM required
! when executing, and thus may be preferred for some embedded systems.
! @item -muninit-const-in-rodata
! @itemx -mno-uninit-const-in-rodata
! @opindex muninit-const-in-rodata
! @opindex mno-uninit-const-in-rodata
! Put uninitialized @code{const} variables in the read-only data section.
! This option is only meaningful in conjunction with @option{-membedded-data}.
! @item -msplit-addresses
! @itemx -mno-split-addresses
! @opindex msplit-addresses
! @opindex mno-split-addresses
! Enable (disable) use of the @code{%hi()} and @code{%lo()} assembler
! relocation operators. This option has been superceded by
! @option{-mexplicit-relocs} but is retained for backwards compatibility.
! @item -mexplicit-relocs
! @itemx -mno-explicit-relocs
! @opindex mexplicit-relocs
! @opindex mno-explicit-relocs
! Use (do not use) assembler relocation operators when dealing with symbolic
! addresses. The alternative, selected by @option{-mno-explicit-relocs},
! is to use assembler macros instead.
! @option{-mexplicit-relocs} is usually the default if GCC was configured
! to use an assembler that supports relocation operators. However, the
! combination of @option{-mabicalls} and @option{-fno-unit-at-a-time}
! implies @option{-mno-explicit-relocs} unless explicitly overridden.
! This is because, when generating abicalls, the choice of relocation
! depends on whether a symbol is local or global. In some rare cases,
! GCC will not be able to decide this until the whole compilation unit
! has been read.
! @item -mrnames
! @itemx -mno-rnames
! @opindex mrnames
! @opindex mno-rnames
! Generate (do not generate) code that refers to registers using their
! software names. The default is @option{-mno-rnames}, which tells GCC
! to use hardware names like @samp{$4} instead of software names like
! @samp{a0}. The only assembler known to support @option{-rnames} is
! the Algorithmics assembler.
! @item -mcheck-zero-division
! @itemx -mno-check-zero-division
! @opindex mcheck-zero-division
! @opindex mno-check-zero-division
! Trap (do not trap) on integer division by zero. The default is
! @option{-mcheck-zero-division}.
! @item -mmemcpy
! @itemx -mno-memcpy
! @opindex mmemcpy
! @opindex mno-memcpy
! Force (do not force) the use of @code{memcpy()} for non-trivial block
! moves. The default is @option{-mno-memcpy}, which allows GCC to inline
! most constant-sized copies.
! @item -mlong-calls
! @itemx -mno-long-calls
! @opindex mlong-calls
! @opindex mno-long-calls
! Disable (do not disable) use of the @code{jal} instruction. Calling
! functions using @code{jal} is more efficient but requires the caller
! and callee to be in the same 256 megabyte segment.
! This option has no effect on abicalls code. The default is
! @option{-mno-long-calls}.
! @item -mmad
! @itemx -mno-mad
! @opindex mmad
! @opindex mno-mad
! Enable (disable) use of the @code{mad}, @code{madu} and @code{mul}
! instructions, as provided by the R4650 ISA.
! @item -mfused-madd
! @itemx -mno-fused-madd
! @opindex mfused-madd
! @opindex mno-fused-madd
! Enable (disable) use of the floating point multiply-accumulate
! instructions, when they are available. The default is
! @option{-mfused-madd}.
! When multiply-accumulate instructions are used, the intermediate
! product is calculated to infinite precision and is not subject to
! the FCSR Flush to Zero bit. This may be undesirable in some
! circumstances.
! @item -nocpp
! @opindex nocpp
! Tell the MIPS assembler to not run its preprocessor over user
! assembler files (with a @samp{.s} suffix) when assembling them.
! @item -mfix-r4000
! @itemx -mno-fix-r4000
! @opindex mfix-r4000
! @opindex mno-fix-r4000
! Work around certain R4000 CPU errata:
! @itemize @minus
! @item
! A double-word or a variable shift may give an incorrect result if executed
! immediately after starting an integer division.
! @item
! A double-word or a variable shift may give an incorrect result if executed
! while an integer multiplication is in progress.
! @item
! An integer division may give an incorrect result if started in a delay slot
! of a taken branch or a jump.
! @end itemize
! @item -mfix-r4400
! @itemx -mno-fix-r4400
! @opindex mfix-r4400
! @opindex mno-fix-r4400
! Work around certain R4400 CPU errata:
! @itemize @minus
! @item
! A double-word or a variable shift may give an incorrect result if executed
! immediately after starting an integer division.
! @end itemize
! @item -mfix-vr4120
! @itemx -mno-fix-vr4120
! @opindex mfix-vr4120
! Work around certain VR4120 errata:
! @itemize @minus
! @item
! @code{dmultu} does not always produce the correct result.
! @item
! @code{div} and @code{ddiv} do not always produce the correct result if one
! of the operands is negative.
! @end itemize
! The workarounds for the division errata rely on special functions in
! @file{libgcc.a}. At present, these functions are only provided by
! the @code{mips64vr*-elf} configurations.
! Other VR4120 errata require a nop to be inserted between certain pairs of
! instructions. These errata are handled by the assembler, not by GCC itself.
! @item -mfix-sb1
! @itemx -mno-fix-sb1
! @opindex mfix-sb1
! Work around certain SB-1 CPU core errata.
! (This flag currently works around the SB-1 revision 2
! ``F1'' and ``F2'' floating point errata.)
! @item -mflush-func=@var{func}
! @itemx -mno-flush-func
! @opindex mflush-func
! Specifies the function to call to flush the I and D caches, or to not
! call any such function. If called, the function must take the same
! arguments as the common @code{_flush_func()}, that is, the address of the
! memory range for which the cache is being flushed, the size of the
! memory range, and the number 3 (to flush both caches). The default
! depends on the target GCC was configured for, but commonly is either
! @samp{_flush_func} or @samp{__cpu_flush}.
! @item -mbranch-likely
! @itemx -mno-branch-likely
! @opindex mbranch-likely
! @opindex mno-branch-likely
! Enable or disable use of Branch Likely instructions, regardless of the
! default for the selected architecture. By default, Branch Likely
! instructions may be generated if they are supported by the selected
! architecture. An exception is for the MIPS32 and MIPS64 architectures
! and processors which implement those architectures; for those, Branch
! Likely instructions will not be generated by default because the MIPS32
! and MIPS64 architectures specifically deprecate their use.
! @item -mfp-exceptions
! @itemx -mno-fp-exceptions
! @opindex mfp-exceptions
! Specifies whether FP exceptions are enabled. This affects how we schedule
! FP instructions for some processors. The default is that FP exceptions are
! enabled.
! For instance, on the SB-1, if FP exceptions are disabled, and we are emitting
! 64-bit code, then we can use both FP pipes. Otherwise, we can only use one
! FP pipe.
! @item -mvr4130-align
! @itemx -mno-vr4130-align
! @opindex mvr4130-align
! The VR4130 pipeline is two-way superscalar, but can only issue two
! instructions together if the first one is 8-byte aligned. When this
! option is enabled, GCC will align pairs of instructions that it
! thinks should execute in parallel.
! This option only has an effect when optimizing for the VR4130.
! It normally makes code faster, but at the expense of making it bigger.
! It is enabled by default at optimization level @option{-O3}.
! @end table
! @node MMIX Options
! @subsection MMIX Options
! @cindex MMIX Options
! These options are defined for the MMIX:
! @table @gcctabopt
! @item -mlibfuncs
! @itemx -mno-libfuncs
! @opindex mlibfuncs
! @opindex mno-libfuncs
! Specify that intrinsic library functions are being compiled, passing all
! values in registers, no matter the size.
! @item -mepsilon
! @itemx -mno-epsilon
! @opindex mepsilon
! @opindex mno-epsilon
! Generate floating-point comparison instructions that compare with respect
! to the @code{rE} epsilon register.
! @item -mabi=mmixware
! @itemx -mabi=gnu
! @opindex mabi-mmixware
! @opindex mabi=gnu
! Generate code that passes function parameters and return values that (in
! the called function) are seen as registers @code{$0} and up, as opposed to
! the GNU ABI which uses global registers @code{$231} and up.
! @item -mzero-extend
! @itemx -mno-zero-extend
! @opindex mzero-extend
! @opindex mno-zero-extend
! When reading data from memory in sizes shorter than 64 bits, use (do not
! use) zero-extending load instructions by default, rather than
! sign-extending ones.
! @item -mknuthdiv
! @itemx -mno-knuthdiv
! @opindex mknuthdiv
! @opindex mno-knuthdiv
! Make the result of a division yielding a remainder have the same sign as
! the divisor. With the default, @option{-mno-knuthdiv}, the sign of the
! remainder follows the sign of the dividend. Both methods are
! arithmetically valid, the latter being almost exclusively used.
! @item -mtoplevel-symbols
! @itemx -mno-toplevel-symbols
! @opindex mtoplevel-symbols
! @opindex mno-toplevel-symbols
! Prepend (do not prepend) a @samp{:} to all global symbols, so the assembly
! code can be used with the @code{PREFIX} assembly directive.
! @item -melf
! @opindex melf
! Generate an executable in the ELF format, rather than the default
! @samp{mmo} format used by the @command{mmix} simulator.
! @item -mbranch-predict
! @itemx -mno-branch-predict
! @opindex mbranch-predict
! @opindex mno-branch-predict
! Use (do not use) the probable-branch instructions, when static branch
! prediction indicates a probable branch.
! @item -mbase-addresses
! @itemx -mno-base-addresses
! @opindex mbase-addresses
! @opindex mno-base-addresses
! Generate (do not generate) code that uses @emph{base addresses}. Using a
! base address automatically generates a request (handled by the assembler
! and the linker) for a constant to be set up in a global register. The
! register is used for one or more base address requests within the range 0
! to 255 from the value held in the register. The generally leads to short
! and fast code, but the number of different data items that can be
! addressed is limited. This means that a program that uses lots of static
! data may require @option{-mno-base-addresses}.
! @item -msingle-exit
! @itemx -mno-single-exit
! @opindex msingle-exit
! @opindex mno-single-exit
! Force (do not force) generated code to have a single exit point in each
! function.
! @end table
! @node MN10300 Options
! @subsection MN10300 Options
! @cindex MN10300 options
! These @option{-m} options are defined for Matsushita MN10300 architectures:
! @table @gcctabopt
! @item -mmult-bug
! @opindex mmult-bug
! Generate code to avoid bugs in the multiply instructions for the MN10300
! processors. This is the default.
! @item -mno-mult-bug
! @opindex mno-mult-bug
! Do not generate code to avoid bugs in the multiply instructions for the
! MN10300 processors.
! @item -mam33
! @opindex mam33
! Generate code which uses features specific to the AM33 processor.
! @item -mno-am33
! @opindex mno-am33
! Do not generate code which uses features specific to the AM33 processor. This
! is the default.
! @item -mno-crt0
! @opindex mno-crt0
! Do not link in the C run-time initialization object file.
! @item -mrelax
! @opindex mrelax
! Indicate to the linker that it should perform a relaxation optimization pass
! to shorten branches, calls and absolute memory addresses. This option only
! has an effect when used on the command line for the final link step.
!
! This option makes symbolic debugging impossible.
@end table
! @node NS32K Options
! @subsection NS32K Options
! @cindex NS32K options
! These are the @samp{-m} options defined for the 32000 series. The default
! values for these options depends on which style of 32000 was selected when
! the compiler was configured; the defaults for the most common choices are
! given below.
@table @gcctabopt
! @item -m32032
! @itemx -m32032
! @opindex m32032
! @opindex m32032
! Generate output for a 32032. This is the default
! when the compiler is configured for 32032 and 32016 based systems.
! @item -m32332
! @itemx -m32332
! @opindex m32332
! @opindex m32332
! Generate output for a 32332. This is the default
! when the compiler is configured for 32332-based systems.
! @item -m32532
! @itemx -m32532
! @opindex m32532
! @opindex m32532
! Generate output for a 32532. This is the default
! when the compiler is configured for 32532-based systems.
! @item -m32081
! @opindex m32081
! Generate output containing 32081 instructions for floating point.
! This is the default for all systems.
! @item -m32381
! @opindex m32381
! Generate output containing 32381 instructions for floating point. This
! also implies @option{-m32081}. The 32381 is only compatible with the 32332
! and 32532 cpus. This is the default for the pc532-netbsd configuration.
!
! @item -mmulti-add
! @opindex mmulti-add
! Try and generate multiply-add floating point instructions @code{polyF}
! and @code{dotF}. This option is only available if the @option{-m32381}
! option is in effect. Using these instructions requires changes to
! register allocation which generally has a negative impact on
! performance. This option should only be enabled when compiling code
! particularly likely to make heavy use of multiply-add instructions.
!
! @item -mnomulti-add
! @opindex mnomulti-add
! Do not try and generate multiply-add floating point instructions
! @code{polyF} and @code{dotF}. This is the default on all platforms.
! @item -msoft-float
! @opindex msoft-float
! Generate output containing library calls for floating point.
! @strong{Warning:} the requisite libraries may not be available.
! @item -mieee-compare
! @itemx -mno-ieee-compare
! @opindex mieee-compare
! @opindex mno-ieee-compare
! Control whether or not the compiler uses IEEE floating point
! comparisons. These handle correctly the case where the result of a
! comparison is unordered.
! @strong{Warning:} the requisite kernel support may not be available.
! @item -mnobitfield
! @opindex mnobitfield
! Do not use the bit-field instructions. On some machines it is faster to
! use shifting and masking operations. This is the default for the pc532.
! @item -mbitfield
! @opindex mbitfield
! Do use the bit-field instructions. This is the default for all platforms
! except the pc532.
! @item -mrtd
! @opindex mrtd
! Use a different function-calling convention, in which functions
! that take a fixed number of arguments return pop their
! arguments on return with the @code{ret} instruction.
! This calling convention is incompatible with the one normally
! used on Unix, so you cannot use it if you need to call libraries
! compiled with the Unix compiler.
! Also, you must provide function prototypes for all functions that
! take variable numbers of arguments (including @code{printf});
! otherwise incorrect code will be generated for calls to those
! functions.
! In addition, seriously incorrect code will result if you call a
! function with too many arguments. (Normally, extra arguments are
! harmlessly ignored.)
! This option takes its name from the 680x0 @code{rtd} instruction.
! @item -mregparam
! @opindex mregparam
! Use a different function-calling convention where the first two arguments
! are passed in registers.
! This calling convention is incompatible with the one normally
! used on Unix, so you cannot use it if you need to call libraries
! compiled with the Unix compiler.
! @item -mnoregparam
! @opindex mnoregparam
! Do not pass any arguments in registers. This is the default for all
! targets.
! @item -msb
! @opindex msb
! It is OK to use the sb as an index register which is always loaded with
! zero. This is the default for the pc532-netbsd target.
! @item -mnosb
! @opindex mnosb
! The sb register is not available for use or has not been initialized to
! zero by the run time system. This is the default for all targets except
! the pc532-netbsd. It is also implied whenever @option{-mhimem} or
! @option{-fpic} is set.
! @item -mhimem
! @opindex mhimem
! Many ns32000 series addressing modes use displacements of up to 512MB@.
! If an address is above 512MB then displacements from zero can not be used.
! This option causes code to be generated which can be loaded above 512MB@.
! This may be useful for operating systems or ROM code.
! @item -mnohimem
! @opindex mnohimem
! Assume code will be loaded in the first 512MB of virtual address space.
! This is the default for all platforms.
@end table
! @node PDP-11 Options
! @subsection PDP-11 Options
! @cindex PDP-11 Options
! These options are defined for the PDP-11:
@table @gcctabopt
! @item -mfpu
! @opindex mfpu
! Use hardware FPP floating point. This is the default. (FIS floating
! point on the PDP-11/40 is not supported.)
! @item -msoft-float
! @opindex msoft-float
! Do not use hardware floating point.
! @item -mac0
! @opindex mac0
! Return floating-point results in ac0 (fr0 in Unix assembler syntax).
! @item -mno-ac0
! @opindex mno-ac0
! Return floating-point results in memory. This is the default.
!
! @item -m40
! @opindex m40
! Generate code for a PDP-11/40.
!
! @item -m45
! @opindex m45
! Generate code for a PDP-11/45. This is the default.
! @item -m10
! @opindex m10
! Generate code for a PDP-11/10.
! @item -mbcopy-builtin
! @opindex bcopy-builtin
! Use inline @code{movstrhi} patterns for copying memory. This is the
! default.
! @item -mbcopy
! @opindex mbcopy
! Do not use inline @code{movstrhi} patterns for copying memory.
! @item -mint16
! @itemx -mno-int32
! @opindex mint16
! @opindex mno-int32
! Use 16-bit @code{int}. This is the default.
! @item -mint32
! @itemx -mno-int16
! @opindex mint32
! @opindex mno-int16
! Use 32-bit @code{int}.
! @item -mfloat64
! @itemx -mno-float32
! @opindex mfloat64
! @opindex mno-float32
! Use 64-bit @code{float}. This is the default.
! @item -mfloat32
! @itemx -mno-float64
! @opindex mfloat32
! @opindex mno-float64
! Use 32-bit @code{float}.
! @item -mabshi
! @opindex mabshi
! Use @code{abshi2} pattern. This is the default.
! @item -mno-abshi
! @opindex mno-abshi
! Do not use @code{abshi2} pattern.
! @item -mbranch-expensive
! @opindex mbranch-expensive
! Pretend that branches are expensive. This is for experimenting with
! code generation only.
! @item -mbranch-cheap
! @opindex mbranch-cheap
! Do not pretend that branches are expensive. This is the default.
! @item -msplit
! @opindex msplit
! Generate code for a system with split I&D.
! @item -mno-split
! @opindex mno-split
! Generate code for a system without split I&D. This is the default.
! @item -munix-asm
! @opindex munix-asm
! Use Unix assembler syntax. This is the default when configured for
! @samp{pdp11-*-bsd}.
! @item -mdec-asm
! @opindex mdec-asm
! Use DEC assembler syntax. This is the default when configured for any
! PDP-11 target other than @samp{pdp11-*-bsd}.
! @end table
! @node PowerPC Options
! @subsection PowerPC Options
! @cindex PowerPC options
! These are listed under @xref{RS/6000 and PowerPC Options}.
! @node RS/6000 and PowerPC Options
! @subsection IBM RS/6000 and PowerPC Options
! @cindex RS/6000 and PowerPC Options
! @cindex IBM RS/6000 and PowerPC Options
! These @samp{-m} options are defined for the IBM RS/6000 and PowerPC:
! @table @gcctabopt
! @item -mpower
! @itemx -mno-power
! @itemx -mpower2
! @itemx -mno-power2
! @itemx -mpowerpc
! @itemx -mno-powerpc
! @itemx -mpowerpc-gpopt
! @itemx -mno-powerpc-gpopt
! @itemx -mpowerpc-gfxopt
! @itemx -mno-powerpc-gfxopt
! @itemx -mpowerpc64
! @itemx -mno-powerpc64
! @opindex mpower
! @opindex mno-power
! @opindex mpower2
! @opindex mno-power2
! @opindex mpowerpc
! @opindex mno-powerpc
! @opindex mpowerpc-gpopt
! @opindex mno-powerpc-gpopt
! @opindex mpowerpc-gfxopt
! @opindex mno-powerpc-gfxopt
! @opindex mpowerpc64
! @opindex mno-powerpc64
! GCC supports two related instruction set architectures for the
! RS/6000 and PowerPC@. The @dfn{POWER} instruction set are those
! instructions supported by the @samp{rios} chip set used in the original
! RS/6000 systems and the @dfn{PowerPC} instruction set is the
! architecture of the Motorola MPC5xx, MPC6xx, MPC8xx microprocessors, and
! the IBM 4xx microprocessors.
! Neither architecture is a subset of the other. However there is a
! large common subset of instructions supported by both. An MQ
! register is included in processors supporting the POWER architecture.
! You use these options to specify which instructions are available on the
! processor you are using. The default value of these options is
! determined when configuring GCC@. Specifying the
! @option{-mcpu=@var{cpu_type}} overrides the specification of these
! options. We recommend you use the @option{-mcpu=@var{cpu_type}} option
! rather than the options listed above.
! The @option{-mpower} option allows GCC to generate instructions that
! are found only in the POWER architecture and to use the MQ register.
! Specifying @option{-mpower2} implies @option{-power} and also allows GCC
! to generate instructions that are present in the POWER2 architecture but
! not the original POWER architecture.
! The @option{-mpowerpc} option allows GCC to generate instructions that
! are found only in the 32-bit subset of the PowerPC architecture.
! Specifying @option{-mpowerpc-gpopt} implies @option{-mpowerpc} and also allows
! GCC to use the optional PowerPC architecture instructions in the
! General Purpose group, including floating-point square root. Specifying
! @option{-mpowerpc-gfxopt} implies @option{-mpowerpc} and also allows GCC to
! use the optional PowerPC architecture instructions in the Graphics
! group, including floating-point select.
! The @option{-mpowerpc64} option allows GCC to generate the additional
! 64-bit instructions that are found in the full PowerPC64 architecture
! and to treat GPRs as 64-bit, doubleword quantities. GCC defaults to
! @option{-mno-powerpc64}.
! If you specify both @option{-mno-power} and @option{-mno-powerpc}, GCC
! will use only the instructions in the common subset of both
! architectures plus some special AIX common-mode calls, and will not use
! the MQ register. Specifying both @option{-mpower} and @option{-mpowerpc}
! permits GCC to use any instruction from either architecture and to
! allow use of the MQ register; specify this for the Motorola MPC601.
! @item -mnew-mnemonics
! @itemx -mold-mnemonics
! @opindex mnew-mnemonics
! @opindex mold-mnemonics
! Select which mnemonics to use in the generated assembler code. With
! @option{-mnew-mnemonics}, GCC uses the assembler mnemonics defined for
! the PowerPC architecture. With @option{-mold-mnemonics} it uses the
! assembler mnemonics defined for the POWER architecture. Instructions
! defined in only one architecture have only one mnemonic; GCC uses that
! mnemonic irrespective of which of these options is specified.
! GCC defaults to the mnemonics appropriate for the architecture in
! use. Specifying @option{-mcpu=@var{cpu_type}} sometimes overrides the
! value of these option. Unless you are building a cross-compiler, you
! should normally not specify either @option{-mnew-mnemonics} or
! @option{-mold-mnemonics}, but should instead accept the default.
! @item -mcpu=@var{cpu_type}
! @opindex mcpu
! Set architecture type, register usage, choice of mnemonics, and
! instruction scheduling parameters for machine type @var{cpu_type}.
! Supported values for @var{cpu_type} are @samp{401}, @samp{403},
! @samp{405}, @samp{405fp}, @samp{440}, @samp{440fp}, @samp{505},
! @samp{601}, @samp{602}, @samp{603}, @samp{603e}, @samp{604},
! @samp{604e}, @samp{620}, @samp{630}, @samp{740}, @samp{7400},
! @samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823},
! @samp{860}, @samp{970}, @samp{common}, @samp{ec603e}, @samp{G3},
! @samp{G4}, @samp{G5}, @samp{power}, @samp{power2}, @samp{power3},
! @samp{power4}, @samp{power5}, @samp{powerpc}, @samp{powerpc64},
! @samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64a}.
! @option{-mcpu=common} selects a completely generic processor. Code
! generated under this option will run on any POWER or PowerPC processor.
! GCC will use only the instructions in the common subset of both
! architectures, and will not use the MQ register. GCC assumes a generic
! processor model for scheduling purposes.
! @option{-mcpu=power}, @option{-mcpu=power2}, @option{-mcpu=powerpc}, and
! @option{-mcpu=powerpc64} specify generic POWER, POWER2, pure 32-bit
! PowerPC (i.e., not MPC601), and 64-bit PowerPC architecture machine
! types, with an appropriate, generic processor model assumed for
! scheduling purposes.
! The other options specify a specific processor. Code generated under
! those options will run best on that processor, and may not run at all on
! others.
! The @option{-mcpu} options automatically enable or disable the
! following options: @option{-maltivec}, @option{-mhard-float},
! @option{-mmfcrf}, @option{-mmultiple}, @option{-mnew-mnemonics},
! @option{-mpower}, @option{-mpower2}, @option{-mpowerpc64},
! @option{-mpowerpc-gpopt}, @option{-mpowerpc-gfxopt},
! @option{-mstring}. The particular options set for any particular CPU
! will vary between compiler versions, depending on what setting seems
! to produce optimal code for that CPU; it doesn't necessarily reflect
! the actual hardware's capabilities. If you wish to set an individual
! option to a particular value, you may specify it after the
! @option{-mcpu} option, like @samp{-mcpu=970 -mno-altivec}.
! On AIX, the @option{-maltivec} and @option{-mpowerpc64} options are
! not enabled or disabled by the @option{-mcpu} option at present, since
! AIX does not have full support for these options. You may still
! enable or disable them individually if you're sure it'll work in your
! environment.
! @item -mtune=@var{cpu_type}
! @opindex mtune
! Set the instruction scheduling parameters for machine type
! @var{cpu_type}, but do not set the architecture type, register usage, or
! choice of mnemonics, as @option{-mcpu=@var{cpu_type}} would. The same
! values for @var{cpu_type} are used for @option{-mtune} as for
! @option{-mcpu}. If both are specified, the code generated will use the
! architecture, registers, and mnemonics set by @option{-mcpu}, but the
! scheduling parameters set by @option{-mtune}.
! @item -maltivec
! @itemx -mno-altivec
! @opindex maltivec
! @opindex mno-altivec
! These switches enable or disable the use of built-in functions that
! allow access to the AltiVec instruction set. You may also need to set
! @option{-mabi=altivec} to adjust the current ABI with AltiVec ABI
! enhancements.
! @item -mabi=spe
! @opindex mabi=spe
! Extend the current ABI with SPE ABI extensions. This does not change
! the default ABI, instead it adds the SPE ABI extensions to the current
! ABI@.
! @item -mabi=no-spe
! @opindex mabi=no-spe
! Disable Booke SPE ABI extensions for the current ABI.
! @item -misel=@var{yes/no}
! @itemx -misel
! @opindex misel
! This switch enables or disables the generation of ISEL instructions.
! @item -mspe=@var{yes/no}
! @itemx -mspe
! @opindex mspe
! This switch enables or disables the generation of SPE simd
! instructions.
+ @item -mfloat-gprs=@var{yes/no}
+ @itemx -mfloat-gprs
+ @opindex mfloat-gprs
+ This switch enables or disables the generation of floating point
+ operations on the general purpose registers for architectures that
+ support it. This option is currently only available on the MPC8540.
! @item -mfull-toc
! @itemx -mno-fp-in-toc
! @itemx -mno-sum-in-toc
! @itemx -mminimal-toc
! @opindex mfull-toc
! @opindex mno-fp-in-toc
! @opindex mno-sum-in-toc
! @opindex mminimal-toc
! Modify generation of the TOC (Table Of Contents), which is created for
! every executable file. The @option{-mfull-toc} option is selected by
! default. In that case, GCC will allocate at least one TOC entry for
! each unique non-automatic variable reference in your program. GCC
! will also place floating-point constants in the TOC@. However, only
! 16,384 entries are available in the TOC@.
! If you receive a linker error message that saying you have overflowed
! the available TOC space, you can reduce the amount of TOC space used
! with the @option{-mno-fp-in-toc} and @option{-mno-sum-in-toc} options.
! @option{-mno-fp-in-toc} prevents GCC from putting floating-point
! constants in the TOC and @option{-mno-sum-in-toc} forces GCC to
! generate code to calculate the sum of an address and a constant at
! run-time instead of putting that sum into the TOC@. You may specify one
! or both of these options. Each causes GCC to produce very slightly
! slower and larger code at the expense of conserving TOC space.
! If you still run out of space in the TOC even when you specify both of
! these options, specify @option{-mminimal-toc} instead. This option causes
! GCC to make only one TOC entry for every file. When you specify this
! option, GCC will produce code that is slower and larger but which
! uses extremely little TOC space. You may wish to use this option
! only on files that contain less frequently executed code.
! @item -maix64
! @itemx -maix32
! @opindex maix64
! @opindex maix32
! Enable 64-bit AIX ABI and calling convention: 64-bit pointers, 64-bit
! @code{long} type, and the infrastructure needed to support them.
! Specifying @option{-maix64} implies @option{-mpowerpc64} and
! @option{-mpowerpc}, while @option{-maix32} disables the 64-bit ABI and
! implies @option{-mno-powerpc64}. GCC defaults to @option{-maix32}.
! @item -mxl-call
! @itemx -mno-xl-call
! @opindex mxl-call
! @opindex mno-xl-call
! On AIX, pass floating-point arguments to prototyped functions beyond the
! register save area (RSA) on the stack in addition to argument FPRs. The
! AIX calling convention was extended but not initially documented to
! handle an obscure K&R C case of calling a function that takes the
! address of its arguments with fewer arguments than declared. AIX XL
! compilers access floating point arguments which do not fit in the
! RSA from the stack when a subroutine is compiled without
! optimization. Because always storing floating-point arguments on the
! stack is inefficient and rarely needed, this option is not enabled by
! default and only is necessary when calling subroutines compiled by AIX
! XL compilers without optimization.
! @item -mpe
! @opindex mpe
! Support @dfn{IBM RS/6000 SP} @dfn{Parallel Environment} (PE)@. Link an
! application written to use message passing with special startup code to
! enable the application to run. The system must have PE installed in the
! standard location (@file{/usr/lpp/ppe.poe/}), or the @file{specs} file
! must be overridden with the @option{-specs=} option to specify the
! appropriate directory location. The Parallel Environment does not
! support threads, so the @option{-mpe} option and the @option{-pthread}
! option are incompatible.
! @item -malign-natural
! @itemx -malign-power
! @opindex malign-natural
! @opindex malign-power
! On AIX, Darwin, and 64-bit PowerPC GNU/Linux, the option
! @option{-malign-natural} overrides the ABI-defined alignment of larger
! types, such as floating-point doubles, on their natural size-based boundary.
! The option @option{-malign-power} instructs GCC to follow the ABI-specified
! alignment rules. GCC defaults to the standard alignment defined in the ABI.
+ @item -msoft-float
+ @itemx -mhard-float
+ @opindex msoft-float
+ @opindex mhard-float
+ Generate code that does not use (uses) the floating-point register set.
+ Software floating point emulation is provided if you use the
+ @option{-msoft-float} option, and pass the option to GCC when linking.
! @item -mmultiple
! @itemx -mno-multiple
! @opindex mmultiple
! @opindex mno-multiple
! Generate code that uses (does not use) the load multiple word
! instructions and the store multiple word instructions. These
! instructions are generated by default on POWER systems, and not
! generated on PowerPC systems. Do not use @option{-mmultiple} on little
! endian PowerPC systems, since those instructions do not work when the
! processor is in little endian mode. The exceptions are PPC740 and
! PPC750 which permit the instructions usage in little endian mode.
! @item -mstring
! @itemx -mno-string
! @opindex mstring
! @opindex mno-string
! Generate code that uses (does not use) the load string instructions
! and the store string word instructions to save multiple registers and
! do small block moves. These instructions are generated by default on
! POWER systems, and not generated on PowerPC systems. Do not use
! @option{-mstring} on little endian PowerPC systems, since those
! instructions do not work when the processor is in little endian mode.
! The exceptions are PPC740 and PPC750 which permit the instructions
! usage in little endian mode.
! @item -mupdate
! @itemx -mno-update
! @opindex mupdate
! @opindex mno-update
! Generate code that uses (does not use) the load or store instructions
! that update the base register to the address of the calculated memory
! location. These instructions are generated by default. If you use
! @option{-mno-update}, there is a small window between the time that the
! stack pointer is updated and the address of the previous frame is
! stored, which means code that walks the stack frame across interrupts or
! signals may get corrupted data.
! @item -mfused-madd
! @itemx -mno-fused-madd
! @opindex mfused-madd
! @opindex mno-fused-madd
! Generate code that uses (does not use) the floating point multiply and
! accumulate instructions. These instructions are generated by default if
! hardware floating is used.
! @item -mno-bit-align
! @itemx -mbit-align
! @opindex mno-bit-align
! @opindex mbit-align
! On System V.4 and embedded PowerPC systems do not (do) force structures
! and unions that contain bit-fields to be aligned to the base type of the
! bit-field.
! For example, by default a structure containing nothing but 8
! @code{unsigned} bit-fields of length 1 would be aligned to a 4 byte
! boundary and have a size of 4 bytes. By using @option{-mno-bit-align},
! the structure would be aligned to a 1 byte boundary and be one byte in
! size.
! @item -mno-strict-align
! @itemx -mstrict-align
! @opindex mno-strict-align
! @opindex mstrict-align
! On System V.4 and embedded PowerPC systems do not (do) assume that
! unaligned memory references will be handled by the system.
! @item -mrelocatable
! @itemx -mno-relocatable
! @opindex mrelocatable
! @opindex mno-relocatable
! On embedded PowerPC systems generate code that allows (does not allow)
! the program to be relocated to a different address at runtime. If you
! use @option{-mrelocatable} on any module, all objects linked together must
! be compiled with @option{-mrelocatable} or @option{-mrelocatable-lib}.
! @item -mrelocatable-lib
! @itemx -mno-relocatable-lib
! @opindex mrelocatable-lib
! @opindex mno-relocatable-lib
! On embedded PowerPC systems generate code that allows (does not allow)
! the program to be relocated to a different address at runtime. Modules
! compiled with @option{-mrelocatable-lib} can be linked with either modules
! compiled without @option{-mrelocatable} and @option{-mrelocatable-lib} or
! with modules compiled with the @option{-mrelocatable} options.
! @item -mno-toc
! @itemx -mtoc
! @opindex mno-toc
! @opindex mtoc
! On System V.4 and embedded PowerPC systems do not (do) assume that
! register 2 contains a pointer to a global area pointing to the addresses
! used in the program.
! @item -mlittle
! @itemx -mlittle-endian
! @opindex mlittle
! @opindex mlittle-endian
! On System V.4 and embedded PowerPC systems compile code for the
! processor in little endian mode. The @option{-mlittle-endian} option is
! the same as @option{-mlittle}.
! @item -mbig
! @itemx -mbig-endian
! @opindex mbig
! @opindex mbig-endian
! On System V.4 and embedded PowerPC systems compile code for the
! processor in big endian mode. The @option{-mbig-endian} option is
! the same as @option{-mbig}.
! @item -mdynamic-no-pic
! @opindex mdynamic-no-pic
! On Darwin and Mac OS X systems, compile code so that it is not
! relocatable, but that its external references are relocatable. The
! resulting code is suitable for applications, but not shared
! libraries.
! @item -mprioritize-restricted-insns=@var{priority}
! @opindex mprioritize-restricted-insns
! This option controls the priority that is assigned to
! dispatch-slot restricted instructions during the second scheduling
! pass. The argument @var{priority} takes the value @var{0/1/2} to assign
! @var{no/highest/second-highest} priority to dispatch slot restricted
! instructions.
! @item -msched-costly-dep=@var{dependence_type}
! @opindex msched-costly-dep
! This option controls which dependences are considered costly
! by the target during instruction scheduling. The argument
! @var{dependence_type} takes one of the following values:
! @var{no}: no dependence is costly,
! @var{all}: all dependences are costly,
! @var{true_store_to_load}: a true dependence from store to load is costly,
! @var{store_to_load}: any dependence from store to load is costly,
! @var{number}: any dependence which latency >= @var{number} is costly.
! @item -minsert-sched-nops=@var{scheme}
! @opindex minsert-sched-nops
! This option controls which nop insertion scheme will be used during
! the second scheduling pass. The argument @var{scheme} takes one of the
! following values:
! @var{no}: Don't insert nops.
! @var{pad}: Pad with nops any dispatch group which has vacant issue slots,
! according to the scheduler's grouping.
! @var{regroup_exact}: Insert nops to force costly dependent insns into
! separate groups. Insert exactly as many nops as needed to force an insn
! to a new group, according to the estimated processor grouping.
! @var{number}: Insert nops to force costly dependent insns into
! separate groups. Insert @var{number} nops to force an insn to a new group.
! @item -mcall-sysv
! @opindex mcall-sysv
! On System V.4 and embedded PowerPC systems compile code using calling
! conventions that adheres to the March 1995 draft of the System V
! Application Binary Interface, PowerPC processor supplement. This is the
! default unless you configured GCC using @samp{powerpc-*-eabiaix}.
! @item -mcall-sysv-eabi
! @opindex mcall-sysv-eabi
! Specify both @option{-mcall-sysv} and @option{-meabi} options.
! @item -mcall-sysv-noeabi
! @opindex mcall-sysv-noeabi
! Specify both @option{-mcall-sysv} and @option{-mno-eabi} options.
! @item -mcall-solaris
! @opindex mcall-solaris
! On System V.4 and embedded PowerPC systems compile code for the Solaris
! operating system.
! @item -mcall-linux
! @opindex mcall-linux
! On System V.4 and embedded PowerPC systems compile code for the
! Linux-based GNU system.
! @item -mcall-gnu
! @opindex mcall-gnu
! On System V.4 and embedded PowerPC systems compile code for the
! Hurd-based GNU system.
! @item -mcall-netbsd
! @opindex mcall-netbsd
! On System V.4 and embedded PowerPC systems compile code for the
! NetBSD operating system.
! @item -maix-struct-return
! @opindex maix-struct-return
! Return all structures in memory (as specified by the AIX ABI)@.
! @item -msvr4-struct-return
! @opindex msvr4-struct-return
! Return structures smaller than 8 bytes in registers (as specified by the
! SVR4 ABI)@.
! @item -mabi=altivec
! @opindex mabi=altivec
! Extend the current ABI with AltiVec ABI extensions. This does not
! change the default ABI, instead it adds the AltiVec ABI extensions to
! the current ABI@.
! @item -mabi=no-altivec
! @opindex mabi=no-altivec
! Disable AltiVec ABI extensions for the current ABI.
! @item -mprototype
! @itemx -mno-prototype
! @opindex mprototype
! @opindex mno-prototype
! On System V.4 and embedded PowerPC systems assume that all calls to
! variable argument functions are properly prototyped. Otherwise, the
! compiler must insert an instruction before every non prototyped call to
! set or clear bit 6 of the condition code register (@var{CR}) to
! indicate whether floating point values were passed in the floating point
! registers in case the function takes a variable arguments. With
! @option{-mprototype}, only calls to prototyped variable argument functions
! will set or clear the bit.
! @item -msim
! @opindex msim
! On embedded PowerPC systems, assume that the startup module is called
! @file{sim-crt0.o} and that the standard C libraries are @file{libsim.a} and
! @file{libc.a}. This is the default for @samp{powerpc-*-eabisim}.
! configurations.
! @item -mmvme
! @opindex mmvme
! On embedded PowerPC systems, assume that the startup module is called
! @file{crt0.o} and the standard C libraries are @file{libmvme.a} and
! @file{libc.a}.
! @item -mads
! @opindex mads
! On embedded PowerPC systems, assume that the startup module is called
! @file{crt0.o} and the standard C libraries are @file{libads.a} and
! @file{libc.a}.
! @item -myellowknife
! @opindex myellowknife
! On embedded PowerPC systems, assume that the startup module is called
! @file{crt0.o} and the standard C libraries are @file{libyk.a} and
! @file{libc.a}.
! @item -mvxworks
! @opindex mvxworks
! On System V.4 and embedded PowerPC systems, specify that you are
! compiling for a VxWorks system.
! @item -mwindiss
! @opindex mwindiss
! Specify that you are compiling for the WindISS simulation environment.
! @item -memb
! @opindex memb
! On embedded PowerPC systems, set the @var{PPC_EMB} bit in the ELF flags
! header to indicate that @samp{eabi} extended relocations are used.
! @item -meabi
! @itemx -mno-eabi
! @opindex meabi
! @opindex mno-eabi
! On System V.4 and embedded PowerPC systems do (do not) adhere to the
! Embedded Applications Binary Interface (eabi) which is a set of
! modifications to the System V.4 specifications. Selecting @option{-meabi}
! means that the stack is aligned to an 8 byte boundary, a function
! @code{__eabi} is called to from @code{main} to set up the eabi
! environment, and the @option{-msdata} option can use both @code{r2} and
! @code{r13} to point to two separate small data areas. Selecting
! @option{-mno-eabi} means that the stack is aligned to a 16 byte boundary,
! do not call an initialization function from @code{main}, and the
! @option{-msdata} option will only use @code{r13} to point to a single
! small data area. The @option{-meabi} option is on by default if you
! configured GCC using one of the @samp{powerpc*-*-eabi*} options.
! @item -msdata=eabi
! @opindex msdata=eabi
! On System V.4 and embedded PowerPC systems, put small initialized
! @code{const} global and static data in the @samp{.sdata2} section, which
! is pointed to by register @code{r2}. Put small initialized
! non-@code{const} global and static data in the @samp{.sdata} section,
! which is pointed to by register @code{r13}. Put small uninitialized
! global and static data in the @samp{.sbss} section, which is adjacent to
! the @samp{.sdata} section. The @option{-msdata=eabi} option is
! incompatible with the @option{-mrelocatable} option. The
! @option{-msdata=eabi} option also sets the @option{-memb} option.
! @item -msdata=sysv
! @opindex msdata=sysv
! On System V.4 and embedded PowerPC systems, put small global and static
! data in the @samp{.sdata} section, which is pointed to by register
! @code{r13}. Put small uninitialized global and static data in the
! @samp{.sbss} section, which is adjacent to the @samp{.sdata} section.
! The @option{-msdata=sysv} option is incompatible with the
! @option{-mrelocatable} option.
! @item -msdata=default
@itemx -msdata
! @opindex msdata=default
@opindex msdata
! On System V.4 and embedded PowerPC systems, if @option{-meabi} is used,
! compile code the same as @option{-msdata=eabi}, otherwise compile code the
! same as @option{-msdata=sysv}.
! @item -msdata-data
! @opindex msdata-data
! On System V.4 and embedded PowerPC systems, put small global and static
! data in the @samp{.sdata} section. Put small uninitialized global and
! static data in the @samp{.sbss} section. Do not use register @code{r13}
! to address small data however. This is the default behavior unless
! other @option{-msdata} options are used.
! @item -msdata=none
! @itemx -mno-sdata
! @opindex msdata=none
! @opindex mno-sdata
! On embedded PowerPC systems, put all initialized global and static data
! in the @samp{.data} section, and all uninitialized data in the
! @samp{.bss} section.
! @item -G @var{num}
! @opindex G
! @cindex smaller data references (PowerPC)
! @cindex .sdata/.sdata2 references (PowerPC)
! On embedded PowerPC systems, put global and static items less than or
! equal to @var{num} bytes into the small data or bss sections instead of
! the normal data or bss section. By default, @var{num} is 8. The
! @option{-G @var{num}} switch is also passed to the linker.
! All modules should be compiled with the same @option{-G @var{num}} value.
! @item -mregnames
! @itemx -mno-regnames
! @opindex mregnames
! @opindex mno-regnames
! On System V.4 and embedded PowerPC systems do (do not) emit register
! names in the assembly language output using symbolic forms.
! @item -mlongcall
! @itemx -mno-longcall
! @opindex mlongcall
! @opindex mno-longcall
! Default to making all function calls indirectly, using a register, so
! that functions which reside further than 32 megabytes (33,554,432
! bytes) from the current location can be called. This setting can be
! overridden by the @code{shortcall} function attribute, or by
! @code{#pragma longcall(0)}.
! Some linkers are capable of detecting out-of-range calls and generating
! glue code on the fly. On these systems, long calls are unnecessary and
! generate slower code. As of this writing, the AIX linker can do this,
! as can the GNU linker for PowerPC/64. It is planned to add this feature
! to the GNU linker for 32-bit PowerPC systems as well.
! On Darwin/PPC systems, @code{#pragma longcall} will generate ``jbsr
! callee, L42'', plus a ``branch island'' (glue code). The two target
! addresses represent the callee and the ``branch island.'' The
! Darwin/PPC linker will prefer the first address and generate a ``bl
! callee'' if the PPC ``bl'' instruction will reach the callee directly;
! otherwise, the linker will generate ``bl L42'' to call the ``branch
! island.'' The ``branch island'' is appended to the body of the
! calling function; it computes the full 32-bit address of the callee
! and jumps to it.
! On Mach-O (Darwin) systems, this option directs the compiler emit to
! the glue for every direct call, and the Darwin linker decides whether
! to use or discard it.
!
! In the future, we may cause GCC to ignore all longcall specifications
! when the linker is known to generate glue.
!
! @item -pthread
! @opindex pthread
! Adds support for multithreading with the @dfn{pthreads} library.
! This option sets flags for both the preprocessor and linker.
@end table
@node S/390 and zSeries Options
*************** accumulate instructions. These instruct
*** 10487,11064 ****
hardware floating point is used.
@end table
! @node CRIS Options
! @subsection CRIS Options
! @cindex CRIS Options
!
! These options are defined specifically for the CRIS ports.
!
! @table @gcctabopt
! @item -march=@var{architecture-type}
! @itemx -mcpu=@var{architecture-type}
! @opindex march
! @opindex mcpu
! Generate code for the specified architecture. The choices for
! @var{architecture-type} are @samp{v3}, @samp{v8} and @samp{v10} for
! respectively ETRAX@w{ }4, ETRAX@w{ }100, and ETRAX@w{ }100@w{ }LX.
! Default is @samp{v0} except for cris-axis-linux-gnu, where the default is
! @samp{v10}.
!
! @item -mtune=@var{architecture-type}
! @opindex mtune
! Tune to @var{architecture-type} everything applicable about the generated
! code, except for the ABI and the set of available instructions. The
! choices for @var{architecture-type} are the same as for
! @option{-march=@var{architecture-type}}.
!
! @item -mmax-stack-frame=@var{n}
! @opindex mmax-stack-frame
! Warn when the stack frame of a function exceeds @var{n} bytes.
!
! @item -melinux-stacksize=@var{n}
! @opindex melinux-stacksize
! Only available with the @samp{cris-axis-aout} target. Arranges for
! indications in the program to the kernel loader that the stack of the
! program should be set to @var{n} bytes.
!
! @item -metrax4
! @itemx -metrax100
! @opindex metrax4
! @opindex metrax100
! The options @option{-metrax4} and @option{-metrax100} are synonyms for
! @option{-march=v3} and @option{-march=v8} respectively.
!
! @item -mmul-bug-workaround
! @itemx -mno-mul-bug-workaround
! @opindex mmul-bug-workaround
! @opindex mno-mul-bug-workaround
! Work around a bug in the @code{muls} and @code{mulu} instructions for CPU
! models where it applies. This option is active by default.
!
! @item -mpdebug
! @opindex mpdebug
! Enable CRIS-specific verbose debug-related information in the assembly
! code. This option also has the effect to turn off the @samp{#NO_APP}
! formatted-code indicator to the assembler at the beginning of the
! assembly file.
!
! @item -mcc-init
! @opindex mcc-init
! Do not use condition-code results from previous instruction; always emit
! compare and test instructions before use of condition codes.
!
! @item -mno-side-effects
! @opindex mno-side-effects
! Do not emit instructions with side-effects in addressing modes other than
! post-increment.
!
! @item -mstack-align
! @itemx -mno-stack-align
! @itemx -mdata-align
! @itemx -mno-data-align
! @itemx -mconst-align
! @itemx -mno-const-align
! @opindex mstack-align
! @opindex mno-stack-align
! @opindex mdata-align
! @opindex mno-data-align
! @opindex mconst-align
! @opindex mno-const-align
! These options (no-options) arranges (eliminate arrangements) for the
! stack-frame, individual data and constants to be aligned for the maximum
! single data access size for the chosen CPU model. The default is to
! arrange for 32-bit alignment. ABI details such as structure layout are
! not affected by these options.
!
! @item -m32-bit
! @itemx -m16-bit
! @itemx -m8-bit
! @opindex m32-bit
! @opindex m16-bit
! @opindex m8-bit
! Similar to the stack- data- and const-align options above, these options
! arrange for stack-frame, writable data and constants to all be 32-bit,
! 16-bit or 8-bit aligned. The default is 32-bit alignment.
!
! @item -mno-prologue-epilogue
! @itemx -mprologue-epilogue
! @opindex mno-prologue-epilogue
! @opindex mprologue-epilogue
! With @option{-mno-prologue-epilogue}, the normal function prologue and
! epilogue that sets up the stack-frame are omitted and no return
! instructions or return sequences are generated in the code. Use this
! option only together with visual inspection of the compiled code: no
! warnings or errors are generated when call-saved registers must be saved,
! or storage for local variable needs to be allocated.
!
! @item -mno-gotplt
! @itemx -mgotplt
! @opindex mno-gotplt
! @opindex mgotplt
! With @option{-fpic} and @option{-fPIC}, don't generate (do generate)
! instruction sequences that load addresses for functions from the PLT part
! of the GOT rather than (traditional on other architectures) calls to the
! PLT. The default is @option{-mgotplt}.
!
! @item -maout
! @opindex maout
! Legacy no-op option only recognized with the cris-axis-aout target.
!
! @item -melf
! @opindex melf
! Legacy no-op option only recognized with the cris-axis-elf and
! cris-axis-linux-gnu targets.
!
! @item -melinux
! @opindex melinux
! Only recognized with the cris-axis-aout target, where it selects a
! GNU/linux-like multilib, include files and instruction set for
! @option{-march=v8}.
!
! @item -mlinux
! @opindex mlinux
! Legacy no-op option only recognized with the cris-axis-linux-gnu target.
!
! @item -sim
! @opindex sim
! This option, recognized for the cris-axis-aout and cris-axis-elf arranges
! to link with input-output functions from a simulator library. Code,
! initialized data and zero-initialized data are allocated consecutively.
!
! @item -sim2
! @opindex sim2
! Like @option{-sim}, but pass linker options to locate initialized data at
! 0x40000000 and zero-initialized data at 0x80000000.
! @end table
!
! @node MMIX Options
! @subsection MMIX Options
! @cindex MMIX Options
! These options are defined for the MMIX:
@table @gcctabopt
! @item -mlibfuncs
! @itemx -mno-libfuncs
! @opindex mlibfuncs
! @opindex mno-libfuncs
! Specify that intrinsic library functions are being compiled, passing all
! values in registers, no matter the size.
!
! @item -mepsilon
! @itemx -mno-epsilon
! @opindex mepsilon
! @opindex mno-epsilon
! Generate floating-point comparison instructions that compare with respect
! to the @code{rE} epsilon register.
!
! @item -mabi=mmixware
! @itemx -mabi=gnu
! @opindex mabi-mmixware
! @opindex mabi=gnu
! Generate code that passes function parameters and return values that (in
! the called function) are seen as registers @code{$0} and up, as opposed to
! the GNU ABI which uses global registers @code{$231} and up.
!
! @item -mzero-extend
! @itemx -mno-zero-extend
! @opindex mzero-extend
! @opindex mno-zero-extend
! When reading data from memory in sizes shorter than 64 bits, use (do not
! use) zero-extending load instructions by default, rather than
! sign-extending ones.
!
! @item -mknuthdiv
! @itemx -mno-knuthdiv
! @opindex mknuthdiv
! @opindex mno-knuthdiv
! Make the result of a division yielding a remainder have the same sign as
! the divisor. With the default, @option{-mno-knuthdiv}, the sign of the
! remainder follows the sign of the dividend. Both methods are
! arithmetically valid, the latter being almost exclusively used.
!
! @item -mtoplevel-symbols
! @itemx -mno-toplevel-symbols
! @opindex mtoplevel-symbols
! @opindex mno-toplevel-symbols
! Prepend (do not prepend) a @samp{:} to all global symbols, so the assembly
! code can be used with the @code{PREFIX} assembly directive.
!
! @item -melf
! @opindex melf
! Generate an executable in the ELF format, rather than the default
! @samp{mmo} format used by the @command{mmix} simulator.
!
! @item -mbranch-predict
! @itemx -mno-branch-predict
! @opindex mbranch-predict
! @opindex mno-branch-predict
! Use (do not use) the probable-branch instructions, when static branch
! prediction indicates a probable branch.
!
! @item -mbase-addresses
! @itemx -mno-base-addresses
! @opindex mbase-addresses
! @opindex mno-base-addresses
! Generate (do not generate) code that uses @emph{base addresses}. Using a
! base address automatically generates a request (handled by the assembler
! and the linker) for a constant to be set up in a global register. The
! register is used for one or more base address requests within the range 0
! to 255 from the value held in the register. The generally leads to short
! and fast code, but the number of different data items that can be
! addressed is limited. This means that a program that uses lots of static
! data may require @option{-mno-base-addresses}.
!
! @item -msingle-exit
! @itemx -mno-single-exit
! @opindex msingle-exit
! @opindex mno-single-exit
! Force (do not force) generated code to have a single exit point in each
! function.
! @end table
!
! @node PDP-11 Options
! @subsection PDP-11 Options
! @cindex PDP-11 Options
! These options are defined for the PDP-11:
! @table @gcctabopt
! @item -mfpu
! @opindex mfpu
! Use hardware FPP floating point. This is the default. (FIS floating
! point on the PDP-11/40 is not supported.)
! @item -msoft-float
! @opindex msoft-float
! Do not use hardware floating point.
! @item -mac0
! @opindex mac0
! Return floating-point results in ac0 (fr0 in Unix assembler syntax).
! @item -mno-ac0
! @opindex mno-ac0
! Return floating-point results in memory. This is the default.
! @item -m40
! @opindex m40
! Generate code for a PDP-11/40.
! @item -m45
! @opindex m45
! Generate code for a PDP-11/45. This is the default.
! @item -m10
! @opindex m10
! Generate code for a PDP-11/10.
! @item -mbcopy-builtin
! @opindex bcopy-builtin
! Use inline @code{movstrhi} patterns for copying memory. This is the
! default.
! @item -mbcopy
! @opindex mbcopy
! Do not use inline @code{movstrhi} patterns for copying memory.
! @item -mint16
! @itemx -mno-int32
! @opindex mint16
! @opindex mno-int32
! Use 16-bit @code{int}. This is the default.
! @item -mint32
! @itemx -mno-int16
! @opindex mint32
! @opindex mno-int16
! Use 32-bit @code{int}.
! @item -mfloat64
! @itemx -mno-float32
! @opindex mfloat64
! @opindex mno-float32
! Use 64-bit @code{float}. This is the default.
! @item -mfloat32
! @itemx -mno-float64
! @opindex mfloat32
! @opindex mno-float64
! Use 32-bit @code{float}.
! @item -mabshi
! @opindex mabshi
! Use @code{abshi2} pattern. This is the default.
! @item -mno-abshi
! @opindex mno-abshi
! Do not use @code{abshi2} pattern.
! @item -mbranch-expensive
! @opindex mbranch-expensive
! Pretend that branches are expensive. This is for experimenting with
! code generation only.
! @item -mbranch-cheap
! @opindex mbranch-cheap
! Do not pretend that branches are expensive. This is the default.
! @item -msplit
! @opindex msplit
! Generate code for a system with split I&D.
! @item -mno-split
! @opindex mno-split
! Generate code for a system without split I&D. This is the default.
! @item -munix-asm
! @opindex munix-asm
! Use Unix assembler syntax. This is the default when configured for
! @samp{pdp11-*-bsd}.
! @item -mdec-asm
! @opindex mdec-asm
! Use DEC assembler syntax. This is the default when configured for any
! PDP-11 target other than @samp{pdp11-*-bsd}.
@end table
! @node Xstormy16 Options
! @subsection Xstormy16 Options
! @cindex Xstormy16 Options
! These options are defined for Xstormy16:
@table @gcctabopt
! @item -msim
! @opindex msim
! Choose startup files and linker script suitable for the simulator.
! @end table
! @node FRV Options
! @subsection FRV Options
! @cindex FRV Options
! @table @gcctabopt
! @item -mgpr-32
! @opindex mgpr-32
! Only use the first 32 general purpose registers.
! @item -mgpr-64
! @opindex mgpr-64
! Use all 64 general purpose registers.
! @item -mfpr-32
! @opindex mfpr-32
! Use only the first 32 floating point registers.
! @item -mfpr-64
! @opindex mfpr-64
! Use all 64 floating point registers
! @item -mhard-float
! @opindex mhard-float
! Use hardware instructions for floating point operations.
! @item -msoft-float
! @opindex msoft-float
! Use library routines for floating point operations.
! @item -malloc-cc
! @opindex malloc-cc
! Dynamically allocate condition code registers.
! @item -mfixed-cc
! @opindex mfixed-cc
! Do not try to dynamically allocate condition code registers, only
! use @code{icc0} and @code{fcc0}.
! @item -mdword
! @opindex mdword
! Change ABI to use double word insns.
! @item -mno-dword
! @opindex mno-dword
! Do not use double word instructions.
! @item -mdouble
! @opindex mdouble
! Use floating point double instructions.
! @item -mno-double
! @opindex mno-double
! Do not use floating point double instructions.
! @item -mmedia
! @opindex mmedia
! Use media instructions.
! @item -mno-media
! @opindex mno-media
! Do not use media instructions.
! @item -mmuladd
! @opindex mmuladd
! Use multiply and add/subtract instructions.
! @item -mno-muladd
! @opindex mno-muladd
! Do not use multiply and add/subtract instructions.
! @item -mlibrary-pic
! @opindex mlibrary-pic
! Generate position-independent EABI code.
! @item -macc-4
! @opindex macc-4
! Use only the first four media accumulator registers.
! @item -macc-8
! @opindex macc-8
! Use all eight media accumulator registers.
! @item -mpack
! @opindex mpack
! Pack VLIW instructions.
! @item -mno-pack
! @opindex mno-pack
! Do not pack VLIW instructions.
! @item -mno-eflags
! @opindex mno-eflags
! Do not mark ABI switches in e_flags.
! @item -mcond-move
! @opindex mcond-move
! Enable the use of conditional-move instructions (default).
! This switch is mainly for debugging the compiler and will likely be removed
! in a future version.
! @item -mno-cond-move
! @opindex mno-cond-move
! Disable the use of conditional-move instructions.
! This switch is mainly for debugging the compiler and will likely be removed
! in a future version.
! @item -mscc
! @opindex mscc
! Enable the use of conditional set instructions (default).
! This switch is mainly for debugging the compiler and will likely be removed
! in a future version.
! @item -mno-scc
! @opindex mno-scc
! Disable the use of conditional set instructions.
! This switch is mainly for debugging the compiler and will likely be removed
! in a future version.
! @item -mcond-exec
! @opindex mcond-exec
! Enable the use of conditional execution (default).
! This switch is mainly for debugging the compiler and will likely be removed
! in a future version.
! @item -mno-cond-exec
! @opindex mno-cond-exec
! Disable the use of conditional execution.
! This switch is mainly for debugging the compiler and will likely be removed
! in a future version.
! @item -mvliw-branch
! @opindex mvliw-branch
! Run a pass to pack branches into VLIW instructions (default).
! This switch is mainly for debugging the compiler and will likely be removed
! in a future version.
! @item -mno-vliw-branch
! @opindex mno-vliw-branch
! Do not run a pass to pack branches into VLIW instructions.
! This switch is mainly for debugging the compiler and will likely be removed
! in a future version.
! @item -mmulti-cond-exec
! @opindex mmulti-cond-exec
! Enable optimization of @code{&&} and @code{||} in conditional execution
! (default).
! This switch is mainly for debugging the compiler and will likely be removed
! in a future version.
! @item -mno-multi-cond-exec
! @opindex mno-multi-cond-exec
! Disable optimization of @code{&&} and @code{||} in conditional execution.
! This switch is mainly for debugging the compiler and will likely be removed
! in a future version.
! @item -mnested-cond-exec
! @opindex mnested-cond-exec
! Enable nested conditional execution optimizations (default).
! This switch is mainly for debugging the compiler and will likely be removed
! in a future version.
! @item -mno-nested-cond-exec
! @opindex mno-nested-cond-exec
! Disable nested conditional execution optimizations.
! This switch is mainly for debugging the compiler and will likely be removed
! in a future version.
! @item -mtomcat-stats
! @opindex mtomcat-stats
! Cause gas to print out tomcat statistics.
! @item -mcpu=@var{cpu}
! @opindex mcpu
! Select the processor type for which to generate code. Possible values are
! @samp{simple}, @samp{tomcat}, @samp{fr500}, @samp{fr400}, @samp{fr300},
! @samp{frv}.
@end table
@node Xtensa Options
--- 10386,11077 ----
hardware floating point is used.
@end table
! @node SH Options
! @subsection SH Options
! These @samp{-m} options are defined for the SH implementations:
@table @gcctabopt
! @item -m1
! @opindex m1
! Generate code for the SH1.
! @item -m2
! @opindex m2
! Generate code for the SH2.
! @item -m2e
! Generate code for the SH2e.
! @item -m3
! @opindex m3
! Generate code for the SH3.
! @item -m3e
! @opindex m3e
! Generate code for the SH3e.
! @item -m4-nofpu
! @opindex m4-nofpu
! Generate code for the SH4 without a floating-point unit.
! @item -m4-single-only
! @opindex m4-single-only
! Generate code for the SH4 with a floating-point unit that only
! supports single-precision arithmetic.
! @item -m4-single
! @opindex m4-single
! Generate code for the SH4 assuming the floating-point unit is in
! single-precision mode by default.
! @item -m4
! @opindex m4
! Generate code for the SH4.
! @item -mb
! @opindex mb
! Compile code for the processor in big endian mode.
! @item -ml
! @opindex ml
! Compile code for the processor in little endian mode.
! @item -mdalign
! @opindex mdalign
! Align doubles at 64-bit boundaries. Note that this changes the calling
! conventions, and thus some functions from the standard C library will
! not work unless you recompile it first with @option{-mdalign}.
! @item -mrelax
! @opindex mrelax
! Shorten some address references at link time, when possible; uses the
! linker option @option{-relax}.
! @item -mbigtable
! @opindex mbigtable
! Use 32-bit offsets in @code{switch} tables. The default is to use
! 16-bit offsets.
! @item -mfmovd
! @opindex mfmovd
! Enable the use of the instruction @code{fmovd}.
! @item -mhitachi
! @opindex mhitachi
! Comply with the calling conventions defined by Renesas.
! @item -mnomacsave
! @opindex mnomacsave
! Mark the @code{MAC} register as call-clobbered, even if
! @option{-mhitachi} is given.
! @item -mieee
! @opindex mieee
! Increase IEEE-compliance of floating-point code.
! @item -misize
! @opindex misize
! Dump instruction size and location in the assembly code.
! @item -mpadstruct
! @opindex mpadstruct
! This option is deprecated. It pads structures to multiple of 4 bytes,
! which is incompatible with the SH ABI@.
! @item -mspace
! @opindex mspace
! Optimize for space instead of speed. Implied by @option{-Os}.
! @item -mprefergot
! @opindex mprefergot
! When generating position-independent code, emit function calls using
! the Global Offset Table instead of the Procedure Linkage Table.
! @item -musermode
! @opindex musermode
! Generate a library function call to invalidate instruction cache
! entries, after fixing up a trampoline. This library function call
! doesn't assume it can write to the whole memory address space. This
! is the default when the target is @code{sh-*-linux*}.
@end table
! @node SPARC Options
! @subsection SPARC Options
! @cindex SPARC options
! These @samp{-m} options are supported on the SPARC:
@table @gcctabopt
! @item -mno-app-regs
! @itemx -mapp-regs
! @opindex mno-app-regs
! @opindex mapp-regs
! Specify @option{-mapp-regs} to generate output using the global registers
! 2 through 4, which the SPARC SVR4 ABI reserves for applications. This
! is the default.
! To be fully SVR4 ABI compliant at the cost of some performance loss,
! specify @option{-mno-app-regs}. You should compile libraries and system
! software with this option.
! @item -mfpu
! @itemx -mhard-float
! @opindex mfpu
! @opindex mhard-float
! Generate output containing floating point instructions. This is the
! default.
! @item -mno-fpu
! @itemx -msoft-float
! @opindex mno-fpu
! @opindex msoft-float
! Generate output containing library calls for floating point.
! @strong{Warning:} the requisite libraries are not available for all SPARC
! targets. Normally the facilities of the machine's usual C compiler are
! used, but this cannot be done directly in cross-compilation. You must make
! your own arrangements to provide suitable library functions for
! cross-compilation. The embedded targets @samp{sparc-*-aout} and
! @samp{sparclite-*-*} do provide software floating point support.
! @option{-msoft-float} changes the calling convention in the output file;
! therefore, it is only useful if you compile @emph{all} of a program with
! this option. In particular, you need to compile @file{libgcc.a}, the
! library that comes with GCC, with @option{-msoft-float} in order for
! this to work.
! @item -mhard-quad-float
! @opindex mhard-quad-float
! Generate output containing quad-word (long double) floating point
! instructions.
! @item -msoft-quad-float
! @opindex msoft-quad-float
! Generate output containing library calls for quad-word (long double)
! floating point instructions. The functions called are those specified
! in the SPARC ABI@. This is the default.
! As of this writing, there are no SPARC implementations that have hardware
! support for the quad-word floating point instructions. They all invoke
! a trap handler for one of these instructions, and then the trap handler
! emulates the effect of the instruction. Because of the trap handler overhead,
! this is much slower than calling the ABI library routines. Thus the
! @option{-msoft-quad-float} option is the default.
! @item -mno-unaligned-doubles
! @itemx -munaligned-doubles
! @opindex mno-unaligned-doubles
! @opindex munaligned-doubles
! Assume that doubles have 8 byte alignment. This is the default.
! With @option{-munaligned-doubles}, GCC assumes that doubles have 8 byte
! alignment only if they are contained in another type, or if they have an
! absolute address. Otherwise, it assumes they have 4 byte alignment.
! Specifying this option avoids some rare compatibility problems with code
! generated by other compilers. It is not the default because it results
! in a performance loss, especially for floating point code.
! @item -mno-faster-structs
! @itemx -mfaster-structs
! @opindex mno-faster-structs
! @opindex mfaster-structs
! With @option{-mfaster-structs}, the compiler assumes that structures
! should have 8 byte alignment. This enables the use of pairs of
! @code{ldd} and @code{std} instructions for copies in structure
! assignment, in place of twice as many @code{ld} and @code{st} pairs.
! However, the use of this changed alignment directly violates the SPARC
! ABI@. Thus, it's intended only for use on targets where the developer
! acknowledges that their resulting code will not be directly in line with
! the rules of the ABI@.
! @item -mimpure-text
! @opindex mimpure-text
! @option{-mimpure-text}, used in addition to @option{-shared}, tells
! the compiler to not pass @option{-z text} to the linker when linking a
! shared object. Using this option, you can link position-dependent
! code into a shared object.
! @option{-mimpure-text} suppresses the ``relocations remain against
! allocatable but non-writable sections'' linker error message.
! However, the necessary relocations will trigger copy-on-write, and the
! shared object is not actually shared across processes. Instead of
! using @option{-mimpure-text}, you should compile all source code with
! @option{-fpic} or @option{-fPIC}.
!
! This option is only available on SunOS and Solaris.
!
! @item -mcpu=@var{cpu_type}
! @opindex mcpu
! Set the instruction set, register set, and instruction scheduling parameters
! for machine type @var{cpu_type}. Supported values for @var{cpu_type} are
! @samp{v7}, @samp{cypress}, @samp{v8}, @samp{supersparc}, @samp{sparclite},
! @samp{f930}, @samp{f934}, @samp{hypersparc}, @samp{sparclite86x},
! @samp{sparclet}, @samp{tsc701}, @samp{v9}, @samp{ultrasparc}, and
! @samp{ultrasparc3}.
! Default instruction scheduling parameters are used for values that select
! an architecture and not an implementation. These are @samp{v7}, @samp{v8},
! @samp{sparclite}, @samp{sparclet}, @samp{v9}.
! Here is a list of each supported architecture and their supported
! implementations.
! @smallexample
! v7: cypress
! v8: supersparc, hypersparc
! sparclite: f930, f934, sparclite86x
! sparclet: tsc701
! v9: ultrasparc, ultrasparc3
! @end smallexample
! By default (unless configured otherwise), GCC generates code for the V7
! variant of the SPARC architecture. With @option{-mcpu=cypress}, the compiler
! additionally optimizes it for the Cypress CY7C602 chip, as used in the
! SPARCStation/SPARCServer 3xx series. This is also appropriate for the older
! SPARCStation 1, 2, IPX etc.
! With @option{-mcpu=v8}, GCC generates code for the V8 variant of the SPARC
! architecture. The only difference from V7 code is that the compiler emits
! the integer multiply and integer divide instructions which exist in SPARC-V8
! but not in SPARC-V7. With @option{-mcpu=supersparc}, the compiler additionally
! optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and
! 2000 series.
! With @option{-mcpu=sparclite}, GCC generates code for the SPARClite variant of
! the SPARC architecture. This adds the integer multiply, integer divide step
! and scan (@code{ffs}) instructions which exist in SPARClite but not in SPARC-V7.
! With @option{-mcpu=f930}, the compiler additionally optimizes it for the
! Fujitsu MB86930 chip, which is the original SPARClite, with no FPU. With
! @option{-mcpu=f934}, the compiler additionally optimizes it for the Fujitsu
! MB86934 chip, which is the more recent SPARClite with FPU.
! With @option{-mcpu=sparclet}, GCC generates code for the SPARClet variant of
! the SPARC architecture. This adds the integer multiply, multiply/accumulate,
! integer divide step and scan (@code{ffs}) instructions which exist in SPARClet
! but not in SPARC-V7. With @option{-mcpu=tsc701}, the compiler additionally
! optimizes it for the TEMIC SPARClet chip.
! With @option{-mcpu=v9}, GCC generates code for the V9 variant of the SPARC
! architecture. This adds 64-bit integer and floating-point move instructions,
! 3 additional floating-point condition code registers and conditional move
! instructions. With @option{-mcpu=ultrasparc}, the compiler additionally
! optimizes it for the Sun UltraSPARC I/II chips. With
! @option{-mcpu=ultrasparc3}, the compiler additionally optimizes it for the
! Sun UltraSPARC III chip.
! @item -mtune=@var{cpu_type}
! @opindex mtune
! Set the instruction scheduling parameters for machine type
! @var{cpu_type}, but do not set the instruction set or register set that the
! option @option{-mcpu=@var{cpu_type}} would.
! The same values for @option{-mcpu=@var{cpu_type}} can be used for
! @option{-mtune=@var{cpu_type}}, but the only useful values are those
! that select a particular cpu implementation. Those are @samp{cypress},
! @samp{supersparc}, @samp{hypersparc}, @samp{f930}, @samp{f934},
! @samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc}, and
! @samp{ultrasparc3}.
! @item -mv8plus
! @itemx -mno-v8plus
! @opindex mv8plus
! @opindex mno-v8plus
! With @option{-mv8plus}, GCC generates code for the SPARC-V8+ ABI. The
! difference from the V8 ABI is that the global and out registers are
! considered 64-bit wide. This is enabled by default on Solaris in 32-bit
! mode for all SPARC-V9 processors.
! @item -mvis
! @itemx -mno-vis
! @opindex mvis
! @opindex mno-vis
! With @option{-mvis}, GCC generates code that takes advantage of the UltraSPARC
! Visual Instruction Set extensions. The default is @option{-mno-vis}.
! @end table
! These @samp{-m} options are supported in addition to the above
! on SPARC-V9 processors in 64-bit environments:
! @table @gcctabopt
! @item -mlittle-endian
! @opindex mlittle-endian
! Generate code for a processor running in little-endian mode. It is only
! available for a few configurations and most notably not on Solaris.
! @item -m32
! @itemx -m64
! @opindex m32
! @opindex m64
! Generate code for a 32-bit or 64-bit environment.
! The 32-bit environment sets int, long and pointer to 32 bits.
! The 64-bit environment sets int to 32 bits and long and pointer
! to 64 bits.
! @item -mcmodel=medlow
! @opindex mcmodel=medlow
! Generate code for the Medium/Low code model: 64-bit addresses, programs
! must be linked in the low 32 bits of memory. Programs can be statically
! or dynamically linked.
! @item -mcmodel=medmid
! @opindex mcmodel=medmid
! Generate code for the Medium/Middle code model: 64-bit addresses, programs
! must be linked in the low 44 bits of memory, the text and data segments must
! be less than 2GB in size and the data segment must be located within 2GB of
! the text segment.
! @item -mcmodel=medany
! @opindex mcmodel=medany
! Generate code for the Medium/Anywhere code model: 64-bit addresses, programs
! may be linked anywhere in memory, the text and data segments must be less
! than 2GB in size and the data segment must be located within 2GB of the
! text segment.
! @item -mcmodel=embmedany
! @opindex mcmodel=embmedany
! Generate code for the Medium/Anywhere code model for embedded systems:
! 64-bit addresses, the text and data segments must be less than 2GB in
! size, both starting anywhere in memory (determined at link time). The
! global register %g4 points to the base of the data segment. Programs
! are statically linked and PIC is not supported.
! @item -mstack-bias
! @itemx -mno-stack-bias
! @opindex mstack-bias
! @opindex mno-stack-bias
! With @option{-mstack-bias}, GCC assumes that the stack pointer, and
! frame pointer if present, are offset by @minus{}2047 which must be added back
! when making stack frame references. This is the default in 64-bit mode.
! Otherwise, assume no such offset is present.
! @end table
! @node System V Options
! @subsection Options for System V
! These additional options are available on System V Release 4 for
! compatibility with other compilers on those systems:
! @table @gcctabopt
! @item -G
! @opindex G
! Create a shared object.
! It is recommended that @option{-symbolic} or @option{-shared} be used instead.
! @item -Qy
! @opindex Qy
! Identify the versions of each tool used by the compiler, in a
! @code{.ident} assembler directive in the output.
! @item -Qn
! @opindex Qn
! Refrain from adding @code{.ident} directives to the output file (this is
! the default).
! @item -YP,@var{dirs}
! @opindex YP
! Search the directories @var{dirs}, and no others, for libraries
! specified with @option{-l}.
! @item -Ym,@var{dir}
! @opindex Ym
! Look in the directory @var{dir} to find the M4 preprocessor.
! The assembler uses this option.
! @c This is supposed to go with a -Yd for predefined M4 macro files, but
! @c the generic assembler that comes with Solaris takes just -Ym.
! @end table
! @node TMS320C3x/C4x Options
! @subsection TMS320C3x/C4x Options
! @cindex TMS320C3x/C4x Options
! These @samp{-m} options are defined for TMS320C3x/C4x implementations:
! @table @gcctabopt
! @item -mcpu=@var{cpu_type}
! @opindex mcpu
! Set the instruction set, register set, and instruction scheduling
! parameters for machine type @var{cpu_type}. Supported values for
! @var{cpu_type} are @samp{c30}, @samp{c31}, @samp{c32}, @samp{c40}, and
! @samp{c44}. The default is @samp{c40} to generate code for the
! TMS320C40.
! @item -mbig-memory
! @itemx -mbig
! @itemx -msmall-memory
! @itemx -msmall
! @opindex mbig-memory
! @opindex mbig
! @opindex msmall-memory
! @opindex msmall
! Generates code for the big or small memory model. The small memory
! model assumed that all data fits into one 64K word page. At run-time
! the data page (DP) register must be set to point to the 64K page
! containing the .bss and .data program sections. The big memory model is
! the default and requires reloading of the DP register for every direct
! memory access.
! @item -mbk
! @itemx -mno-bk
! @opindex mbk
! @opindex mno-bk
! Allow (disallow) allocation of general integer operands into the block
! count register BK@.
! @item -mdb
! @itemx -mno-db
! @opindex mdb
! @opindex mno-db
! Enable (disable) generation of code using decrement and branch,
! DBcond(D), instructions. This is enabled by default for the C4x. To be
! on the safe side, this is disabled for the C3x, since the maximum
! iteration count on the C3x is @math{2^{23} + 1} (but who iterates loops more than
! @math{2^{23}} times on the C3x?). Note that GCC will try to reverse a loop so
! that it can utilize the decrement and branch instruction, but will give
! up if there is more than one memory reference in the loop. Thus a loop
! where the loop counter is decremented can generate slightly more
! efficient code, in cases where the RPTB instruction cannot be utilized.
! @item -mdp-isr-reload
! @itemx -mparanoid
! @opindex mdp-isr-reload
! @opindex mparanoid
! Force the DP register to be saved on entry to an interrupt service
! routine (ISR), reloaded to point to the data section, and restored on
! exit from the ISR@. This should not be required unless someone has
! violated the small memory model by modifying the DP register, say within
! an object library.
! @item -mmpyi
! @itemx -mno-mpyi
! @opindex mmpyi
! @opindex mno-mpyi
! For the C3x use the 24-bit MPYI instruction for integer multiplies
! instead of a library call to guarantee 32-bit results. Note that if one
! of the operands is a constant, then the multiplication will be performed
! using shifts and adds. If the @option{-mmpyi} option is not specified for the C3x,
! then squaring operations are performed inline instead of a library call.
! @item -mfast-fix
! @itemx -mno-fast-fix
! @opindex mfast-fix
! @opindex mno-fast-fix
! The C3x/C4x FIX instruction to convert a floating point value to an
! integer value chooses the nearest integer less than or equal to the
! floating point value rather than to the nearest integer. Thus if the
! floating point number is negative, the result will be incorrectly
! truncated an additional code is necessary to detect and correct this
! case. This option can be used to disable generation of the additional
! code required to correct the result.
! @item -mrptb
! @itemx -mno-rptb
! @opindex mrptb
! @opindex mno-rptb
! Enable (disable) generation of repeat block sequences using the RPTB
! instruction for zero overhead looping. The RPTB construct is only used
! for innermost loops that do not call functions or jump across the loop
! boundaries. There is no advantage having nested RPTB loops due to the
! overhead required to save and restore the RC, RS, and RE registers.
! This is enabled by default with @option{-O2}.
! @item -mrpts=@var{count}
! @itemx -mno-rpts
! @opindex mrpts
! @opindex mno-rpts
! Enable (disable) the use of the single instruction repeat instruction
! RPTS@. If a repeat block contains a single instruction, and the loop
! count can be guaranteed to be less than the value @var{count}, GCC will
! emit a RPTS instruction instead of a RPTB@. If no value is specified,
! then a RPTS will be emitted even if the loop count cannot be determined
! at compile time. Note that the repeated instruction following RPTS does
! not have to be reloaded from memory each iteration, thus freeing up the
! CPU buses for operands. However, since interrupts are blocked by this
! instruction, it is disabled by default.
! @item -mloop-unsigned
! @itemx -mno-loop-unsigned
! @opindex mloop-unsigned
! @opindex mno-loop-unsigned
! The maximum iteration count when using RPTS and RPTB (and DB on the C40)
! is @math{2^{31} + 1} since these instructions test if the iteration count is
! negative to terminate the loop. If the iteration count is unsigned
! there is a possibility than the @math{2^{31} + 1} maximum iteration count may be
! exceeded. This switch allows an unsigned iteration count.
! @item -mti
! @opindex mti
! Try to emit an assembler syntax that the TI assembler (asm30) is happy
! with. This also enforces compatibility with the API employed by the TI
! C3x C compiler. For example, long doubles are passed as structures
! rather than in floating point registers.
! @item -mregparm
! @itemx -mmemparm
! @opindex mregparm
! @opindex mmemparm
! Generate code that uses registers (stack) for passing arguments to functions.
! By default, arguments are passed in registers where possible rather
! than by pushing arguments on to the stack.
! @item -mparallel-insns
! @itemx -mno-parallel-insns
! @opindex mparallel-insns
! @opindex mno-parallel-insns
! Allow the generation of parallel instructions. This is enabled by
! default with @option{-O2}.
! @item -mparallel-mpy
! @itemx -mno-parallel-mpy
! @opindex mparallel-mpy
! @opindex mno-parallel-mpy
! Allow the generation of MPY||ADD and MPY||SUB parallel instructions,
! provided @option{-mparallel-insns} is also specified. These instructions have
! tight register constraints which can pessimize the code generation
! of large functions.
! @end table
! @node V850 Options
! @subsection V850 Options
! @cindex V850 Options
! These @samp{-m} options are defined for V850 implementations:
! @table @gcctabopt
! @item -mlong-calls
! @itemx -mno-long-calls
! @opindex mlong-calls
! @opindex mno-long-calls
! Treat all calls as being far away (near). If calls are assumed to be
! far away, the compiler will always load the functions address up into a
! register, and call indirect through the pointer.
! @item -mno-ep
! @itemx -mep
! @opindex mno-ep
! @opindex mep
! Do not optimize (do optimize) basic blocks that use the same index
! pointer 4 or more times to copy pointer into the @code{ep} register, and
! use the shorter @code{sld} and @code{sst} instructions. The @option{-mep}
! option is on by default if you optimize.
! @item -mno-prolog-function
! @itemx -mprolog-function
! @opindex mno-prolog-function
! @opindex mprolog-function
! Do not use (do use) external functions to save and restore registers
! at the prologue and epilogue of a function. The external functions
! are slower, but use less code space if more than one function saves
! the same number of registers. The @option{-mprolog-function} option
! is on by default if you optimize.
! @item -mspace
! @opindex mspace
! Try to make the code as small as possible. At present, this just turns
! on the @option{-mep} and @option{-mprolog-function} options.
! @item -mtda=@var{n}
! @opindex mtda
! Put static or global variables whose size is @var{n} bytes or less into
! the tiny data area that register @code{ep} points to. The tiny data
! area can hold up to 256 bytes in total (128 bytes for byte references).
! @item -msda=@var{n}
! @opindex msda
! Put static or global variables whose size is @var{n} bytes or less into
! the small data area that register @code{gp} points to. The small data
! area can hold up to 64 kilobytes.
! @item -mzda=@var{n}
! @opindex mzda
! Put static or global variables whose size is @var{n} bytes or less into
! the first 32 kilobytes of memory.
! @item -mv850
! @opindex mv850
! Specify that the target processor is the V850.
! @item -mbig-switch
! @opindex mbig-switch
! Generate code suitable for big switch tables. Use this option only if
! the assembler/linker complain about out of range branches within a switch
! table.
! @item -mapp-regs
! @opindex mapp-regs
! This option will cause r2 and r5 to be used in the code generated by
! the compiler. This setting is the default.
! @item -mno-app-regs
! @opindex mno-app-regs
! This option will cause r2 and r5 to be treated as fixed registers.
! @item -mv850e1
! @opindex mv850e1
! Specify that the target processor is the V850E1. The preprocessor
! constants @samp{__v850e1__} and @samp{__v850e__} will be defined if
! this option is used.
! @item -mv850e
! @opindex mv850e
! Specify that the target processor is the V850E. The preprocessor
! constant @samp{__v850e__} will be defined if this option is used.
! If neither @option{-mv850} nor @option{-mv850e} nor @option{-mv850e1}
! are defined then a default target processor will be chosen and the
! relevant @samp{__v850*__} preprocessor constant will be defined.
! The preprocessor constants @samp{__v850} and @samp{__v851__} are always
! defined, regardless of which processor variant is the target.
! @item -mdisable-callt
! @opindex mdisable-callt
! This option will suppress generation of the CALLT instruction for the
! v850e and v850e1 flavors of the v850 architecture. The default is
! @option{-mno-disable-callt} which allows the CALLT instruction to be used.
! @end table
! @node VAX Options
! @subsection VAX Options
! @cindex VAX options
! These @samp{-m} options are defined for the VAX:
! @table @gcctabopt
! @item -munix
! @opindex munix
! Do not output certain jump instructions (@code{aobleq} and so on)
! that the Unix assembler for the VAX cannot handle across long
! ranges.
! @item -mgnu
! @opindex mgnu
! Do output those jump instructions, on the assumption that you
! will assemble with the GNU assembler.
! @item -mg
! @opindex mg
! Output code for g-format floating point numbers instead of d-format.
! @end table
! @node x86-64 Options
! @subsection x86-64 Options
! @cindex x86-64 options
! These are listed under @xref{i386 and x86-64 Options}.
! @node Xstormy16 Options
! @subsection Xstormy16 Options
! @cindex Xstormy16 Options
! These options are defined for Xstormy16:
+ @table @gcctabopt
+ @item -msim
+ @opindex msim
+ Choose startup files and linker script suitable for the simulator.
@end table
@node Xtensa Options
*************** instructions. Note that the assembler w
*** 11144,11149 ****
--- 11157,11168 ----
every cross-file call, not just those that really will be out of range.
@end table
+ @node zSeries Options
+ @subsection zSeries Options
+ @cindex zSeries options
+
+ These are listed under @xref{S/390 and zSeries Options}.
+
@node Code Gen Options
@section Options for Code Generation Conventions
@cindex code generation conventions