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[xtensa] DFA pipeline description
- From: Steven Bosscher <stevenb at suse dot de>
- To: Bob Wilson <bwilson at tensilica dot com>
- Cc: gcc-patches at gcc dot gnu dot org
- Date: Fri, 18 Jun 2004 17:40:24 +0200
- Subject: [xtensa] DFA pipeline description
- Organization: SUSE Labs
Hi,
Does this loop reasonable? The diffs of the old
description compared to the new one are quite large,
but mostly it's just moving instructions with equal
costs to other places. The ones with latencies >1
are still scheduled early, so the code quality should
be the same.
OK for mainline?
Gr.
Steven
* config/xtensa/xtensa.c
(TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE): Define.
* xtensa.md: Replace the old pipeline description with a DFA model.
Index: config/xtensa/xtensa.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/xtensa/xtensa.c,v
retrieving revision 1.57
diff -c -3 -p -r1.57 xtensa.c
*** config/xtensa/xtensa.c 13 May 2004 06:40:09 -0000 1.57
--- config/xtensa/xtensa.c 18 Jun 2004 15:24:49 -0000
*************** static const int reg_nonleaf_alloc_order
*** 259,264 ****
--- 259,267 ----
#undef TARGET_RETURN_IN_MSB
#define TARGET_RETURN_IN_MSB xtensa_return_in_msb
+ #undef TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE
+ #define TARGET_SCHED_USE_DFA_PIPELINE_INTERFACE hook_int_void_1
+
struct gcc_target targetm = TARGET_INITIALIZER;
Index: config/xtensa/xtensa.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/xtensa/xtensa.md,v
retrieving revision 1.19
diff -c -3 -p -r1.19 xtensa.md
*** config/xtensa/xtensa.md 27 Apr 2004 22:47:56 -0000 1.19
--- config/xtensa/xtensa.md 18 Jun 2004 15:24:50 -0000
***************
*** 52,71 ****
[(set_attr "type" "multi")])
! ;; Functional units.
!
! (define_function_unit "memory" 1 0 (eq_attr "type" "load,fload") 2 0)
!
! (define_function_unit "sreg" 1 1 (eq_attr "type" "rsr") 2 0)
!
! (define_function_unit "mul16" 1 0 (eq_attr "type" "mul16") 2 0)
!
! (define_function_unit "mul32" 1 0 (eq_attr "type" "mul32") 2 0)
!
! (define_function_unit "fpmadd" 1 0 (eq_attr "type" "fmadd") 4 0)
!
! (define_function_unit "fpconv" 1 0 (eq_attr "type" "fconv") 2 0)
;; Addition.
--- 52,92 ----
[(set_attr "type" "multi")])
! ;; Pipeline model.
+ ;; The Xtensa basically has simple 5-stage RISC pipeline.
+ ;; Most instructions complete in 1 cycle, and it is OK to assume that
+ ;; everything is fully pipelined. The exceptions have special insn
+ ;; reservations in the pipeline description below. The Xtensa can
+ ;; issue one instruction per cycle, so defining CPU units is unnecessary.
+
+ (define_insn_reservation "xtensa_any_insn" 1
+ (eq_attr "type" "!load,fload,rsr,mul16,mul32,fmadd,fconv")
+ "nothing")
+
+ (define_insn_reservation "xtensa_memory" 2
+ (eq_attr "type" "load,fload")
+ "nothing")
+
+ (define_insn_reservation "xtensa_sreg" 2
+ (eq_attr "type" "rsr")
+ "nothing")
+
+ (define_insn_reservation "xtensa_mul16" 2
+ (eq_attr "type" "mul16")
+ "nothing")
+
+ (define_insn_reservation "xtensa_mul32" 2
+ (eq_attr "type" "mul32")
+ "nothing")
+
+ (define_insn_reservation "xtensa_fmadd" 4
+ (eq_attr "type" "fmadd")
+ "nothing")
+
+ (define_insn_reservation "xtensa_fconv" 2
+ (eq_attr "type" "fconv")
+ "nothing")
;; Addition.