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Re: [m68k] ColdFire V4 patch
>Style: Space before open paren in function calls, brace on own line, no
>old-style decls any more, comments should end with a period.
Here it is again, cleaned up:
This patch adds mov3q, mvs/mvz support for ColdFire V4 cores, updates
MUL costs for V3/V4, uses bitfiled instructions where possible for ColdFire.
Built uberbaum tree with it.
gcc/
2004-06-15 Peter Barada <peter@the-baradas.com>
* config/m68k/m68k.md: (movsi_cfv4): New pattern to allow mov3q.
(movsi_cf): make named, don't match TARGET_CFV4.
(pushexthisi_const): Use mov3q if possible.
(extendhisi2, cvf4_extendhisi2): Split extendhisi2 pattern
to special case mvz.w for ColdFire V4.
(extendqisi2, cvf4_extendqisi2): Split extendhisi2 pattern
to special case mvz.b for ColdFire V4.
(udivmodhi4, divmodhi4): Use mvz to zero extend arg for
divide.
(iorsi3, xorsi3, andsi3): Use bitfiled instructiosn if possible.
* config/m68k/m68k.c(valid_mov3q_const): New function.
(const_method): SWAP is valid for ColdFire.
(MULL_COST, MULW_COST): Fix costs for ColdFire V3/V4.
* config/m68k/m68k-protos.h: Prototype here.
Index: gcc/config/m68k/m68k-protos.h
===================================================================
RCS file: /cvs/uberbaum/gcc/config/m68k/m68k-protos.h,v
retrieving revision 1.14
diff -c -3 -p -r1.14 m68k-protos.h
*** gcc/config/m68k/m68k-protos.h 11 Oct 2003 06:35:53 -0000 1.14
--- gcc/config/m68k/m68k-protos.h 15 Jun 2004 14:25:26 -0000
***************
*** 1,5 ****
/* Definitions of target machine for GNU compiler. Sun 68000/68020 version.
! Copyright (C) 2000, 2002 Free Software Foundation, Inc.
This file is part of GCC.
--- 1,5 ----
/* Definitions of target machine for GNU compiler. Sun 68000/68020 version.
! Copyright (C) 2000, 2002, 2004 Free Software Foundation, Inc.
This file is part of GCC.
*************** Boston, MA 02111-1307, USA. */
*** 23,28 ****
--- 23,29 ----
#ifdef RTX_CODE
extern HOST_WIDE_INT m68k_initial_elimination_offset (int from, int to);
extern const char *output_move_const_into_data_reg (rtx *);
+ extern int valid_mov3q_const (rtx);
extern const char *output_move_simode_const (rtx *);
extern const char *output_move_simode (rtx *);
extern const char *output_move_himode (rtx *);
Index: gcc/config/m68k/m68k.c
===================================================================
RCS file: /cvs/uberbaum/gcc/config/m68k/m68k.c,v
retrieving revision 1.133
diff -c -3 -p -r1.133 m68k.c
*** gcc/config/m68k/m68k.c 1 Jun 2004 13:22:04 -0000 1.133
--- gcc/config/m68k/m68k.c 15 Jun 2004 14:25:27 -0000
*************** const_method (rtx constant)
*** 1447,1458 ****
/* This is the only value where neg.w is useful */
if (i == -65408)
return NEGW;
- /* Try also with swap */
- u = i;
- if (USE_MOVQ ((u >> 16) | (u << 16)))
- return SWAP;
}
if (TARGET_CFV4)
{
/* Try using MVZ/MVS with an immediate value to load constants. */
--- 1447,1459 ----
/* This is the only value where neg.w is useful */
if (i == -65408)
return NEGW;
}
+ /* Try also with swap. */
+ u = i;
+ if (USE_MOVQ ((u >> 16) | (u << 16)))
+ return SWAP;
+
if (TARGET_CFV4)
{
/* Try using MVZ/MVS with an immediate value to load constants. */
*************** m68k_rtx_costs (rtx x, int code, int out
*** 1524,1532 ****
for add and the time for shift, taking away a little more because
sometimes move insns are needed. */
/* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */
! #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : TARGET_CFV3 ? 3 : TARGET_COLDFIRE ? 10 : 13)
#define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : \
! TARGET_CFV3 ? 2 : 5)
#define DIVW_COST (TARGET_68020 ? 27 : TARGET_CF_HWDIV ? 11 : 12)
case PLUS:
--- 1525,1533 ----
for add and the time for shift, taking away a little more because
sometimes move insns are needed. */
/* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS terms. */
! #define MULL_COST (TARGET_68060 ? 2 : TARGET_68040 ? 5 : (TARGET_COLDFIRE && !TARGET_5200) ? 3 : TARGET_COLDFIRE ? 10 : 13)
#define MULW_COST (TARGET_68060 ? 2 : TARGET_68040 ? 3 : TARGET_68020 ? 8 : \
! (TARGET_COLDFIRE && !TARGET_5200) ? 2 : 5)
#define DIVW_COST (TARGET_68020 ? 27 : TARGET_CF_HWDIV ? 11 : 12)
case PLUS:
*************** output_move_const_into_data_reg (rtx *op
*** 1651,1656 ****
--- 1652,1674 ----
}
}
+ /* Return 1 if 'constant' can be represented by
+ mov3q on a ColdFire V4 core. */
+ int
+ valid_mov3q_const (rtx constant)
+ {
+ int i;
+
+ if (TARGET_CFV4 && GET_CODE (constant) == CONST_INT)
+ {
+ i = INTVAL (constant);
+ if ((i == -1) || (i >= 1 && i <= 7))
+ return 1;
+ }
+ return 0;
+ }
+
+
const char *
output_move_simode_const (rtx *operands)
{
*************** output_move_simode_const (rtx *operands)
*** 1663,1668 ****
--- 1681,1689 ----
|| !(GET_CODE (operands[0]) == MEM
&& MEM_VOLATILE_P (operands[0]))))
return "clr%.l %0";
+ else if ((GET_MODE (operands[0]) == SImode)
+ && valid_mov3q_const (operands[1]))
+ return "mov3q%.l %1,%0";
else if (operands[1] == const0_rtx
&& ADDRESS_REG_P (operands[0]))
return "sub%.l %0,%0";
*************** output_move_simode_const (rtx *operands)
*** 1671,1683 ****
else if (ADDRESS_REG_P (operands[0])
&& INTVAL (operands[1]) < 0x8000
&& INTVAL (operands[1]) >= -0x8000)
! return "move%.w %1,%0";
else if (GET_CODE (operands[0]) == MEM
&& GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
&& REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
&& INTVAL (operands[1]) < 0x8000
&& INTVAL (operands[1]) >= -0x8000)
! return "pea %a1";
return "move%.l %1,%0";
}
--- 1692,1712 ----
else if (ADDRESS_REG_P (operands[0])
&& INTVAL (operands[1]) < 0x8000
&& INTVAL (operands[1]) >= -0x8000)
! {
! if (valid_mov3q_const (operands[1]))
! return "mov3q%.l %1,%0";
! return "move%.w %1,%0";
! }
else if (GET_CODE (operands[0]) == MEM
&& GET_CODE (XEXP (operands[0], 0)) == PRE_DEC
&& REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM
&& INTVAL (operands[1]) < 0x8000
&& INTVAL (operands[1]) >= -0x8000)
! {
! if (valid_mov3q_const (operands[1]))
! return "mov3q%.l %1,%-";
! return "pea %a1";
! }
return "move%.l %1,%0";
}
Index: gcc/config/m68k/m68k.md
===================================================================
RCS file: /cvs/uberbaum/gcc/config/m68k/m68k.md,v
retrieving revision 1.76
diff -c -3 -p -r1.76 m68k.md
*** gcc/config/m68k/m68k.md 29 May 2004 15:10:41 -0000 1.76
--- gcc/config/m68k/m68k.md 15 Jun 2004 14:25:27 -0000
***************
*** 587,592 ****
--- 587,594 ----
{
if (operands[1] == const0_rtx)
return "clr%.l %0";
+ if (valid_mov3q_const(operands[1]))
+ return "mov3q%.l %1,%-";
return "pea %a1";
})
***************
*** 675,684 ****
return output_move_simode (operands);
})
! (define_insn ""
[(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g,U")
(match_operand:SI 1 "general_operand" "g,r<Q>,U"))]
! "TARGET_COLDFIRE"
"* return output_move_simode (operands);")
;; Special case of fullword move, where we need to get a non-GOT PIC
--- 677,692 ----
return output_move_simode (operands);
})
! (define_insn "movsi_cf"
[(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g,U")
(match_operand:SI 1 "general_operand" "g,r<Q>,U"))]
! "TARGET_COLDFIRE && !TARGET_CFV4"
! "* return output_move_simode (operands);")
!
! (define_insn "movsi_cfv4"
! [(set (match_operand:SI 0 "nonimmediate_operand" "=r<Q>,g,U")
! (match_operand:SI 1 "general_operand" "Rg,Rr<Q>,U"))]
! "TARGET_CFV4"
"* return output_move_simode (operands);")
;; Special case of fullword move, where we need to get a non-GOT PIC
***************
*** 1250,1255 ****
--- 1258,1265 ----
{
if (DATA_REG_P (operands[0]))
{
+ if (TARGET_CFV4)
+ return "mvz%.w %1,%0";
if (GET_CODE (operands[1]) == REG
&& REGNO (operands[0]) == REGNO (operands[1]))
return "and%.l #0xFFFF,%0";
***************
*** 1280,1289 ****
{
if (GET_CODE (operands[1]) == REG
&& REGNO (operands[0]) == REGNO (operands[1]))
! return (!TARGET_COLDFIRE ? "and%.w #0xFF,%0" : "and%.l #0xFF,%0");
if (reg_mentioned_p (operands[0], operands[1]))
! return (!TARGET_COLDFIRE ? "move%.b %1,%0\;and%.w #0xFF,%0"
! : "move%.b %1,%0\;and%.l #0xFF,%0");
return "clr%.w %0\;move%.b %1,%0";
}
else if (GET_CODE (operands[0]) == MEM
--- 1290,1307 ----
{
if (GET_CODE (operands[1]) == REG
&& REGNO (operands[0]) == REGNO (operands[1]))
! {
! if (TARGET_CFV4)
! return "mvz%.b %0,%0";
! return (!TARGET_COLDFIRE ? "and%.w #0xFF,%0" : "and%.l #0xFF,%0");
! }
if (reg_mentioned_p (operands[0], operands[1]))
! {
! if (TARGET_CFV4)
! return "mvz%.b %1,%0";
! return (!TARGET_COLDFIRE ? "move%.b %1,%0\;and%.w #0xFF,%0"
! : "move%.b %1,%0\;and%.l #0xFF,%0");
! }
return "clr%.w %0\;move%.b %1,%0";
}
else if (GET_CODE (operands[0]) == MEM
***************
*** 1318,1323 ****
--- 1336,1343 ----
{
if (DATA_REG_P (operands[0]))
{
+ if (TARGET_CFV4)
+ return "mvz%.b %1,%0";
if (GET_CODE (operands[1]) == REG
&& REGNO (operands[0]) == REGNO (operands[1]))
return "and%.l #0xFF,%0";
***************
*** 1358,1363 ****
--- 1378,1385 ----
{
CC_STATUS_INIT;
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
+ if (TARGET_CFV4)
+ return "mvs%.b %1,%2\;smi %0\;extb%.l %0";
if (TARGET_68020 || TARGET_COLDFIRE)
return "move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0";
else
***************
*** 1372,1377 ****
--- 1394,1401 ----
{
CC_STATUS_INIT;
operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
+ if (TARGET_CFV4)
+ return "mvs%.w %1,%2\;smi %0\;extb%.l %0";
if (TARGET_68020 || TARGET_COLDFIRE)
return "move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0";
else
***************
*** 1423,1433 ****
return "smi %0\;ext%.w %0\;ext%.l %0";
})
! (define_insn "extendhisi2"
[(set (match_operand:SI 0 "nonimmediate_operand" "=*d,a")
(sign_extend:SI
(match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))]
! ""
{
if (ADDRESS_REG_P (operands[0]))
return "move%.w %1,%0";
--- 1447,1471 ----
return "smi %0\;ext%.w %0\;ext%.l %0";
})
! (define_expand "extendhisi2"
! [(set (match_operand:SI 0 "nonimmediate_operand" "")
! (sign_extend:SI
! (match_operand:HI 1 "nonimmediate_src_operand" "")))]
! ""
! "")
!
! (define_insn "cfv4_extendhisi2"
! [(set (match_operand:SI 0 "nonimmediate_operand" "=d")
! (sign_extend:SI
! (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))]
! "TARGET_CFV4"
! "mvs%.w %1,%0")
!
! (define_insn "68k_extendhisi2"
[(set (match_operand:SI 0 "nonimmediate_operand" "=*d,a")
(sign_extend:SI
(match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))]
! "!TARGET_CFV4"
{
if (ADDRESS_REG_P (operands[0]))
return "move%.w %1,%0";
***************
*** 1440,1449 ****
""
"ext%.w %0")
! (define_insn "extendqisi2"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
! "TARGET_68020 || TARGET_COLDFIRE"
"extb%.l %0")
;; Conversions between float and double.
--- 1478,1499 ----
""
"ext%.w %0")
! (define_expand "extendqisi2"
! [(set (match_operand:SI 0 "nonimmediate_operand" "")
! (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))]
! "TARGET_68020 || TARGET_COLDFIRE"
! "")
!
! (define_insn "cfv4_extendqisi2"
! [(set (match_operand:SI 0 "general_operand" "=d")
! (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rms")))]
! "TARGET_CFV4"
! "mvs%.b %1,%0")
!
! (define_insn "m68k_extendqisi2"
[(set (match_operand:SI 0 "nonimmediate_operand" "=d")
(sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
! "TARGET_68020 || (TARGET_COLDFIRE && !TARGET_CFV4)"
"extb%.l %0")
;; Conversions between float and double.
***************
*** 2985,2994 ****
(umod:HI (match_dup 1) (match_dup 2)))]
"!TARGET_COLDFIRE || TARGET_CF_HWDIV"
{
! output_asm_insn (MOTOROLA ?
! "and%.l #0xFFFF,%0\;divu%.w %2,%0" :
! "and%.l #0xFFFF,%0\;divu %2,%0",
! operands);
if (!find_reg_note(insn, REG_UNUSED, operands[3]))
{
CC_STATUS_INIT;
--- 3035,3051 ----
(umod:HI (match_dup 1) (match_dup 2)))]
"!TARGET_COLDFIRE || TARGET_CF_HWDIV"
{
! if (TARGET_CFV4)
! output_asm_insn (MOTOROLA ?
! "mvz%.w %0,%0\;divu%.w %2,%0" :
! "mvz%.w %0,%0\;divu %2,%0",
! operands);
! else
! output_asm_insn (MOTOROLA ?
! "and%.l #0xFFFF,%0\;divu%.w %2,%0" :
! "and%.l #0xFFFF,%0\;divu %2,%0",
! operands);
!
if (!find_reg_note(insn, REG_UNUSED, operands[3]))
{
CC_STATUS_INIT;
***************
*** 3091,3097 ****
(and:SI (match_operand:SI 1 "general_operand" "%0,0")
(match_operand:SI 2 "general_src_operand" "d,dmsK")))]
"TARGET_COLDFIRE"
! "and%.l %2,%0")
(define_insn "andhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
--- 3148,3164 ----
(and:SI (match_operand:SI 1 "general_operand" "%0,0")
(match_operand:SI 2 "general_src_operand" "d,dmsK")))]
"TARGET_COLDFIRE"
! {
! if (TARGET_CFV4 && DATA_REG_P (operands[0])
! && GET_CODE (operands[2]) == CONST_INT)
! {
! if (INTVAL (operands[2]) == 0x000000ff)
! return \"mvz%.b %0,%0\";
! else if (INTVAL (operands[2]) == 0x0000ffff)
! return \"mvz%.w %0,%0\";
! }
! return output_andsi3 (operands);
! })
(define_insn "andhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
***************
*** 3253,3259 ****
(ior:SI (match_operand:SI 1 "general_operand" "%0,0")
(match_operand:SI 2 "general_src_operand" "d,dmsK")))]
"TARGET_COLDFIRE"
! "or%.l %2,%0")
(define_insn "iorhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
--- 3320,3328 ----
(ior:SI (match_operand:SI 1 "general_operand" "%0,0")
(match_operand:SI 2 "general_src_operand" "d,dmsK")))]
"TARGET_COLDFIRE"
! {
! return output_iorsi3 (operands);
! })
(define_insn "iorhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "=m,d")
***************
*** 3432,3438 ****
(xor:SI (match_operand:SI 1 "general_operand" "%0,0")
(match_operand:SI 2 "general_operand" "d,Ks")))]
"TARGET_COLDFIRE"
! "eor%.l %2,%0")
(define_insn "xorhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "=dm")
--- 3501,3509 ----
(xor:SI (match_operand:SI 1 "general_operand" "%0,0")
(match_operand:SI 2 "general_operand" "d,Ks")))]
"TARGET_COLDFIRE"
! {
! return output_xorsi3 (operands);
! })
(define_insn "xorhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "=dm")