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[committed] Don't generated indexed stores when indexing is disabled on PA

From: "John David Anglin" <dave at hiauly1 dot hia dot nrc dot ca>
To: gcc-patches at gcc dot gnu dot org
Date: Mon, 31 May 2004 12:21:44 -0400 (EDT)
Subject: [committed] Don't generated indexed stores when indexing is disabled on PA
The following patch fixes a few testsuite fails on hppa64-hp-hpux11.11.
For some reasone when I added these peephole2 patterns, I thought they
wouldn't match when indexing was disabled.  In any case, it is better
to just disable them when indexing is disabled.

Tested with a build and check on hppa64-hp-hpux11.11 on 3.5.

Dave
-- 
J. David Anglin                                  dave.anglin@nrc-cnrc.gc.ca
National Research Council of Canada              (613) 990-0752 (FAX: 952-6602)

2004-05-31  John David Anglin  <dave.anglin@nrc-cnrc.gc.ca>

	* pa.md: Disable the peephole2 patterns that generate indexed
	floating-point stores when indexing is disabled.

Index: config/pa/pa.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/pa/pa.md,v
retrieving revision 1.147
diff -u -3 -p -r1.147 pa.md
--- config/pa/pa.md	17 May 2004 03:01:23 -0000	1.147
+++ config/pa/pa.md	31 May 2004 15:34:25 -0000
@@ -2308,6 +2308,7 @@
    (set (mem:SI (match_dup 0))
         (match_operand:SI 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && REG_OK_FOR_BASE_P (operands[2])
    && FP_REGNO_P (REGNO (operands[3]))"
   [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
@@ -2324,6 +2325,7 @@
    (set (mem:SI (match_dup 0))
         (match_operand:SI 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && REG_OK_FOR_BASE_P (operands[2])
    && FP_REGNO_P (REGNO (operands[3]))"
   [(set (mem:SI (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
@@ -2340,6 +2342,7 @@
    (set (mem:SI (match_dup 0))
         (match_operand:SI 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && TARGET_64BIT
    && REG_OK_FOR_BASE_P (operands[2])
    && FP_REGNO_P (REGNO (operands[3]))"
@@ -2357,6 +2360,7 @@
    (set (mem:SI (match_dup 0))
         (match_operand:SI 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && TARGET_64BIT
    && REG_OK_FOR_BASE_P (operands[2])
    && FP_REGNO_P (REGNO (operands[3]))"
@@ -2373,6 +2377,7 @@
    (set (mem:SI (match_dup 0))
         (match_operand:SI 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && REG_OK_FOR_BASE_P (operands[1])
    && (TARGET_NO_SPACE_REGS
        || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
@@ -2389,6 +2394,7 @@
    (set (mem:SI (match_dup 0))
         (match_operand:SI 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && REG_OK_FOR_BASE_P (operands[2])
    && (TARGET_NO_SPACE_REGS
        || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
@@ -2405,6 +2411,7 @@
    (set (mem:SI (match_dup 0))
         (match_operand:SI 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && TARGET_64BIT
    && REG_OK_FOR_BASE_P (operands[1])
    && (TARGET_NO_SPACE_REGS
@@ -2422,6 +2429,7 @@
    (set (mem:SI (match_dup 0))
         (match_operand:SI 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && TARGET_64BIT
    && REG_OK_FOR_BASE_P (operands[2])
    && (TARGET_NO_SPACE_REGS
@@ -3818,6 +3826,7 @@
    (set (mem:DF (match_dup 0))
         (match_operand:DF 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && REG_OK_FOR_BASE_P (operands[2])
    && FP_REGNO_P (REGNO (operands[3]))"
   [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
@@ -3834,6 +3843,7 @@
    (set (mem:DF (match_dup 0))
         (match_operand:DF 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && REG_OK_FOR_BASE_P (operands[2])
    && FP_REGNO_P (REGNO (operands[3]))"
   [(set (mem:DF (plus:SI (mult:SI (match_dup 1) (const_int 8)) (match_dup 2)))
@@ -3850,6 +3860,7 @@
    (set (mem:DF (match_dup 0))
         (match_operand:DF 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && TARGET_64BIT
    && REG_OK_FOR_BASE_P (operands[2])
    && FP_REGNO_P (REGNO (operands[3]))"
@@ -3867,6 +3878,7 @@
    (set (mem:DF (match_dup 0))
         (match_operand:DF 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && TARGET_64BIT
    && REG_OK_FOR_BASE_P (operands[2])
    && FP_REGNO_P (REGNO (operands[3]))"
@@ -3883,6 +3895,7 @@
    (set (mem:DF (match_dup 0))
         (match_operand:DF 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && REG_OK_FOR_BASE_P (operands[1])
    && (TARGET_NO_SPACE_REGS
        || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
@@ -3899,6 +3912,7 @@
    (set (mem:DF (match_dup 0))
         (match_operand:DF 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && REG_OK_FOR_BASE_P (operands[2])
    && (TARGET_NO_SPACE_REGS
        || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
@@ -3915,6 +3929,7 @@
    (set (mem:DF (match_dup 0))
         (match_operand:DF 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && TARGET_64BIT
    && REG_OK_FOR_BASE_P (operands[1])
    && (TARGET_NO_SPACE_REGS
@@ -3932,6 +3947,7 @@
    (set (mem:DF (match_dup 0))
         (match_operand:DF 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && TARGET_64BIT
    && REG_OK_FOR_BASE_P (operands[2])
    && (TARGET_NO_SPACE_REGS
@@ -4126,6 +4142,7 @@
    (set (mem:DI (match_dup 0))
         (match_operand:DI 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && TARGET_64BIT
    && REG_OK_FOR_BASE_P (operands[2])
    && FP_REGNO_P (REGNO (operands[3]))"
@@ -4143,6 +4160,7 @@
    (set (mem:DI (match_dup 0))
         (match_operand:DI 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && TARGET_64BIT
    && REG_OK_FOR_BASE_P (operands[2])
    && FP_REGNO_P (REGNO (operands[3]))"
@@ -4159,6 +4177,7 @@
    (set (mem:DI (match_dup 0))
         (match_operand:DI 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && TARGET_64BIT
    && REG_OK_FOR_BASE_P (operands[1])
    && (TARGET_NO_SPACE_REGS
@@ -4176,6 +4195,7 @@
    (set (mem:DI (match_dup 0))
         (match_operand:DI 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && TARGET_64BIT
    && REG_OK_FOR_BASE_P (operands[2])
    && (TARGET_NO_SPACE_REGS
@@ -4321,6 +4341,7 @@
    (set (mem:SF (match_dup 0))
         (match_operand:SF 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && REG_OK_FOR_BASE_P (operands[2])
    && FP_REGNO_P (REGNO (operands[3]))"
   [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
@@ -4337,6 +4358,7 @@
    (set (mem:SF (match_dup 0))
         (match_operand:SF 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && REG_OK_FOR_BASE_P (operands[2])
    && FP_REGNO_P (REGNO (operands[3]))"
   [(set (mem:SF (plus:SI (mult:SI (match_dup 1) (const_int 4)) (match_dup 2)))
@@ -4353,6 +4375,7 @@
    (set (mem:SF (match_dup 0))
         (match_operand:SF 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && TARGET_64BIT
    && REG_OK_FOR_BASE_P (operands[2])
    && FP_REGNO_P (REGNO (operands[3]))"
@@ -4370,6 +4393,7 @@
    (set (mem:SF (match_dup 0))
         (match_operand:SF 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && TARGET_64BIT
    && REG_OK_FOR_BASE_P (operands[2])
    && FP_REGNO_P (REGNO (operands[3]))"
@@ -4386,6 +4410,7 @@
    (set (mem:SF (match_dup 0))
         (match_operand:SF 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && REG_OK_FOR_BASE_P (operands[1])
    && (TARGET_NO_SPACE_REGS
        || (!REG_POINTER (operands[1]) && REG_POINTER (operands[2])))
@@ -4402,6 +4427,7 @@
    (set (mem:SF (match_dup 0))
         (match_operand:SF 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && REG_OK_FOR_BASE_P (operands[2])
    && (TARGET_NO_SPACE_REGS
        || (REG_POINTER (operands[1]) && !REG_POINTER (operands[2])))
@@ -4418,6 +4444,7 @@
    (set (mem:SF (match_dup 0))
         (match_operand:SF 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && TARGET_64BIT
    && REG_OK_FOR_BASE_P (operands[1])
    && (TARGET_NO_SPACE_REGS
@@ -4435,6 +4462,7 @@
    (set (mem:SF (match_dup 0))
         (match_operand:SF 3 "register_operand" ""))]
   "!TARGET_SOFT_FLOAT
+   && !TARGET_DISABLE_INDEXING
    && TARGET_64BIT
    && REG_OK_FOR_BASE_P (operands[2])
    && (TARGET_NO_SPACE_REGS
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