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[PATCH - ARM] fix peephole 2 patterns
- From: Richard Earnshaw <rearnsha at buzzard dot freeserve dot co dot uk>
- To: gcc-patches at gcc dot gnu dot org
- Cc: Richard dot Earnshaw at buzzard dot freeserve dot co dot uk
- Date: Fri, 14 May 2004 22:55:17 +0100
- Subject: [PATCH - ARM] fix peephole 2 patterns
- Reply-to: Richard dot Earnshaw at buzzard dot freeserve dot co dot uk
This patch fixes a particular bug caused by the peephole2 patterns
matching without taking register classes into consideration. The
particular instance that was failing was
(set (reg:SI 64 s1) (reg:SI 0 r0))
(set (reg:CC cc) (compare:CC (reg:SI 0 r0) (const_int 0)))
which peephole2 combined (incorrectly) a mov/compare instruction (subs ..
#0).
The peephole works fine if the target of the first insn is also a core
integer register, but it fails if using a VFP register as its target.
I've taken the opportunity to fix all the peephole2 patterns to prevent
things like this happening again in the future.
Tested on arm-elf. Installed on mainline and csl-arm-branch.
2004-05-14 Richard Earnshaw <rearnsha@arm.com>
* arm.md (all peephole2 patterns): Use predicates that validate
register classes as appropriate.
Index: config/arm/arm.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/arm/arm.md,v
retrieving revision 1.165
diff -p -p -r1.165 arm.md
*** config/arm/arm.md 5 May 2004 23:11:54 -0000 1.165
--- config/arm/arm.md 14 May 2004 21:42:38 -0000
***************
*** 466,473 ****
; addition.
(define_peephole2
[(match_scratch:SI 3 "r")
! (set (match_operand:SI 0 "s_register_operand" "")
! (plus:SI (match_operand:SI 1 "s_register_operand" "")
(match_operand:SI 2 "const_int_operand" "")))]
"TARGET_ARM &&
!(const_ok_for_arm (INTVAL (operands[2]))
--- 466,473 ----
; addition.
(define_peephole2
[(match_scratch:SI 3 "r")
! (set (match_operand:SI 0 "arm_general_register_operand" "")
! (plus:SI (match_operand:SI 1 "arm_general_register_operand" "")
(match_operand:SI 2 "const_int_operand" "")))]
"TARGET_ARM &&
!(const_ok_for_arm (INTVAL (operands[2]))
***************
*** 534,548 ****
;; Reloading and elimination of the frame pointer can
;; sometimes cause this optimization to be missed.
(define_peephole2
! [(set (match_operand:SI 0 "register_operand" "")
(match_operand:SI 1 "const_int_operand" ""))
(set (match_dup 0)
! (plus:SI (match_dup 0) (match_operand:SI 2 "register_operand" "")))]
"TARGET_THUMB
- && REGNO (operands[2]) == STACK_POINTER_REGNUM
&& (unsigned HOST_WIDE_INT) (INTVAL (operands[1])) < 1024
&& (INTVAL (operands[1]) & 3) == 0"
! [(set (match_dup 0) (plus:SI (match_dup 2) (match_dup 1)))]
""
)
--- 534,547 ----
;; Reloading and elimination of the frame pointer can
;; sometimes cause this optimization to be missed.
(define_peephole2
! [(set (match_operand:SI 0 "arm_general_register_operand" "")
(match_operand:SI 1 "const_int_operand" ""))
(set (match_dup 0)
! (plus:SI (match_dup 0) (reg:SI SP_REGNUM)))]
"TARGET_THUMB
&& (unsigned HOST_WIDE_INT) (INTVAL (operands[1])) < 1024
&& (INTVAL (operands[1]) & 3) == 0"
! [(set (match_dup 0) (plus:SI (reg:SI SP_REGNUM) (match_dup 1)))]
""
)
***************
*** 630,637 ****
;; similarly for the beq variant using bcc.
;; This is a common looping idiom (while (n--))
(define_peephole2
! [(set (match_operand:SI 0 "s_register_operand" "")
! (plus:SI (match_operand:SI 1 "s_register_operand" "")
(const_int -1)))
(set (match_operand 2 "cc_register" "")
(compare (match_dup 0) (const_int -1)))
--- 629,636 ----
;; similarly for the beq variant using bcc.
;; This is a common looping idiom (while (n--))
(define_peephole2
! [(set (match_operand:SI 0 "arm_general_register_operand" "")
! (plus:SI (match_operand:SI 1 "arm_general_register_operand" "")
(const_int -1)))
(set (match_operand 2 "cc_register" "")
(compare (match_dup 0) (const_int -1)))
***************
*** 986,994 ****
(define_peephole2
[(match_scratch:SI 3 "r")
! (set (match_operand:SI 0 "s_register_operand" "")
(minus:SI (match_operand:SI 1 "const_int_operand" "")
! (match_operand:SI 2 "s_register_operand" "")))]
"TARGET_ARM
&& !const_ok_for_arm (INTVAL (operands[1]))
&& const_ok_for_arm (~INTVAL (operands[1]))"
--- 985,993 ----
(define_peephole2
[(match_scratch:SI 3 "r")
! (set (match_operand:SI 0 "arm_general_register_operand" "")
(minus:SI (match_operand:SI 1 "const_int_operand" "")
! (match_operand:SI 2 "arm_general_register_operand" "")))]
"TARGET_ARM
&& !const_ok_for_arm (INTVAL (operands[1]))
&& const_ok_for_arm (~INTVAL (operands[1]))"
***************
*** 2116,2123 ****
(define_peephole2
[(match_scratch:SI 3 "r")
! (set (match_operand:SI 0 "s_register_operand" "")
! (ior:SI (match_operand:SI 1 "s_register_operand" "")
(match_operand:SI 2 "const_int_operand" "")))]
"TARGET_ARM
&& !const_ok_for_arm (INTVAL (operands[2]))
--- 2115,2122 ----
(define_peephole2
[(match_scratch:SI 3 "r")
! (set (match_operand:SI 0 "arm_general_register_operand" "")
! (ior:SI (match_operand:SI 1 "arm_general_register_operand" "")
(match_operand:SI 2 "const_int_operand" "")))]
"TARGET_ARM
&& !const_ok_for_arm (INTVAL (operands[2]))
***************
*** 9651,9665 ****
; This pattern is never tried by combine, so do it as a peephole
(define_peephole2
! [(set (match_operand:SI 0 "s_register_operand" "")
! (match_operand:SI 1 "s_register_operand" ""))
(set (reg:CC CC_REGNUM)
(compare:CC (match_dup 1) (const_int 0)))]
! "TARGET_ARM
! && (!(TARGET_HARD_FLOAT && TARGET_MAVERICK)
! || (!cirrus_fp_register (operands[0], SImode)
! && !cirrus_fp_register (operands[1], SImode)))
! "
[(parallel [(set (reg:CC CC_REGNUM) (compare:CC (match_dup 1) (const_int 0)))
(set (match_dup 0) (match_dup 1))])]
""
--- 9650,9660 ----
; This pattern is never tried by combine, so do it as a peephole
(define_peephole2
! [(set (match_operand:SI 0 "arm_general_register_operand" "")
! (match_operand:SI 1 "arm_general_register_operand" ""))
(set (reg:CC CC_REGNUM)
(compare:CC (match_dup 1) (const_int 0)))]
! "TARGET_ARM"
[(parallel [(set (reg:CC CC_REGNUM) (compare:CC (match_dup 1) (const_int 0)))
(set (match_dup 0) (match_dup 1))])]
""